2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 /*****************************\
25 Reset functions and helpers
26 \*****************************/
28 #include <asm/unaligned.h>
30 #include <linux/pci.h> /* To determine if a card is pci-e */
31 #include <linux/log2.h>
38 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
40 * @ah: the &struct ath5k_hw
41 * @channel: the currently set channel upon reset
43 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
44 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
46 * Since delta slope is floating point we split it on its exponent and
47 * mantissa and provide these values on hw.
49 * For more infos i think this patent is related
50 * http://www.freepatentsonline.com/7184495.html
52 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
53 struct ieee80211_channel *channel)
55 /* Get exponent and mantissa and set it */
56 u32 coef_scaled, coef_exp, coef_man,
57 ds_coef_exp, ds_coef_man, clock;
59 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
60 !(channel->hw_value & CHANNEL_OFDM));
63 * ALGO: coef = (5 * clock / carrier_freq) / 2
64 * we scale coef by shifting clock value by 24 for
65 * better precision since we use integers */
66 /* TODO: Half/quarter rate */
67 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
68 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
71 * ALGO: coef_exp = 14 - highest set bit position */
72 coef_exp = ilog2(coef_scaled);
74 /* Doesn't make sense if it's zero*/
75 if (!coef_scaled || !coef_exp)
78 /* Note: we've shifted coef_scaled by 24 */
79 coef_exp = 14 - (coef_exp - 24);
82 /* Get mantissa (significant digits)
83 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
84 coef_man = coef_scaled +
85 (1 << (24 - coef_exp - 1));
87 /* Calculate delta slope coefficient exponent
88 * and mantissa (remove scaling) and set them on hw */
89 ds_coef_man = coef_man >> (24 - coef_exp);
90 ds_coef_exp = coef_exp - 16;
92 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
93 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
94 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
95 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
102 * index into rates for control rates, we can set it up like this because
103 * this is only used for AR5212 and we know it supports G mode
105 static const unsigned int control_rates[] =
106 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
109 * ath5k_hw_write_rate_duration - fill rate code to duration table
111 * @ah: the &struct ath5k_hw
112 * @mode: one of enum ath5k_driver_mode
114 * Write the rate code to duration table upon hw reset. This is a helper for
115 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
116 * the hardware, based on current mode, for each rate. The rates which are
117 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
118 * different rate code so we write their value twice (one for long preample
119 * and one for short).
121 * Note: Band doesn't matter here, if we set the values for OFDM it works
122 * on both a and g modes. So all we have to do is set values for all g rates
123 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
124 * quarter rate mode, we need to use another set of bitrates (that's why we
125 * need the mode parameter) but we don't handle these proprietary modes yet.
127 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
130 struct ath5k_softc *sc = ah->ah_sc;
131 struct ieee80211_rate *rate;
134 /* Write rate duration table */
135 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
139 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
141 /* Set ACK timeout */
142 reg = AR5K_RATE_DUR(rate->hw_value);
144 /* An ACK frame consists of 10 bytes. If you add the FCS,
145 * which ieee80211_generic_frame_duration() adds,
146 * its 14 bytes. Note we use the control rate and not the
147 * actual rate for this rate. See mac80211 tx.c
148 * ieee80211_duration() for a brief description of
149 * what rate we should choose to TX ACKs. */
150 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
153 ath5k_hw_reg_write(ah, tx_time, reg);
155 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
159 * We're not distinguishing short preamble here,
160 * This is true, all we'll get is a longer value here
161 * which is not necessarilly bad. We could use
162 * export ieee80211_frame_duration() but that needs to be
163 * fixed first to be properly used by mac802111 drivers:
165 * - remove erp stuff and let the routine figure ofdm
167 * - remove passing argument ieee80211_local as
168 * drivers don't have access to it
169 * - move drivers using ieee80211_generic_frame_duration()
172 ath5k_hw_reg_write(ah, tx_time,
173 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
180 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
183 u32 mask = val ? val : ~0U;
185 ATH5K_TRACE(ah->ah_sc);
187 /* Read-and-clear RX Descriptor Pointer*/
188 ath5k_hw_reg_read(ah, AR5K_RXDP);
191 * Reset the device and wait until success
193 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
195 /* Wait at least 128 PCI clocks */
198 if (ah->ah_version == AR5K_AR5210) {
199 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
200 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
201 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
202 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
204 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
205 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
208 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
211 * Reset configuration register (for hw byte-swap). Note that this
212 * is only set for big endian. We do the necessary magic in
215 if ((val & AR5K_RESET_CTL_PCU) == 0)
216 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
224 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
225 bool set_chip, u16 sleep_duration)
230 ATH5K_TRACE(ah->ah_sc);
231 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
235 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
237 case AR5K_PM_NETWORK_SLEEP:
239 ath5k_hw_reg_write(ah,
240 AR5K_SLEEP_CTL_SLE_ALLOW |
244 staid |= AR5K_STA_ID1_PWR_SV;
247 case AR5K_PM_FULL_SLEEP:
249 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
252 staid |= AR5K_STA_ID1_PWR_SV;
257 staid &= ~AR5K_STA_ID1_PWR_SV;
262 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
264 /* If card is down we 'll get 0xffff... so we
265 * need to clean this up before we write the register
267 if (data & 0xffc00000)
270 /* Preserve sleep duration etc */
271 data = data & ~AR5K_SLEEP_CTL_SLE;
273 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
277 for (i = 200; i > 0; i--) {
278 /* Check if the chip did wake up */
279 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
280 AR5K_PCICFG_SPWR_DN) == 0)
283 /* Wait a bit and retry */
285 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
289 /* Fail if the chip didn't wake up */
300 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
308 * Put MAC and Baseband on warm reset and
309 * keep that state (don't clean sleep control
310 * register). After this MAC and Baseband are
311 * disabled and a full reset is needed to come
312 * back. This way we save as much power as possible
313 * without puting the card on full sleep.
315 int ath5k_hw_on_hold(struct ath5k_hw *ah)
317 struct pci_dev *pdev = ah->ah_sc->pdev;
321 /* Make sure device is awake */
322 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
324 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
329 * Put chipset on warm reset...
331 * Note: puting PCI core on warm reset on PCI-E cards
332 * results card to hang and always return 0xffff... so
333 * we ingore that flag for PCI-E cards. On PCI cards
334 * this flag gets cleared after 64 PCI clocks.
336 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
338 if (ah->ah_version == AR5K_AR5210) {
339 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
340 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
341 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
344 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
345 AR5K_RESET_CTL_BASEBAND | bus_flags);
349 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
353 /* ...wakeup again!*/
354 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
356 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
364 * Bring up MAC + PHY Chips and program PLL
365 * TODO: Half/Quarter rate support
367 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
369 struct pci_dev *pdev = ah->ah_sc->pdev;
370 u32 turbo, mode, clock, bus_flags;
377 ATH5K_TRACE(ah->ah_sc);
379 /* Wakeup the device */
380 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
382 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
387 * Put chipset on warm reset...
389 * Note: puting PCI core on warm reset on PCI-E cards
390 * results card to hang and always return 0xffff... so
391 * we ingore that flag for PCI-E cards. On PCI cards
392 * this flag gets cleared after 64 PCI clocks.
394 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
396 if (ah->ah_version == AR5K_AR5210) {
397 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
398 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
399 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
402 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
403 AR5K_RESET_CTL_BASEBAND | bus_flags);
407 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
411 /* ...wakeup again!...*/
412 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
414 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
418 /* ...clear reset control register and pull device out of
420 if (ath5k_hw_nic_reset(ah, 0)) {
421 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
425 /* On initialization skip PLL programming since we don't have
426 * a channel / mode set yet */
430 if (ah->ah_version != AR5K_AR5210) {
432 * Get channel mode flags
435 if (ah->ah_radio >= AR5K_RF5112) {
436 mode = AR5K_PHY_MODE_RAD_RF5112;
437 clock = AR5K_PHY_PLL_RF5112;
439 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
440 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
443 if (flags & CHANNEL_2GHZ) {
444 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
445 clock |= AR5K_PHY_PLL_44MHZ;
447 if (flags & CHANNEL_CCK) {
448 mode |= AR5K_PHY_MODE_MOD_CCK;
449 } else if (flags & CHANNEL_OFDM) {
450 /* XXX Dynamic OFDM/CCK is not supported by the
451 * AR5211 so we set MOD_OFDM for plain g (no
452 * CCK headers) operation. We need to test
453 * this, 5211 might support ofdm-only g after
454 * all, there are also initial register values
455 * in the code for g mode (see initvals.c). */
456 if (ah->ah_version == AR5K_AR5211)
457 mode |= AR5K_PHY_MODE_MOD_OFDM;
459 mode |= AR5K_PHY_MODE_MOD_DYN;
462 "invalid radio modulation mode\n");
465 } else if (flags & CHANNEL_5GHZ) {
466 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
468 if (ah->ah_radio == AR5K_RF5413)
469 clock = AR5K_PHY_PLL_40MHZ_5413;
471 clock |= AR5K_PHY_PLL_40MHZ;
473 if (flags & CHANNEL_OFDM)
474 mode |= AR5K_PHY_MODE_MOD_OFDM;
477 "invalid radio modulation mode\n");
481 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
485 if (flags & CHANNEL_TURBO)
486 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
487 } else { /* Reset the device */
489 /* ...enable Atheros turbo mode if requested */
490 if (flags & CHANNEL_TURBO)
491 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
495 if (ah->ah_version != AR5K_AR5210) {
497 /* ...update PLL if needed */
498 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
499 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
503 /* ...set the PHY operating mode */
504 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
505 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
512 * If there is an external 32KHz crystal available, use it
513 * as ref. clock instead of 32/40MHz clock and baseband clocks
514 * to save power during sleep or restore normal 32/40MHz
517 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
518 * 123 - 127) require delay on access.
520 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
522 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
523 u32 scal, spending, usec32;
525 /* Only set 32KHz settings if we have an external
526 * 32KHz crystal present */
527 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
528 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
532 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
533 /* Set up tsf increment on each cycle */
534 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
536 /* Set baseband sleep control registers
537 * and sleep control rate */
538 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
540 if ((ah->ah_radio == AR5K_RF5112) ||
541 (ah->ah_radio == AR5K_RF5413) ||
542 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
546 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
548 if ((ah->ah_radio == AR5K_RF5112) ||
549 (ah->ah_radio == AR5K_RF5413) ||
550 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
551 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
552 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
553 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
554 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
555 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
556 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
558 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
559 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
560 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
561 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
562 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
563 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
566 /* Enable sleep clock operation */
567 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
568 AR5K_PCICFG_SLEEP_CLOCK_EN);
572 /* Disable sleep clock operation and
573 * restore default parameters */
574 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
575 AR5K_PCICFG_SLEEP_CLOCK_EN);
577 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
578 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
580 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
581 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
583 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
584 scal = AR5K_PHY_SCAL_32MHZ_2417;
585 else if (ee->ee_is_hb63)
586 scal = AR5K_PHY_SCAL_32MHZ_HB63;
588 scal = AR5K_PHY_SCAL_32MHZ;
589 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
591 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
592 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
594 if ((ah->ah_radio == AR5K_RF5112) ||
595 (ah->ah_radio == AR5K_RF5413) ||
596 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
600 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
602 if ((ah->ah_radio == AR5K_RF5112) ||
603 (ah->ah_radio == AR5K_RF5413))
607 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
609 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
614 /* TODO: Half/Quarter rate */
615 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
616 struct ieee80211_channel *channel)
618 if (ah->ah_version == AR5K_AR5212 &&
619 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
621 /* Setup ADC control */
622 ath5k_hw_reg_write(ah,
624 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
626 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
627 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
628 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
633 /* Disable barker RSSI threshold */
634 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
635 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
637 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
638 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
640 /* Set the mute mask */
641 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
644 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
645 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
646 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
648 /* Enable DCU double buffering */
649 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
650 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
651 AR5K_TXCFG_DCU_DBL_BUF_DIS);
653 /* Set DAC/ADC delays */
654 if (ah->ah_version == AR5K_AR5212) {
656 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
657 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
658 scal = AR5K_PHY_SCAL_32MHZ_2417;
659 else if (ee->ee_is_hb63)
660 scal = AR5K_PHY_SCAL_32MHZ_HB63;
662 scal = AR5K_PHY_SCAL_32MHZ;
663 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
667 if ((ah->ah_radio == AR5K_RF5413) ||
668 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
671 if (channel->center_freq == 2462 ||
672 channel->center_freq == 2467)
675 /* Only update if needed */
676 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
677 ath5k_hw_reg_write(ah, fast_adc,
681 /* Fix for first revision of the RF5112 RF chipset */
682 if (ah->ah_radio == AR5K_RF5112 &&
683 ah->ah_radio_5ghz_revision <
684 AR5K_SREV_RAD_5112A) {
686 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
688 if (channel->hw_value & CHANNEL_5GHZ)
692 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
695 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
697 /* 5311 has different tx/rx latency masks
698 * from 5211, since we deal 5311 the same
699 * as 5211 when setting initvals, shift
700 * values here to their proper locations */
701 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
702 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
704 AR5K_USEC_TX_LATENCY_5211 |
706 AR5K_USEC_RX_LATENCY_5210)),
708 /* Clear QCU/DCU clock gating register */
709 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
710 /* Set DAC/ADC delays */
711 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
712 /* Enable PCU FIFO corruption ECO */
713 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
714 AR5K_DIAG_SW_ECO_ENABLE);
718 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
719 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode)
721 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
722 s16 cck_ofdm_pwr_delta;
724 /* Adjust power delta for channel 14 */
725 if (channel->center_freq == 2484)
727 ((ee->ee_cck_ofdm_power_delta -
728 ee->ee_scaled_cck_delta) * 2) / 10;
731 (ee->ee_cck_ofdm_power_delta * 2) / 10;
733 /* Set CCK to OFDM power delta on tx power
734 * adjustment register */
735 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
736 if (channel->hw_value == CHANNEL_G)
737 ath5k_hw_reg_write(ah,
738 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
739 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
740 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
741 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
742 AR5K_PHY_TX_PWR_ADJ);
744 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
746 /* For older revs we scale power on sw during tx power
748 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
749 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
750 ee->ee_cck_ofdm_gain_delta;
753 /* Set antenna idle switch table */
754 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
755 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
756 (ah->ah_ant_ctl[ee_mode][0] |
757 AR5K_PHY_ANT_CTL_TXRX_EN));
759 /* Set antenna switch tables */
760 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]],
761 AR5K_PHY_ANT_SWITCH_TABLE_0);
762 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]],
763 AR5K_PHY_ANT_SWITCH_TABLE_1);
765 /* Noise floor threshold */
766 ath5k_hw_reg_write(ah,
767 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
770 if ((channel->hw_value & CHANNEL_TURBO) &&
771 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
772 /* Switch settling time (Turbo) */
773 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
774 AR5K_PHY_SETTLING_SWITCH,
775 ee->ee_switch_settling_turbo[ee_mode]);
777 /* Tx/Rx attenuation (Turbo) */
778 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
779 AR5K_PHY_GAIN_TXRX_ATTEN,
780 ee->ee_atn_tx_rx_turbo[ee_mode]);
782 /* ADC/PGA desired size (Turbo) */
783 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
784 AR5K_PHY_DESIRED_SIZE_ADC,
785 ee->ee_adc_desired_size_turbo[ee_mode]);
787 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
788 AR5K_PHY_DESIRED_SIZE_PGA,
789 ee->ee_pga_desired_size_turbo[ee_mode]);
791 /* Tx/Rx margin (Turbo) */
792 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
793 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
794 ee->ee_margin_tx_rx_turbo[ee_mode]);
797 /* Switch settling time */
798 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
799 AR5K_PHY_SETTLING_SWITCH,
800 ee->ee_switch_settling[ee_mode]);
802 /* Tx/Rx attenuation */
803 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
804 AR5K_PHY_GAIN_TXRX_ATTEN,
805 ee->ee_atn_tx_rx[ee_mode]);
807 /* ADC/PGA desired size */
808 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
809 AR5K_PHY_DESIRED_SIZE_ADC,
810 ee->ee_adc_desired_size[ee_mode]);
812 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
813 AR5K_PHY_DESIRED_SIZE_PGA,
814 ee->ee_pga_desired_size[ee_mode]);
817 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
818 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
819 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
820 ee->ee_margin_tx_rx[ee_mode]);
824 ath5k_hw_reg_write(ah,
825 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
826 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
827 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
828 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
831 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
832 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
833 ee->ee_tx_end2xlna_enable[ee_mode]);
836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
837 AR5K_PHY_NF_THRESH62,
838 ee->ee_thr_62[ee_mode]);
841 /* False detect backoff for channels
842 * that have spur noise. Write the new
843 * cyclic power RSSI threshold. */
844 if (ath5k_hw_chan_has_spur_noise(ah, channel))
845 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
846 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
847 AR5K_INIT_CYCRSSI_THR1 +
848 ee->ee_false_detect[ee_mode]);
850 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
851 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
852 AR5K_INIT_CYCRSSI_THR1);
854 /* I/Q correction (set enable bit last to match HAL sources) */
855 /* TODO: Per channel i/q infos ? */
856 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
858 ee->ee_i_cal[ee_mode]);
859 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
860 ee->ee_q_cal[ee_mode]);
861 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
864 /* Heavy clipping -disable for now */
865 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
866 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
872 * Main reset function
874 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
875 struct ieee80211_channel *channel, bool change_channel)
877 struct ath_common *common = ath5k_hw_common(ah);
878 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo;
880 u8 mode, freq, ee_mode, ant[2];
883 ATH5K_TRACE(ah->ah_sc);
894 * Save some registers before a reset
896 /*DCU/Antenna selection not available on 5210*/
897 if (ah->ah_version != AR5K_AR5210) {
899 switch (channel->hw_value & CHANNEL_MODES) {
901 mode = AR5K_MODE_11A;
902 freq = AR5K_INI_RFGAIN_5GHZ;
903 ee_mode = AR5K_EEPROM_MODE_11A;
906 mode = AR5K_MODE_11G;
907 freq = AR5K_INI_RFGAIN_2GHZ;
908 ee_mode = AR5K_EEPROM_MODE_11G;
911 mode = AR5K_MODE_11B;
912 freq = AR5K_INI_RFGAIN_2GHZ;
913 ee_mode = AR5K_EEPROM_MODE_11B;
916 mode = AR5K_MODE_11A_TURBO;
917 freq = AR5K_INI_RFGAIN_5GHZ;
918 ee_mode = AR5K_EEPROM_MODE_11A;
921 if (ah->ah_version == AR5K_AR5211) {
923 "TurboG mode not available on 5211");
926 mode = AR5K_MODE_11G_TURBO;
927 freq = AR5K_INI_RFGAIN_2GHZ;
928 ee_mode = AR5K_EEPROM_MODE_11G;
931 if (ah->ah_version == AR5K_AR5211) {
933 "XR mode not available on 5211");
937 freq = AR5K_INI_RFGAIN_5GHZ;
938 ee_mode = AR5K_EEPROM_MODE_11A;
942 "invalid channel: %d\n", channel->center_freq);
946 if (change_channel) {
948 * Save frame sequence count
949 * For revs. after Oahu, only save
950 * seq num for DCU 0 (Global seq num)
952 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
954 for (i = 0; i < 10; i++)
955 s_seq[i] = ath5k_hw_reg_read(ah,
956 AR5K_QUEUE_DCU_SEQNUM(i));
959 s_seq[0] = ath5k_hw_reg_read(ah,
960 AR5K_QUEUE_DCU_SEQNUM(0));
963 /* TSF accelerates on AR5211 durring reset
964 * As a workaround save it here and restore
965 * it later so that it's back in time after
966 * reset. This way it'll get re-synced on the
967 * next beacon without breaking ad-hoc.
969 * On AR5212 TSF is almost preserved across a
970 * reset so it stays back in time anyway and
971 * we don't have to save/restore it.
973 * XXX: Since this breaks power saving we have
974 * to disable power saving until we receive the
975 * next beacon, so we can resync beacon timers */
976 if (ah->ah_version == AR5K_AR5211) {
977 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
978 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
982 /* Save default antenna */
983 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
985 if (ah->ah_version == AR5K_AR5212) {
986 /* Restore normal 32/40MHz clock operation
987 * to avoid register access delay on certain
989 ath5k_hw_set_sleep_clock(ah, false);
991 /* Since we are going to write rf buffer
992 * check if we have any pending gain_F
993 * optimization settings */
994 if (change_channel && ah->ah_rf_banks != NULL)
995 ath5k_hw_gainf_calibrate(ah);
1000 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1001 AR5K_PCICFG_LEDSTATE;
1002 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1003 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1005 /* AR5K_STA_ID1 flags, only preserve antenna
1006 * settings and ack/cts rate mode */
1007 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
1008 (AR5K_STA_ID1_DEFAULT_ANTENNA |
1009 AR5K_STA_ID1_DESC_ANTENNA |
1010 AR5K_STA_ID1_RTS_DEF_ANTENNA |
1011 AR5K_STA_ID1_ACKCTS_6MB |
1012 AR5K_STA_ID1_BASE_RATE_11B |
1013 AR5K_STA_ID1_SELFGEN_DEF_ANT);
1015 /* Wakeup the device */
1016 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1021 * Initialize operating mode
1023 ah->ah_op_mode = op_mode;
1025 /* PHY access enable */
1026 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1027 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1029 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1032 /* Write initial settings */
1033 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
1038 * 5211/5212 Specific
1040 if (ah->ah_version != AR5K_AR5210) {
1043 * Write initial RF gain settings
1044 * This should work for both 5111/5112
1046 ret = ath5k_hw_rfgain_init(ah, freq);
1053 * Tweak initval settings for revised
1054 * chipsets and add some more config
1057 ath5k_hw_tweak_initval_settings(ah, channel);
1062 ret = ath5k_hw_txpower(ah, channel, ee_mode,
1063 ah->ah_txpower.txp_max_pwr / 2);
1067 /* Write rate duration table only on AR5212 and if
1068 * virtual interface has already been brought up
1069 * XXX: rethink this after new mode changes to
1070 * mac80211 are integrated */
1071 if (ah->ah_version == AR5K_AR5212 &&
1072 ah->ah_sc->vif != NULL)
1073 ath5k_hw_write_rate_duration(ah, mode);
1078 ret = ath5k_hw_rfregs_init(ah, channel, mode);
1083 /* Write OFDM timings on 5212*/
1084 if (ah->ah_version == AR5K_AR5212 &&
1085 channel->hw_value & CHANNEL_OFDM) {
1086 struct ath5k_eeprom_info *ee =
1087 &ah->ah_capabilities.cap_eeprom;
1089 ret = ath5k_hw_write_ofdm_timings(ah, channel);
1093 /* Note: According to docs we can have a newer
1094 * EEPROM on old hardware, so we need to verify
1095 * that our hardware is new enough to have spur
1096 * mitigation registers (delta phase etc) */
1097 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 ||
1098 (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1099 ee->ee_version >= AR5K_EEPROM_VERSION_5_3))
1100 ath5k_hw_set_spur_mitigation_filter(ah,
1104 /*Enable/disable 802.11b mode on 5111
1105 (enable 2111 frequency converter + CCK)*/
1106 if (ah->ah_radio == AR5K_RF5111) {
1107 if (mode == AR5K_MODE_11B)
1108 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
1111 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
1116 * In case a fixed antenna was set as default
1117 * use the same switch table twice.
1119 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1120 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A;
1121 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1122 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B;
1124 ant[0] = AR5K_ANT_SWTABLE_A;
1125 ant[1] = AR5K_ANT_SWTABLE_B;
1128 /* Commit values from EEPROM */
1129 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);
1133 * For 5210 we do all initialization using
1134 * initvals, so we don't have to modify
1135 * any settings (5210 also only supports
1139 /* Disable phy and wait */
1140 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1145 * Restore saved values
1148 /*DCU/Antenna selection not available on 5210*/
1149 if (ah->ah_version != AR5K_AR5210) {
1151 if (change_channel) {
1152 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1153 for (i = 0; i < 10; i++)
1154 ath5k_hw_reg_write(ah, s_seq[i],
1155 AR5K_QUEUE_DCU_SEQNUM(i));
1157 ath5k_hw_reg_write(ah, s_seq[0],
1158 AR5K_QUEUE_DCU_SEQNUM(0));
1162 if (ah->ah_version == AR5K_AR5211) {
1163 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1164 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1168 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
1172 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1175 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1176 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1178 /* Restore sta_id flags and preserve our mac address*/
1179 ath5k_hw_reg_write(ah,
1180 get_unaligned_le32(common->macaddr),
1182 ath5k_hw_reg_write(ah,
1183 staid1_flags | get_unaligned_le16(common->macaddr + 4),
1191 /* Restore bssid and bssid mask */
1192 ath5k_hw_set_associd(ah);
1194 /* Set PCU config */
1195 ath5k_hw_set_opmode(ah);
1197 /* Clear any pending interrupts
1198 * PISR/SISR Not available on 5210 */
1199 if (ah->ah_version != AR5K_AR5210)
1200 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1202 /* Set RSSI/BRSSI thresholds
1204 * Note: If we decide to set this value
1205 * dynamicaly, have in mind that when AR5K_RSSI_THR
1206 * register is read it might return 0x40 if we haven't
1207 * wrote anything to it plus BMISS RSSI threshold is zeroed.
1208 * So doing a save/restore procedure here isn't the right
1209 * choice. Instead store it on ath5k_hw */
1210 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1211 AR5K_TUNE_BMISS_THRES <<
1212 AR5K_RSSI_THR_BMISS_S),
1215 /* MIC QoS support */
1216 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1217 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
1218 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
1221 /* QoS NOACK Policy */
1222 if (ah->ah_version == AR5K_AR5212) {
1223 ath5k_hw_reg_write(ah,
1224 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
1225 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
1226 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
1235 /* Set channel on PHY */
1236 ret = ath5k_hw_channel(ah, channel);
1241 * Enable the PHY and wait until completion
1242 * This includes BaseBand and Synthesizer
1245 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1248 * On 5211+ read activation -> rx delay
1251 * TODO: Half/quarter rate support
1253 if (ah->ah_version != AR5K_AR5210) {
1255 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1256 AR5K_PHY_RX_DELAY_M;
1257 delay = (channel->hw_value & CHANNEL_CCK) ?
1258 ((delay << 2) / 22) : (delay / 10);
1260 udelay(100 + (2 * delay));
1266 * Perform ADC test to see if baseband is ready
1267 * Set tx hold and check adc test register
1269 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1270 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1271 for (i = 0; i <= 20; i++) {
1272 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1276 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1279 * Start automatic gain control calibration
1281 * During AGC calibration RX path is re-routed to
1282 * a power detector so we don't receive anything.
1284 * This method is used to calibrate some static offsets
1285 * used together with on-the fly I/Q calibration (the
1286 * one performed via ath5k_hw_phy_calibrate), that doesn't
1287 * interrupt rx path.
1289 * While rx path is re-routed to the power detector we also
1290 * start a noise floor calibration, to measure the
1291 * card's noise floor (the noise we measure when we are not
1292 * transmiting or receiving anything).
1294 * If we are in a noisy environment AGC calibration may time
1295 * out and/or noise floor calibration might timeout.
1297 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1298 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
1300 /* At the same time start I/Q calibration for QAM constellation
1301 * -no need for CCK- */
1302 ah->ah_calibration = false;
1303 if (!(mode == AR5K_MODE_11B)) {
1304 ah->ah_calibration = true;
1305 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1306 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1307 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1311 /* Wait for gain calibration to finish (we check for I/Q calibration
1312 * during ath5k_phy_calibrate) */
1313 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1314 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1315 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1316 channel->center_freq);
1319 /* Restore antenna mode */
1320 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
1322 /* Restore slot time and ACK timeouts */
1323 if (ah->ah_coverage_class > 0)
1324 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1327 * Configure QCUs/DCUs
1330 /* TODO: HW Compression support for data queues */
1331 /* TODO: Burst prefetch for data queues */
1334 * Reset queues and start beacon timers at the end of the reset routine
1335 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1336 * Note: If we want we can assign multiple qcus on one dcu.
1338 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1339 ret = ath5k_hw_reset_tx_queue(ah, i);
1341 ATH5K_ERR(ah->ah_sc,
1342 "failed to reset TX queue #%d\n", i);
1349 * Configure DMA/Interrupts
1353 * Set Rx/Tx DMA Configuration
1355 * Set standard DMA size (128). Note that
1356 * a DMA size of 512 causes rx overruns and tx errors
1357 * on pci-e cards (tested on 5424 but since rx overruns
1358 * also occur on 5416/5418 with madwifi we set 128
1359 * for all PCI-E cards to be safe).
1361 * XXX: need to check 5210 for this
1362 * TODO: Check out tx triger level, it's always 64 on dumps but I
1363 * guess we can tweak it and see how it goes ;-)
1365 if (ah->ah_version != AR5K_AR5210) {
1366 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1367 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
1368 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1369 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
1372 /* Pre-enable interrupts on 5211/5212*/
1373 if (ah->ah_version != AR5K_AR5210)
1374 ath5k_hw_set_imr(ah, ah->ah_imr);
1376 /* Enable 32KHz clock function for AR5212+ chips
1377 * Set clocks to 32KHz operation and use an
1378 * external 32KHz crystal when sleeping if one
1380 if (ah->ah_version == AR5K_AR5212 &&
1381 ah->ah_op_mode != NL80211_IFTYPE_AP)
1382 ath5k_hw_set_sleep_clock(ah, true);
1385 * Disable beacons and reset the TSF
1387 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1388 ath5k_hw_reset_tsf(ah);