2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "ar9002_phy.h"
21 #define AR9285_CLCAL_REDO_THRESH 1
23 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
24 struct ath9k_cal_list *currCal)
26 struct ath_common *common = ath9k_hw_common(ah);
28 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
29 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
30 currCal->calData->calCountMax);
32 switch (currCal->calData->calType) {
34 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
35 ath_print(common, ATH_DBG_CALIBRATE,
36 "starting IQ Mismatch Calibration\n");
39 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
40 ath_print(common, ATH_DBG_CALIBRATE,
41 "starting ADC Gain Calibration\n");
44 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
45 ath_print(common, ATH_DBG_CALIBRATE,
46 "starting ADC DC Calibration\n");
49 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
50 ath_print(common, ATH_DBG_CALIBRATE,
51 "starting Init ADC DC Calibration\n");
54 break; /* Not supported */
57 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
58 AR_PHY_TIMING_CTRL4_DO_CAL);
61 static bool ar9002_hw_per_calibration(struct ath_hw *ah,
62 struct ath9k_channel *ichan,
64 struct ath9k_cal_list *currCal)
66 struct ath9k_hw_cal_data *caldata = ah->caldata;
67 bool iscaldone = false;
69 if (currCal->calState == CAL_RUNNING) {
70 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
71 AR_PHY_TIMING_CTRL4_DO_CAL)) {
73 currCal->calData->calCollect(ah);
76 if (ah->cal_samples >=
77 currCal->calData->calNumSamples) {
79 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
80 if (rxchainmask & (1 << i))
84 currCal->calData->calPostProc(ah, numChains);
85 caldata->CalValid |= currCal->calData->calType;
86 currCal->calState = CAL_DONE;
89 ar9002_hw_setup_calibration(ah, currCal);
92 } else if (!(caldata->CalValid & currCal->calData->calType)) {
93 ath9k_hw_reset_calibration(ah, currCal);
99 /* Assumes you are talking about the currently configured channel */
100 static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
101 enum ath9k_cal_types calType)
103 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
105 switch (calType & ah->supp_cals) {
106 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
110 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
118 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
122 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
123 ah->totalPowerMeasI[i] +=
124 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
125 ah->totalPowerMeasQ[i] +=
126 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
127 ah->totalIqCorrMeas[i] +=
128 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
129 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
130 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
131 ah->cal_samples, i, ah->totalPowerMeasI[i],
132 ah->totalPowerMeasQ[i],
133 ah->totalIqCorrMeas[i]);
137 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
141 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
142 ah->totalAdcIOddPhase[i] +=
143 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
144 ah->totalAdcIEvenPhase[i] +=
145 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
146 ah->totalAdcQOddPhase[i] +=
147 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
148 ah->totalAdcQEvenPhase[i] +=
149 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
151 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
152 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
153 "oddq=0x%08x; evenq=0x%08x;\n",
155 ah->totalAdcIOddPhase[i],
156 ah->totalAdcIEvenPhase[i],
157 ah->totalAdcQOddPhase[i],
158 ah->totalAdcQEvenPhase[i]);
162 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
166 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
167 ah->totalAdcDcOffsetIOddPhase[i] +=
168 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
169 ah->totalAdcDcOffsetIEvenPhase[i] +=
170 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
171 ah->totalAdcDcOffsetQOddPhase[i] +=
172 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
173 ah->totalAdcDcOffsetQEvenPhase[i] +=
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
176 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
177 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
178 "oddq=0x%08x; evenq=0x%08x;\n",
180 ah->totalAdcDcOffsetIOddPhase[i],
181 ah->totalAdcDcOffsetIEvenPhase[i],
182 ah->totalAdcDcOffsetQOddPhase[i],
183 ah->totalAdcDcOffsetQEvenPhase[i]);
187 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
189 struct ath_common *common = ath9k_hw_common(ah);
190 u32 powerMeasQ, powerMeasI, iqCorrMeas;
191 u32 qCoffDenom, iCoffDenom;
192 int32_t qCoff, iCoff;
195 for (i = 0; i < numChains; i++) {
196 powerMeasI = ah->totalPowerMeasI[i];
197 powerMeasQ = ah->totalPowerMeasQ[i];
198 iqCorrMeas = ah->totalIqCorrMeas[i];
200 ath_print(common, ATH_DBG_CALIBRATE,
201 "Starting IQ Cal and Correction for Chain %d\n",
204 ath_print(common, ATH_DBG_CALIBRATE,
205 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
206 i, ah->totalIqCorrMeas[i]);
210 if (iqCorrMeas > 0x80000000) {
211 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
215 ath_print(common, ATH_DBG_CALIBRATE,
216 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
217 ath_print(common, ATH_DBG_CALIBRATE,
218 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
219 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
222 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
223 qCoffDenom = powerMeasQ / 64;
225 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
227 iCoff = iqCorrMeas / iCoffDenom;
228 qCoff = powerMeasI / qCoffDenom - 64;
229 ath_print(common, ATH_DBG_CALIBRATE,
230 "Chn %d iCoff = 0x%08x\n", i, iCoff);
231 ath_print(common, ATH_DBG_CALIBRATE,
232 "Chn %d qCoff = 0x%08x\n", i, qCoff);
234 iCoff = iCoff & 0x3f;
235 ath_print(common, ATH_DBG_CALIBRATE,
236 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
237 if (iqCorrNeg == 0x0)
238 iCoff = 0x40 - iCoff;
242 else if (qCoff <= -16)
245 ath_print(common, ATH_DBG_CALIBRATE,
246 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
249 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
250 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
252 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
253 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
255 ath_print(common, ATH_DBG_CALIBRATE,
256 "IQ Cal and Correction done for Chain %d\n",
261 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
262 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
265 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
267 struct ath_common *common = ath9k_hw_common(ah);
268 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
269 u32 qGainMismatch, iGainMismatch, val, i;
271 for (i = 0; i < numChains; i++) {
272 iOddMeasOffset = ah->totalAdcIOddPhase[i];
273 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
274 qOddMeasOffset = ah->totalAdcQOddPhase[i];
275 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
277 ath_print(common, ATH_DBG_CALIBRATE,
278 "Starting ADC Gain Cal for Chain %d\n", i);
280 ath_print(common, ATH_DBG_CALIBRATE,
281 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
283 ath_print(common, ATH_DBG_CALIBRATE,
284 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
286 ath_print(common, ATH_DBG_CALIBRATE,
287 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
289 ath_print(common, ATH_DBG_CALIBRATE,
290 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
293 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
295 ((iEvenMeasOffset * 32) /
296 iOddMeasOffset) & 0x3f;
298 ((qOddMeasOffset * 32) /
299 qEvenMeasOffset) & 0x3f;
301 ath_print(common, ATH_DBG_CALIBRATE,
302 "Chn %d gain_mismatch_i = 0x%08x\n", i,
304 ath_print(common, ATH_DBG_CALIBRATE,
305 "Chn %d gain_mismatch_q = 0x%08x\n", i,
308 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
310 val |= (qGainMismatch) | (iGainMismatch << 6);
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
313 ath_print(common, ATH_DBG_CALIBRATE,
314 "ADC Gain Cal done for Chain %d\n", i);
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
319 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
320 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
323 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
325 struct ath_common *common = ath9k_hw_common(ah);
326 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
327 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
328 const struct ath9k_percal_data *calData =
329 ah->cal_list_curr->calData;
331 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
333 for (i = 0; i < numChains; i++) {
334 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
335 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
336 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
337 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
339 ath_print(common, ATH_DBG_CALIBRATE,
340 "Starting ADC DC Offset Cal for Chain %d\n", i);
342 ath_print(common, ATH_DBG_CALIBRATE,
343 "Chn %d pwr_meas_odd_i = %d\n", i,
345 ath_print(common, ATH_DBG_CALIBRATE,
346 "Chn %d pwr_meas_even_i = %d\n", i,
348 ath_print(common, ATH_DBG_CALIBRATE,
349 "Chn %d pwr_meas_odd_q = %d\n", i,
351 ath_print(common, ATH_DBG_CALIBRATE,
352 "Chn %d pwr_meas_even_q = %d\n", i,
355 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
357 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
360 ath_print(common, ATH_DBG_CALIBRATE,
361 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
363 ath_print(common, ATH_DBG_CALIBRATE,
364 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
367 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
369 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
370 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
372 ath_print(common, ATH_DBG_CALIBRATE,
373 "ADC DC Offset Cal done for Chain %d\n", i);
376 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
377 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
378 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
381 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
384 int32_t delta, currPDADC, slope;
386 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
387 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
389 if (ah->initPDADC == 0 || currPDADC == 0) {
391 * Zero value indicates that no frames have been transmitted
392 * yet, can't do temperature compensation until frames are
397 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
399 if (slope == 0) { /* to avoid divide by zero case */
402 delta = ((currPDADC - ah->initPDADC)*4) / slope;
404 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
405 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
406 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
407 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
411 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
414 int delta, currPDADC, regval;
416 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
417 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
419 if (ah->initPDADC == 0 || currPDADC == 0)
422 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
423 delta = (currPDADC - ah->initPDADC + 4) / 8;
425 delta = (currPDADC - ah->initPDADC + 5) / 10;
427 if (delta != ah->PDADCdelta) {
428 ah->PDADCdelta = delta;
429 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
430 regval = ah->originalGain[i] - delta;
435 AR_PHY_TX_GAIN_TBL1 + i * 4,
436 AR_PHY_TX_GAIN, regval);
441 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
456 for (i = 0; i < ARRAY_SIZE(regList); i++)
457 regList[i][1] = REG_READ(ah, regList[i][0]);
459 regVal = REG_READ(ah, 0x7834);
461 REG_WRITE(ah, 0x7834, regVal);
462 regVal = REG_READ(ah, 0x9808);
463 regVal |= (0x1 << 27);
464 REG_WRITE(ah, 0x9808, regVal);
466 /* 786c,b23,1, pwddac=1 */
467 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
468 /* 7854, b5,1, pdrxtxbb=1 */
469 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
470 /* 7854, b7,1, pdv2i=1 */
471 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
472 /* 7854, b8,1, pddacinterface=1 */
473 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
474 /* 7824,b12,0, offcal=0 */
475 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
476 /* 7838, b1,0, pwddb=0 */
477 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
478 /* 7820,b11,0, enpacal=0 */
479 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
480 /* 7820,b25,1, pdpadrv1=0 */
481 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
482 /* 7820,b24,0, pdpadrv2=0 */
483 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
484 /* 7820,b23,0, pdpaout=0 */
485 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
486 /* 783c,b14-16,7, padrvgn2tab_0=7 */
487 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
489 * 7838,b29-31,0, padrvgn1tab_0=0
490 * does not matter since we turn it off
492 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
494 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
497 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
498 * txon=1,paon=1,oscon=1,synthon_force=1
500 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
502 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
505 for (i = 6; i > 0; i--) {
506 regVal = REG_READ(ah, 0x7834);
507 regVal |= (1 << (20 + i));
508 REG_WRITE(ah, 0x7834, regVal);
510 /* regVal = REG_READ(ah, 0x7834); */
511 regVal &= (~(0x1 << (20 + i)));
512 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
514 REG_WRITE(ah, 0x7834, regVal);
517 regVal = (regVal >> 20) & 0x7f;
519 /* Update PA cal info */
520 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
521 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
522 ah->pacal_info.max_skipcount =
523 2 * ah->pacal_info.max_skipcount;
524 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
526 ah->pacal_info.max_skipcount = 1;
527 ah->pacal_info.skipcount = 0;
528 ah->pacal_info.prev_offset = regVal;
531 ENABLE_REGWRITE_BUFFER(ah);
533 regVal = REG_READ(ah, 0x7834);
535 REG_WRITE(ah, 0x7834, regVal);
536 regVal = REG_READ(ah, 0x9808);
537 regVal &= (~(0x1 << 27));
538 REG_WRITE(ah, 0x9808, regVal);
540 for (i = 0; i < ARRAY_SIZE(regList); i++)
541 REG_WRITE(ah, regList[i][0], regList[i][1]);
543 REGWRITE_BUFFER_FLUSH(ah);
544 DISABLE_REGWRITE_BUFFER(ah);
547 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
549 struct ath_common *common = ath9k_hw_common(ah);
551 int i, offset, offs_6_1, offs_0;
552 u32 ccomp_org, reg_field;
563 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
565 /* PA CAL is not needed for high power solution */
566 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
567 AR5416_EEP_TXGAIN_HIGH_POWER)
570 for (i = 0; i < ARRAY_SIZE(regList); i++)
571 regList[i][1] = REG_READ(ah, regList[i][0]);
573 regVal = REG_READ(ah, 0x7834);
575 REG_WRITE(ah, 0x7834, regVal);
576 regVal = REG_READ(ah, 0x9808);
577 regVal |= (0x1 << 27);
578 REG_WRITE(ah, 0x9808, regVal);
580 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
581 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
582 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
583 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
584 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
585 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
586 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
587 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
588 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
589 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
590 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
591 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
592 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
593 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
595 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
597 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
598 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
600 for (i = 6; i > 0; i--) {
601 regVal = REG_READ(ah, 0x7834);
602 regVal |= (1 << (19 + i));
603 REG_WRITE(ah, 0x7834, regVal);
605 regVal = REG_READ(ah, 0x7834);
606 regVal &= (~(0x1 << (19 + i)));
607 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
608 regVal |= (reg_field << (19 + i));
609 REG_WRITE(ah, 0x7834, regVal);
612 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
614 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
615 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
616 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
617 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
619 offset = (offs_6_1<<1) | offs_0;
621 offs_6_1 = offset>>1;
624 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
625 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
626 ah->pacal_info.max_skipcount =
627 2 * ah->pacal_info.max_skipcount;
628 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
630 ah->pacal_info.max_skipcount = 1;
631 ah->pacal_info.skipcount = 0;
632 ah->pacal_info.prev_offset = offset;
635 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
636 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
638 regVal = REG_READ(ah, 0x7834);
640 REG_WRITE(ah, 0x7834, regVal);
641 regVal = REG_READ(ah, 0x9808);
642 regVal &= (~(0x1 << 27));
643 REG_WRITE(ah, 0x9808, regVal);
645 for (i = 0; i < ARRAY_SIZE(regList); i++)
646 REG_WRITE(ah, regList[i][0], regList[i][1]);
648 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
651 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
653 if (AR_SREV_9271(ah)) {
654 if (is_reset || !ah->pacal_info.skipcount)
655 ar9271_hw_pa_cal(ah, is_reset);
657 ah->pacal_info.skipcount--;
658 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
659 if (is_reset || !ah->pacal_info.skipcount)
660 ar9285_hw_pa_cal(ah, is_reset);
662 ah->pacal_info.skipcount--;
666 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
668 if (OLC_FOR_AR9287_10_LATER)
669 ar9287_hw_olc_temp_compensation(ah);
670 else if (OLC_FOR_AR9280_20_LATER)
671 ar9280_hw_olc_temp_compensation(ah);
674 static bool ar9002_hw_calibrate(struct ath_hw *ah,
675 struct ath9k_channel *chan,
679 bool iscaldone = true;
680 struct ath9k_cal_list *currCal = ah->cal_list_curr;
681 bool nfcal, nfcal_pending = false;
683 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
685 nfcal_pending = ah->caldata->nfcal_pending;
687 if (currCal && !nfcal &&
688 (currCal->calState == CAL_RUNNING ||
689 currCal->calState == CAL_WAITING)) {
690 iscaldone = ar9002_hw_per_calibration(ah, chan,
691 rxchainmask, currCal);
693 ah->cal_list_curr = currCal = currCal->calNext;
695 if (currCal->calState == CAL_WAITING) {
697 ath9k_hw_reset_calibration(ah, currCal);
702 /* Do NF cal only at longer intervals */
703 if (longcal || nfcal_pending) {
704 /* Do periodic PAOffset Cal */
705 ar9002_hw_pa_cal(ah, false);
706 ar9002_hw_olc_temp_compensation(ah);
709 * Get the value from the previous NF cal and update
712 if (ath9k_hw_getnf(ah, chan)) {
714 * Load the NF from history buffer of the current
716 * NF is slow time-variant, so it is OK to use a
719 ath9k_hw_loadnf(ah, ah->curchan);
723 ath9k_hw_start_nfcal(ah, false);
729 /* Carrier leakage Calibration fix */
730 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
732 struct ath_common *common = ath9k_hw_common(ah);
734 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
735 if (IS_CHAN_HT20(chan)) {
736 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
737 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
738 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
739 AR_PHY_AGC_CONTROL_FLTR_CAL);
740 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
741 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
742 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
743 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
744 ath_print(common, ATH_DBG_CALIBRATE, "offset "
745 "calibration failed to complete in "
749 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
750 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
751 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
753 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
754 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
755 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
756 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
757 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
758 0, AH_WAIT_TIMEOUT)) {
759 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
760 "failed to complete in 1ms; noisy ??\n");
764 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
765 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
766 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
771 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
774 u_int32_t txgain_max;
775 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
776 u_int32_t reg_clc_I0, reg_clc_Q0;
777 u_int32_t i0_num = 0;
778 u_int32_t q0_num = 0;
779 u_int32_t total_num = 0;
780 u_int32_t reg_rf2g5_org;
783 if (!(ar9285_hw_cl_cal(ah, chan)))
786 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
787 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
789 for (i = 0; i < (txgain_max+1); i++) {
790 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
791 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
792 if (!(gain_mask & (1 << clc_gain))) {
793 gain_mask |= (1 << clc_gain);
798 for (i = 0; i < clc_num; i++) {
799 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
800 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
801 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
802 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
809 total_num = i0_num + q0_num;
810 if (total_num > AR9285_CLCAL_REDO_THRESH) {
811 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
812 if (AR_SREV_9285E_20(ah)) {
813 REG_WRITE(ah, AR9285_RF2G5,
814 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
815 AR9285_RF2G5_IC50TX_XE_SET);
817 REG_WRITE(ah, AR9285_RF2G5,
818 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
819 AR9285_RF2G5_IC50TX_SET);
821 retv = ar9285_hw_cl_cal(ah, chan);
822 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
827 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
829 struct ath_common *common = ath9k_hw_common(ah);
831 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
832 if (!ar9285_hw_clc(ah, chan))
835 if (AR_SREV_9280_20_OR_LATER(ah)) {
836 if (!AR_SREV_9287_11_OR_LATER(ah))
837 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
838 AR_PHY_ADC_CTL_OFF_PWDADC);
839 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
840 AR_PHY_AGC_CONTROL_FLTR_CAL);
843 /* Calibrate the AGC */
844 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
845 REG_READ(ah, AR_PHY_AGC_CONTROL) |
846 AR_PHY_AGC_CONTROL_CAL);
848 /* Poll for offset calibration complete */
849 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
850 AR_PHY_AGC_CONTROL_CAL,
851 0, AH_WAIT_TIMEOUT)) {
852 ath_print(common, ATH_DBG_CALIBRATE,
853 "offset calibration failed to "
854 "complete in 1ms; noisy environment?\n");
858 if (AR_SREV_9280_20_OR_LATER(ah)) {
859 if (!AR_SREV_9287_11_OR_LATER(ah))
860 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
861 AR_PHY_ADC_CTL_OFF_PWDADC);
862 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
863 AR_PHY_AGC_CONTROL_FLTR_CAL);
867 /* Do PA Calibration */
868 ar9002_hw_pa_cal(ah, true);
870 /* Do NF Calibration after DC offset and other calibrations */
871 ath9k_hw_start_nfcal(ah, true);
874 ah->caldata->nfcal_pending = true;
876 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
878 /* Enable IQ, ADC Gain and ADC DC offset CALs */
879 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
880 if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
881 INIT_CAL(&ah->adcgain_caldata);
882 INSERT_CAL(ah, &ah->adcgain_caldata);
883 ath_print(common, ATH_DBG_CALIBRATE,
884 "enabling ADC Gain Calibration.\n");
886 if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
887 INIT_CAL(&ah->adcdc_caldata);
888 INSERT_CAL(ah, &ah->adcdc_caldata);
889 ath_print(common, ATH_DBG_CALIBRATE,
890 "enabling ADC DC Calibration.\n");
892 if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
893 INIT_CAL(&ah->iq_caldata);
894 INSERT_CAL(ah, &ah->iq_caldata);
895 ath_print(common, ATH_DBG_CALIBRATE,
896 "enabling IQ Calibration.\n");
899 ah->cal_list_curr = ah->cal_list;
901 if (ah->cal_list_curr)
902 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
906 ah->caldata->CalValid = 0;
911 static const struct ath9k_percal_data iq_cal_multi_sample = {
915 ar9002_hw_iqcal_collect,
916 ar9002_hw_iqcalibrate
918 static const struct ath9k_percal_data iq_cal_single_sample = {
922 ar9002_hw_iqcal_collect,
923 ar9002_hw_iqcalibrate
925 static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
929 ar9002_hw_adc_gaincal_collect,
930 ar9002_hw_adc_gaincal_calibrate
932 static const struct ath9k_percal_data adc_gain_cal_single_sample = {
936 ar9002_hw_adc_gaincal_collect,
937 ar9002_hw_adc_gaincal_calibrate
939 static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
943 ar9002_hw_adc_dccal_collect,
944 ar9002_hw_adc_dccal_calibrate
946 static const struct ath9k_percal_data adc_dc_cal_single_sample = {
950 ar9002_hw_adc_dccal_collect,
951 ar9002_hw_adc_dccal_calibrate
953 static const struct ath9k_percal_data adc_init_dc_cal = {
957 ar9002_hw_adc_dccal_collect,
958 ar9002_hw_adc_dccal_calibrate
961 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
963 if (AR_SREV_9100(ah)) {
964 ah->iq_caldata.calData = &iq_cal_multi_sample;
965 ah->supp_cals = IQ_MISMATCH_CAL;
969 if (AR_SREV_9160_10_OR_LATER(ah)) {
970 if (AR_SREV_9280_20_OR_LATER(ah)) {
971 ah->iq_caldata.calData = &iq_cal_single_sample;
972 ah->adcgain_caldata.calData =
973 &adc_gain_cal_single_sample;
974 ah->adcdc_caldata.calData =
975 &adc_dc_cal_single_sample;
976 ah->adcdc_calinitdata.calData =
979 ah->iq_caldata.calData = &iq_cal_multi_sample;
980 ah->adcgain_caldata.calData =
981 &adc_gain_cal_multi_sample;
982 ah->adcdc_caldata.calData =
983 &adc_dc_cal_multi_sample;
984 ah->adcdc_calinitdata.calData =
987 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
991 void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
993 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
994 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
996 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
997 priv_ops->init_cal = ar9002_hw_init_cal;
998 priv_ops->setup_calibration = ar9002_hw_setup_calibration;
999 priv_ops->iscal_supported = ar9002_hw_iscal_supported;
1001 ops->calibrate = ar9002_hw_calibrate;