2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar5008_initvals.h"
19 #include "ar9001_initvals.h"
20 #include "ar9002_initvals.h"
21 #include "ar9002_phy.h"
23 int modparam_force_new_ani;
24 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
25 MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
27 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
29 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
31 if (AR_SREV_9271(ah)) {
32 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
33 ARRAY_SIZE(ar9271Modes_9271), 5);
34 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
35 ARRAY_SIZE(ar9271Common_9271), 2);
36 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
37 ar9271Common_normal_cck_fir_coeff_9271,
38 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
39 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
40 ar9271Common_japan_2484_cck_fir_coeff_9271,
41 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
42 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
43 ar9271Modes_9271_1_0_only,
44 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5);
45 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
46 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
47 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
48 ar9271Modes_high_power_tx_gain_9271,
49 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
50 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
51 ar9271Modes_normal_power_tx_gain_9271,
52 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
56 if (AR_SREV_9287_11_OR_LATER(ah)) {
57 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
58 ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
59 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
60 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
61 if (ah->config.pcie_clock_req)
62 INIT_INI_ARRAY(&ah->iniPcieSerdes,
63 ar9287PciePhy_clkreq_off_L1_9287_1_1,
64 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
66 INIT_INI_ARRAY(&ah->iniPcieSerdes,
67 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
68 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
70 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
73 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
74 ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
75 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
76 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
78 if (ah->config.pcie_clock_req) {
79 INIT_INI_ARRAY(&ah->iniPcieSerdes,
80 ar9285PciePhy_clkreq_off_L1_9285_1_2,
81 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
83 INIT_INI_ARRAY(&ah->iniPcieSerdes,
84 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
85 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
88 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
89 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
90 ARRAY_SIZE(ar9280Modes_9280_2), 5);
91 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
92 ARRAY_SIZE(ar9280Common_9280_2), 2);
94 if (ah->config.pcie_clock_req) {
95 INIT_INI_ARRAY(&ah->iniPcieSerdes,
96 ar9280PciePhy_clkreq_off_L1_9280,
97 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
99 INIT_INI_ARRAY(&ah->iniPcieSerdes,
100 ar9280PciePhy_clkreq_always_on_L1_9280,
101 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
103 INIT_INI_ARRAY(&ah->iniModesAdditional,
104 ar9280Modes_fast_clock_9280_2,
105 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
106 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
107 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
108 ARRAY_SIZE(ar5416Modes_9160), 5);
109 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
110 ARRAY_SIZE(ar5416Common_9160), 2);
111 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
112 ARRAY_SIZE(ar5416Bank0_9160), 2);
113 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
114 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
115 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
116 ARRAY_SIZE(ar5416Bank1_9160), 2);
117 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
118 ARRAY_SIZE(ar5416Bank2_9160), 2);
119 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
120 ARRAY_SIZE(ar5416Bank3_9160), 3);
121 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
122 ARRAY_SIZE(ar5416Bank6_9160), 3);
123 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
124 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
125 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
126 ARRAY_SIZE(ar5416Bank7_9160), 2);
127 if (AR_SREV_9160_11(ah)) {
128 INIT_INI_ARRAY(&ah->iniAddac,
129 ar5416Addac_9160_1_1,
130 ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
132 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
133 ARRAY_SIZE(ar5416Addac_9160), 2);
135 } else if (AR_SREV_9100_OR_LATER(ah)) {
136 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
137 ARRAY_SIZE(ar5416Modes_9100), 5);
138 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
139 ARRAY_SIZE(ar5416Common_9100), 2);
140 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
141 ARRAY_SIZE(ar5416Bank0_9100), 2);
142 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
143 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
144 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
145 ARRAY_SIZE(ar5416Bank1_9100), 2);
146 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
147 ARRAY_SIZE(ar5416Bank2_9100), 2);
148 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
149 ARRAY_SIZE(ar5416Bank3_9100), 3);
150 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
151 ARRAY_SIZE(ar5416Bank6_9100), 3);
152 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
153 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
154 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
155 ARRAY_SIZE(ar5416Bank7_9100), 2);
156 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
157 ARRAY_SIZE(ar5416Addac_9100), 2);
159 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
160 ARRAY_SIZE(ar5416Modes), 5);
161 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
162 ARRAY_SIZE(ar5416Common), 2);
163 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
164 ARRAY_SIZE(ar5416Bank0), 2);
165 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
166 ARRAY_SIZE(ar5416BB_RfGain), 3);
167 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
168 ARRAY_SIZE(ar5416Bank1), 2);
169 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
170 ARRAY_SIZE(ar5416Bank2), 2);
171 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
172 ARRAY_SIZE(ar5416Bank3), 3);
173 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
174 ARRAY_SIZE(ar5416Bank6), 3);
175 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
176 ARRAY_SIZE(ar5416Bank6TPC), 3);
177 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
178 ARRAY_SIZE(ar5416Bank7), 2);
179 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
180 ARRAY_SIZE(ar5416Addac), 2);
184 /* Support for Japan ch.14 (2484) spread */
185 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
187 if (AR_SREV_9287_11_OR_LATER(ah)) {
188 INIT_INI_ARRAY(&ah->iniCckfirNormal,
189 ar9287Common_normal_cck_fir_coeff_9287_1_1,
190 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
192 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
193 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
194 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
199 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
203 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
204 AR5416_EEP_MINOR_VER_17) {
205 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
207 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
208 INIT_INI_ARRAY(&ah->iniModesRxGain,
209 ar9280Modes_backoff_13db_rxgain_9280_2,
210 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
211 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
212 INIT_INI_ARRAY(&ah->iniModesRxGain,
213 ar9280Modes_backoff_23db_rxgain_9280_2,
214 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
216 INIT_INI_ARRAY(&ah->iniModesRxGain,
217 ar9280Modes_original_rxgain_9280_2,
218 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
220 INIT_INI_ARRAY(&ah->iniModesRxGain,
221 ar9280Modes_original_rxgain_9280_2,
222 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
226 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
230 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
231 AR5416_EEP_MINOR_VER_19) {
232 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
234 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
235 INIT_INI_ARRAY(&ah->iniModesTxGain,
236 ar9280Modes_high_power_tx_gain_9280_2,
237 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
239 INIT_INI_ARRAY(&ah->iniModesTxGain,
240 ar9280Modes_original_tx_gain_9280_2,
241 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
243 INIT_INI_ARRAY(&ah->iniModesTxGain,
244 ar9280Modes_original_tx_gain_9280_2,
245 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
249 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
251 if (AR_SREV_9287_11_OR_LATER(ah))
252 INIT_INI_ARRAY(&ah->iniModesRxGain,
253 ar9287Modes_rx_gain_9287_1_1,
254 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
255 else if (AR_SREV_9280_20(ah))
256 ar9280_20_hw_init_rxgain_ini(ah);
258 if (AR_SREV_9287_11_OR_LATER(ah)) {
259 INIT_INI_ARRAY(&ah->iniModesTxGain,
260 ar9287Modes_tx_gain_9287_1_1,
261 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
262 } else if (AR_SREV_9280_20(ah)) {
263 ar9280_20_hw_init_txgain_ini(ah);
264 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
265 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
268 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
269 if (AR_SREV_9285E_20(ah)) {
270 INIT_INI_ARRAY(&ah->iniModesTxGain,
271 ar9285Modes_XE2_0_high_power,
273 ar9285Modes_XE2_0_high_power), 5);
275 INIT_INI_ARRAY(&ah->iniModesTxGain,
276 ar9285Modes_high_power_tx_gain_9285_1_2,
278 ar9285Modes_high_power_tx_gain_9285_1_2), 5);
281 if (AR_SREV_9285E_20(ah)) {
282 INIT_INI_ARRAY(&ah->iniModesTxGain,
283 ar9285Modes_XE2_0_normal_power,
285 ar9285Modes_XE2_0_normal_power), 5);
287 INIT_INI_ARRAY(&ah->iniModesTxGain,
288 ar9285Modes_original_tx_gain_9285_1_2,
290 ar9285Modes_original_tx_gain_9285_1_2), 5);
297 * Helper for ASPM support.
299 * Disable PLL when in L0s as well as receiver clock when in L1.
300 * This power saving option must be enabled through the SerDes.
302 * Programming the SerDes must go through the same 288 bit serial shift
303 * register as the other analog registers. Hence the 9 writes.
305 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
311 /* Nothing to do on restore for 11N */
312 if (!power_off /* !restore */) {
313 if (AR_SREV_9280_20_OR_LATER(ah)) {
315 * AR9280 2.0 or later chips use SerDes values from the
316 * initvals.h initialized depending on chipset during
319 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
320 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
321 INI_RA(&ah->iniPcieSerdes, i, 1));
324 ENABLE_REGWRITE_BUFFER(ah);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
329 /* RX shut off when elecidle is asserted */
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
335 * Ignore ah->ah_config.pcie_clock_req setting for
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
340 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
341 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
342 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
344 /* Load the new settings */
345 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
347 REGWRITE_BUFFER_FLUSH(ah);
354 /* clear bit 19 to disable L1 */
355 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
357 val = REG_READ(ah, AR_WA);
360 * Set PCIe workaround bits
361 * In AR9280 and AR9285, bit 14 in WA register (disable L1)
362 * should only be set when device enters D3 and be
363 * cleared when device comes back to D0.
365 if (ah->config.pcie_waen) {
366 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
367 val |= AR_WA_D3_L1_DISABLE;
369 if (((AR_SREV_9285(ah) ||
372 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
374 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
375 val |= AR_WA_D3_L1_DISABLE;
379 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
381 * Disable bit 6 and 7 before entering D3 to
382 * prevent system hang.
384 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
387 if (AR_SREV_9280(ah))
390 if (AR_SREV_9285E_20(ah))
393 REG_WRITE(ah, AR_WA, val);
395 if (ah->config.pcie_waen) {
396 val = ah->config.pcie_waen;
398 val &= (~AR_WA_D3_L1_DISABLE);
400 if (AR_SREV_9285(ah) ||
403 val = AR9285_WA_DEFAULT;
405 val &= (~AR_WA_D3_L1_DISABLE);
407 else if (AR_SREV_9280(ah)) {
409 * For AR9280 chips, bit 22 of 0x4004
412 val = AR9280_WA_DEFAULT;
414 val &= (~AR_WA_D3_L1_DISABLE);
420 /* WAR for ASPM system hang */
421 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
422 val |= (AR_WA_BIT6 | AR_WA_BIT7);
424 if (AR_SREV_9285E_20(ah))
427 REG_WRITE(ah, AR_WA, val);
429 /* set bit 19 to allow forcing of pcie core into L1 state */
430 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
434 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
439 ENABLE_REGWRITE_BUFFER(ah);
441 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
442 for (i = 0; i < 8; i++)
443 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
445 REGWRITE_BUFFER_FLUSH(ah);
447 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
448 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
450 return ath9k_hw_reverse_bits(val, 8);
453 int ar9002_hw_rf_claim(struct ath_hw *ah)
457 REG_WRITE(ah, AR_PHY(0), 0x00000007);
459 val = ar9002_hw_get_radiorev(ah);
460 switch (val & AR_RADIO_SREV_MAJOR) {
462 val = AR_RAD5133_SREV_MAJOR;
464 case AR_RAD5133_SREV_MAJOR:
465 case AR_RAD5122_SREV_MAJOR:
466 case AR_RAD2133_SREV_MAJOR:
467 case AR_RAD2122_SREV_MAJOR:
470 ath_err(ath9k_hw_common(ah),
471 "Radio Chip Rev 0x%02X not supported\n",
472 val & AR_RADIO_SREV_MAJOR);
476 ah->hw_version.analog5GhzRev = val;
481 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
483 if (AR_SREV_9287_13_OR_LATER(ah)) {
484 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
485 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
486 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
487 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
488 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
489 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
490 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
494 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
495 void ar9002_hw_attach_ops(struct ath_hw *ah)
497 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
498 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
500 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
501 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
503 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
505 ar5008_hw_attach_phy_ops(ah);
506 if (AR_SREV_9280_20_OR_LATER(ah))
507 ar9002_hw_attach_phy_ops(ah);
509 ar9002_hw_attach_calib_ops(ah);
510 ar9002_hw_attach_mac_ops(ah);
513 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
518 switch (chan->chanmode) {
523 case CHANNEL_A_HT40PLUS:
524 case CHANNEL_A_HT40MINUS:
532 case CHANNEL_G_HT40PLUS:
533 case CHANNEL_G_HT40MINUS:
541 ENABLE_REGWRITE_BUFFER(ah);
543 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
544 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
545 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
548 if (reg == AR_PHY_CCK_DETECT) {
549 val_orig = REG_READ(ah, reg);
550 val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
551 val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
553 REG_WRITE(ah, reg, val|val_orig);
555 REG_WRITE(ah, reg, val);
558 REGWRITE_BUFFER_FLUSH(ah);