2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef AR9003_EEPROM_H
18 #define AR9003_EEPROM_H
20 #include <linux/types.h>
22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
25 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
27 /* 16-bit offset location start of calibration struct */
28 #define AR9300_EEP_START_LOC 256
29 #define AR9300_NUM_5G_CAL_PIERS 8
30 #define AR9300_NUM_2G_CAL_PIERS 3
31 #define AR9300_NUM_5G_20_TARGET_POWERS 8
32 #define AR9300_NUM_5G_40_TARGET_POWERS 8
33 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
34 #define AR9300_NUM_2G_20_TARGET_POWERS 3
35 #define AR9300_NUM_2G_40_TARGET_POWERS 3
36 /* #define AR9300_NUM_CTLS 21 */
37 #define AR9300_NUM_CTLS_5G 9
38 #define AR9300_NUM_CTLS_2G 12
39 #define AR9300_NUM_BAND_EDGES_5G 8
40 #define AR9300_NUM_BAND_EDGES_2G 4
41 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
42 #define AR9300_EEPMISC_WOW 0x02
43 #define AR9300_CUSTOMER_DATA_SIZE 20
45 #define AR9300_MAX_CHAINS 3
46 #define AR9300_ANT_16S 25
47 #define AR9300_FUTURE_MODAL_SZ 6
49 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
50 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_1_S 25
52 #define AR9300_PAPRD_SCALE_2 0x70000000
53 #define AR9300_PAPRD_SCALE_2_S 28
55 /* Delta from which to start power to pdadc table */
56 /* This offset is used in both open loop and closed loop power control
57 * schemes. In open loop power control, it is not really needed, but for
58 * the "sake of consistency" it was kept. For certain AP designs, this
59 * value is overwritten by the value in the flag "pwrTableOffset" just
60 * before writing the pdadc vs pwr into the chip registers.
62 #define AR9300_PWR_TABLE_OFFSET 0
64 /* byte addressable */
65 #define AR9300_EEPROM_SIZE (16*1024)
67 #define AR9300_BASE_ADDR_4K 0xfff
68 #define AR9300_BASE_ADDR 0x3ff
69 #define AR9300_BASE_ADDR_512 0x1ff
71 #define AR9300_OTP_BASE 0x14000
72 #define AR9300_OTP_STATUS 0x15f18
73 #define AR9300_OTP_STATUS_TYPE 0x7
74 #define AR9300_OTP_STATUS_VALID 0x4
75 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
76 #define AR9300_OTP_STATUS_SM_BUSY 0x1
77 #define AR9300_OTP_READ_DATA 0x15f1c
79 enum targetPowerHTRates {
80 HT_TARGET_RATE_0_8_16,
81 HT_TARGET_RATE_1_3_9_11_17_19,
96 enum targetPowerLegacyRates {
97 LEGACY_TARGET_RATE_6_24,
98 LEGACY_TARGET_RATE_36,
99 LEGACY_TARGET_RATE_48,
100 LEGACY_TARGET_RATE_54
103 enum targetPowerCckRates {
104 LEGACY_TARGET_RATE_1L_5L,
105 LEGACY_TARGET_RATE_5S,
106 LEGACY_TARGET_RATE_11L,
107 LEGACY_TARGET_RATE_11S
111 ALL_TARGET_LEGACY_6_24,
112 ALL_TARGET_LEGACY_36,
113 ALL_TARGET_LEGACY_48,
114 ALL_TARGET_LEGACY_54,
115 ALL_TARGET_LEGACY_1L_5L,
116 ALL_TARGET_LEGACY_5S,
117 ALL_TARGET_LEGACY_11L,
118 ALL_TARGET_LEGACY_11S,
119 ALL_TARGET_HT20_0_8_16,
120 ALL_TARGET_HT20_1_3_9_11_17_19,
133 ALL_TARGET_HT40_0_8_16,
134 ALL_TARGET_HT40_1_3_9_11_17_19,
156 enum CompressAlgorithm {
167 struct ar9300_base_eep_hdr {
169 /* 4 bits tx and 4 bits rx */
171 struct eepFlags opCapFlags;
175 /* takes lower byte in eeprom location */
177 /* offset in dB to be added to beginning
178 * of pdadc table in calibration
180 int8_t pwrTableOffset;
181 u8 params_for_tuning_caps[2];
183 * bit0 - enable tx temp comp
184 * bit1 - enable tx volt comp
185 * bit2 - enable fastClock - default to 1
186 * bit3 - enable doubling - default to 1
187 * bit4 - enable internal regulator - default to 1
190 /* misc flags: bit0 - turn down drivestrength */
191 u8 miscConfiguration;
192 u8 eepromWriteEnableGpio;
197 /* SW controlled internal regulator fields */
201 struct ar9300_modal_eep_header {
202 /* 4 idle, t1, t2, b (4 bits per setting) */
203 __le32 antCtrlCommon;
204 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
205 __le32 antCtrlCommon2;
206 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
207 __le16 antCtrlChain[AR9300_MAX_CHAINS];
208 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
209 u8 xatten1DB[AR9300_MAX_CHAINS];
210 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
211 u8 xatten1Margin[AR9300_MAX_CHAINS];
214 /* spur channels in usual fbin coding format */
215 u8 spurChans[AR_EEPROM_MODAL_SPURS];
216 /* 3 Check if the register is per chain */
217 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
221 u8 txFrameToDataStart;
226 int8_t adcDesiredSize;
231 __le32 papdRateMaskHt20;
232 __le32 papdRateMaskHt40;
233 __le16 switchcomspdt;
237 struct ar9300_cal_data_per_freq_op_loop {
239 /* pdadc voltage at power measurement */
241 /* pcdac used for power measurement */
243 /* range is -60 to -127 create a mapping equation 1db resolution */
244 int8_t rxNoisefloorCal;
245 /*range is same as noisefloor */
246 int8_t rxNoisefloorPower;
247 /* temp measured when noisefloor cal was performed */
251 struct cal_tgt_pow_legacy {
255 struct cal_tgt_pow_ht {
259 struct cal_ctl_data_2g {
260 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
263 struct cal_ctl_data_5g {
264 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
267 struct ar9300_BaseExtension_1 {
270 int8_t quick_drop_low;
271 int8_t quick_drop_high;
274 struct ar9300_BaseExtension_2 {
276 int8_t tempSlopeHigh;
277 u8 xatten1DBLow[AR9300_MAX_CHAINS];
278 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
279 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
280 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
283 struct ar9300_eeprom {
287 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
289 struct ar9300_base_eep_hdr baseEepHeader;
291 struct ar9300_modal_eep_header modalHeader2G;
292 struct ar9300_BaseExtension_1 base_ext1;
293 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
294 struct ar9300_cal_data_per_freq_op_loop
295 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
296 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
297 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
298 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
299 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
300 struct cal_tgt_pow_legacy
301 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
302 struct cal_tgt_pow_legacy
303 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
304 struct cal_tgt_pow_ht
305 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
306 struct cal_tgt_pow_ht
307 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
308 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
309 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
310 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
311 struct ar9300_modal_eep_header modalHeader5G;
312 struct ar9300_BaseExtension_2 base_ext2;
313 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
314 struct ar9300_cal_data_per_freq_op_loop
315 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
316 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
317 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
318 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
319 struct cal_tgt_pow_legacy
320 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
321 struct cal_tgt_pow_ht
322 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
323 struct cal_tgt_pow_ht
324 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
325 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
326 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
327 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
330 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
331 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
333 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
335 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
336 struct ath9k_channel *chan);