drivers/net/wireless/ath/ath9k/ar9003_eeprom.h

   1 #ifndef AR9003_EEPROM_H
   2 #define AR9003_EEPROM_H
   3
   4 #include <linux/types.h>
   5
   6 #define AR9300_EEP_VER               0xD000
   7 #define AR9300_EEP_VER_MINOR_MASK    0xFFF
   8 #define AR9300_EEP_MINOR_VER_1       0x1
   9 #define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1
  10
  11 /* 16-bit offset location start of calibration struct */
  12 #define AR9300_EEP_START_LOC         256
  13 #define AR9300_NUM_5G_CAL_PIERS      8
  14 #define AR9300_NUM_2G_CAL_PIERS      3
  15 #define AR9300_NUM_5G_20_TARGET_POWERS  8
  16 #define AR9300_NUM_5G_40_TARGET_POWERS  8
  17 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
  18 #define AR9300_NUM_2G_20_TARGET_POWERS  3
  19 #define AR9300_NUM_2G_40_TARGET_POWERS  3
  20 /* #define AR9300_NUM_CTLS              21 */
  21 #define AR9300_NUM_CTLS_5G           9
  22 #define AR9300_NUM_CTLS_2G           12
  23 #define AR9300_NUM_BAND_EDGES_5G     8
  24 #define AR9300_NUM_BAND_EDGES_2G     4
  25 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
  26 #define AR9300_EEPMISC_WOW           0x02
  27 #define AR9300_CUSTOMER_DATA_SIZE    20
  28
  29 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
  30 #define AR9300_MAX_CHAINS            3
  31 #define AR9300_ANT_16S               25
  32 #define AR9300_FUTURE_MODAL_SZ       6
  33
  34 /* Delta from which to start power to pdadc table */
  35 /* This offset is used in both open loop and closed loop power control
  36  * schemes. In open loop power control, it is not really needed, but for
  37  * the "sake of consistency" it was kept. For certain AP designs, this
  38  * value is overwritten by the value in the flag "pwrTableOffset" just
  39  * before writing the pdadc vs pwr into the chip registers.
  40  */
  41 #define AR9300_PWR_TABLE_OFFSET  0
  42
  43 /* byte addressable */
  44 #define AR9300_EEPROM_SIZE (16*1024)
  45
  46 #define AR9300_BASE_ADDR_4K 0xfff
  47 #define AR9300_BASE_ADDR 0x3ff
  48 #define AR9300_BASE_ADDR_512 0x1ff
  49
  50 #define AR9300_OTP_BASE                 0x14000
  51 #define AR9300_OTP_STATUS               0x15f18
  52 #define AR9300_OTP_STATUS_TYPE          0x7
  53 #define AR9300_OTP_STATUS_VALID         0x4
  54 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
  55 #define AR9300_OTP_STATUS_SM_BUSY       0x1
  56 #define AR9300_OTP_READ_DATA            0x15f1c
  57
  58 enum targetPowerHTRates {
  59         HT_TARGET_RATE_0_8_16,
  60         HT_TARGET_RATE_1_3_9_11_17_19,
  61         HT_TARGET_RATE_4,
  62         HT_TARGET_RATE_5,
  63         HT_TARGET_RATE_6,
  64         HT_TARGET_RATE_7,
  65         HT_TARGET_RATE_12,
  66         HT_TARGET_RATE_13,
  67         HT_TARGET_RATE_14,
  68         HT_TARGET_RATE_15,
  69         HT_TARGET_RATE_20,
  70         HT_TARGET_RATE_21,
  71         HT_TARGET_RATE_22,
  72         HT_TARGET_RATE_23
  73 };
  74
  75 enum targetPowerLegacyRates {
  76         LEGACY_TARGET_RATE_6_24,
  77         LEGACY_TARGET_RATE_36,
  78         LEGACY_TARGET_RATE_48,
  79         LEGACY_TARGET_RATE_54
  80 };
  81
  82 enum targetPowerCckRates {
  83         LEGACY_TARGET_RATE_1L_5L,
  84         LEGACY_TARGET_RATE_5S,
  85         LEGACY_TARGET_RATE_11L,
  86         LEGACY_TARGET_RATE_11S
  87 };
  88
  89 enum ar9300_Rates {
  90         ALL_TARGET_LEGACY_6_24,
  91         ALL_TARGET_LEGACY_36,
  92         ALL_TARGET_LEGACY_48,
  93         ALL_TARGET_LEGACY_54,
  94         ALL_TARGET_LEGACY_1L_5L,
  95         ALL_TARGET_LEGACY_5S,
  96         ALL_TARGET_LEGACY_11L,
  97         ALL_TARGET_LEGACY_11S,
  98         ALL_TARGET_HT20_0_8_16,
  99         ALL_TARGET_HT20_1_3_9_11_17_19,
 100         ALL_TARGET_HT20_4,
 101         ALL_TARGET_HT20_5,
 102         ALL_TARGET_HT20_6,
 103         ALL_TARGET_HT20_7,
 104         ALL_TARGET_HT20_12,
 105         ALL_TARGET_HT20_13,
 106         ALL_TARGET_HT20_14,
 107         ALL_TARGET_HT20_15,
 108         ALL_TARGET_HT20_20,
 109         ALL_TARGET_HT20_21,
 110         ALL_TARGET_HT20_22,
 111         ALL_TARGET_HT20_23,
 112         ALL_TARGET_HT40_0_8_16,
 113         ALL_TARGET_HT40_1_3_9_11_17_19,
 114         ALL_TARGET_HT40_4,
 115         ALL_TARGET_HT40_5,
 116         ALL_TARGET_HT40_6,
 117         ALL_TARGET_HT40_7,
 118         ALL_TARGET_HT40_12,
 119         ALL_TARGET_HT40_13,
 120         ALL_TARGET_HT40_14,
 121         ALL_TARGET_HT40_15,
 122         ALL_TARGET_HT40_20,
 123         ALL_TARGET_HT40_21,
 124         ALL_TARGET_HT40_22,
 125         ALL_TARGET_HT40_23,
 126         ar9300RateSize,
 127 };
 128
 129
 130 struct eepFlags {
 131         u8 opFlags;
 132         u8 eepMisc;
 133 } __packed;
 134
 135 enum CompressAlgorithm {
 136         _CompressNone = 0,
 137         _CompressLzma,
 138         _CompressPairs,
 139         _CompressBlock,
 140         _Compress4,
 141         _Compress5,
 142         _Compress6,
 143         _Compress7,
 144 };
 145
 146 struct ar9300_base_eep_hdr {
 147         __le16 regDmn[2];
 148         /* 4 bits tx and 4 bits rx */
 149         u8 txrxMask;
 150         struct eepFlags opCapFlags;
 151         u8 rfSilent;
 152         u8 blueToothOptions;
 153         u8 deviceCap;
 154         /* takes lower byte in eeprom location */
 155         u8 deviceType;
 156         /* offset in dB to be added to beginning
 157          * of pdadc table in calibration
 158          */
 159         int8_t pwrTableOffset;
 160         u8 params_for_tuning_caps[2];
 161         /*
 162          * bit0 - enable tx temp comp
 163          * bit1 - enable tx volt comp
 164          * bit2 - enable fastClock - default to 1
 165          * bit3 - enable doubling - default to 1
 166          * bit4 - enable internal regulator - default to 1
 167          */
 168         u8 featureEnable;
 169         /* misc flags: bit0 - turn down drivestrength */
 170         u8 miscConfiguration;
 171         u8 eepromWriteEnableGpio;
 172         u8 wlanDisableGpio;
 173         u8 wlanLedGpio;
 174         u8 rxBandSelectGpio;
 175         u8 txrxgain;
 176         /* SW controlled internal regulator fields */
 177         __le32 swreg;
 178 } __packed;
 179
 180 struct ar9300_modal_eep_header {
 181         /* 4 idle, t1, t2, b (4 bits per setting) */
 182         __le32 antCtrlCommon;
 183         /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 184         __le32 antCtrlCommon2;
 185         /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
 186         __le16 antCtrlChain[AR9300_MAX_CHAINS];
 187         /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 188         u8 xatten1DB[AR9300_MAX_CHAINS];
 189         /* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
 190         u8 xatten1Margin[AR9300_MAX_CHAINS];
 191         int8_t tempSlope;
 192         int8_t voltSlope;
 193         /* spur channels in usual fbin coding format */
 194         u8 spurChans[AR_EEPROM_MODAL_SPURS];
 195         /* 3  Check if the register is per chain */
 196         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
 197         u8 ob[AR9300_MAX_CHAINS];
 198         u8 db_stage2[AR9300_MAX_CHAINS];
 199         u8 db_stage3[AR9300_MAX_CHAINS];
 200         u8 db_stage4[AR9300_MAX_CHAINS];
 201         u8 xpaBiasLvl;
 202         u8 txFrameToDataStart;
 203         u8 txFrameToPaOn;
 204         u8 txClip;
 205         int8_t antennaGain;
 206         u8 switchSettling;
 207         int8_t adcDesiredSize;
 208         u8 txEndToXpaOff;
 209         u8 txEndToRxOn;
 210         u8 txFrameToXpaOn;
 211         u8 thresh62;
 212         __le32 papdRateMaskHt20;
 213         __le32 papdRateMaskHt40;
 214         u8 futureModal[10];
 215 } __packed;
 216
 217 struct ar9300_cal_data_per_freq_op_loop {
 218         int8_t refPower;
 219         /* pdadc voltage at power measurement */
 220         u8 voltMeas;
 221         /* pcdac used for power measurement   */
 222         u8 tempMeas;
 223         /* range is -60 to -127 create a mapping equation 1db resolution */
 224         int8_t rxNoisefloorCal;
 225         /*range is same as noisefloor */
 226         int8_t rxNoisefloorPower;
 227         /* temp measured when noisefloor cal was performed */
 228         u8 rxTempMeas;
 229 } __packed;
 230
 231 struct cal_tgt_pow_legacy {
 232         u8 tPow2x[4];
 233 } __packed;
 234
 235 struct cal_tgt_pow_ht {
 236         u8 tPow2x[14];
 237 } __packed;
 238
 239 struct cal_ctl_data_2g {
 240         u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
 241 } __packed;
 242
 243 struct cal_ctl_data_5g {
 244         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
 245 } __packed;
 246
 247 struct ar9300_BaseExtension_1 {
 248         u8 ant_div_control;
 249         u8 future[13];
 250 } __packed;
 251
 252 struct ar9300_BaseExtension_2 {
 253         int8_t    tempSlopeLow;
 254         int8_t    tempSlopeHigh;
 255         u8   xatten1DBLow[AR9300_MAX_CHAINS];
 256         u8   xatten1MarginLow[AR9300_MAX_CHAINS];
 257         u8   xatten1DBHigh[AR9300_MAX_CHAINS];
 258         u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 259 } __packed;
 260
 261 struct ar9300_eeprom {
 262         u8 eepromVersion;
 263         u8 templateVersion;
 264         u8 macAddr[6];
 265         u8 custData[AR9300_CUSTOMER_DATA_SIZE];
 266
 267         struct ar9300_base_eep_hdr baseEepHeader;
 268
 269         struct ar9300_modal_eep_header modalHeader2G;
 270         struct ar9300_BaseExtension_1 base_ext1;
 271         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
 272         struct ar9300_cal_data_per_freq_op_loop
 273          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
 274         u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 275         u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
 276         u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 277         u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 278         struct cal_tgt_pow_legacy
 279          calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 280         struct cal_tgt_pow_legacy
 281          calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
 282         struct cal_tgt_pow_ht
 283          calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 284         struct cal_tgt_pow_ht
 285          calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 286         u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
 287         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
 288         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
 289         struct ar9300_modal_eep_header modalHeader5G;
 290         struct ar9300_BaseExtension_2 base_ext2;
 291         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
 292         struct ar9300_cal_data_per_freq_op_loop
 293          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
 294         u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
 295         u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 296         u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 297         struct cal_tgt_pow_legacy
 298          calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
 299         struct cal_tgt_pow_ht
 300          calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 301         struct cal_tgt_pow_ht
 302          calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 303         u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
 304         u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
 305         struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
 306 } __packed;
 307
 308 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 309 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 310
 311 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
 312 #endif