2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef AR9003_EEPROM_H
18 #define AR9003_EEPROM_H
20 #include <linux/types.h>
22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
25 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
27 /* 16-bit offset location start of calibration struct */
28 #define AR9300_EEP_START_LOC 256
29 #define AR9300_NUM_5G_CAL_PIERS 8
30 #define AR9300_NUM_2G_CAL_PIERS 3
31 #define AR9300_NUM_5G_20_TARGET_POWERS 8
32 #define AR9300_NUM_5G_40_TARGET_POWERS 8
33 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
34 #define AR9300_NUM_2G_20_TARGET_POWERS 3
35 #define AR9300_NUM_2G_40_TARGET_POWERS 3
36 /* #define AR9300_NUM_CTLS 21 */
37 #define AR9300_NUM_CTLS_5G 9
38 #define AR9300_NUM_CTLS_2G 12
39 #define AR9300_NUM_BAND_EDGES_5G 8
40 #define AR9300_NUM_BAND_EDGES_2G 4
41 #define AR9300_EEPMISC_WOW 0x02
42 #define AR9300_CUSTOMER_DATA_SIZE 20
44 #define AR9300_MAX_CHAINS 3
45 #define AR9300_ANT_16S 25
46 #define AR9300_FUTURE_MODAL_SZ 6
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
50 #define AR9300_PAPRD_SCALE_1_S 25
51 #define AR9300_PAPRD_SCALE_2 0x70000000
52 #define AR9300_PAPRD_SCALE_2_S 28
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
56 /* Delta from which to start power to pdadc table */
57 /* This offset is used in both open loop and closed loop power control
58 * schemes. In open loop power control, it is not really needed, but for
59 * the "sake of consistency" it was kept. For certain AP designs, this
60 * value is overwritten by the value in the flag "pwrTableOffset" just
61 * before writing the pdadc vs pwr into the chip registers.
63 #define AR9300_PWR_TABLE_OFFSET 0
65 /* byte addressable */
66 #define AR9300_EEPROM_SIZE (16*1024)
68 #define AR9300_BASE_ADDR_4K 0xfff
69 #define AR9300_BASE_ADDR 0x3ff
70 #define AR9300_BASE_ADDR_512 0x1ff
72 /* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */
73 #define AR9300_EEPMISC_LITTLE_ENDIAN 0
75 #define AR9300_OTP_BASE \
76 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
77 #define AR9300_OTP_STATUS \
78 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18)
79 #define AR9300_OTP_STATUS_TYPE 0x7
80 #define AR9300_OTP_STATUS_VALID 0x4
81 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
82 #define AR9300_OTP_STATUS_SM_BUSY 0x1
83 #define AR9300_OTP_READ_DATA \
84 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c)
86 enum targetPowerHTRates {
87 HT_TARGET_RATE_0_8_16,
88 HT_TARGET_RATE_1_3_9_11_17_19,
103 enum targetPowerLegacyRates {
104 LEGACY_TARGET_RATE_6_24,
105 LEGACY_TARGET_RATE_36,
106 LEGACY_TARGET_RATE_48,
107 LEGACY_TARGET_RATE_54
110 enum targetPowerCckRates {
111 LEGACY_TARGET_RATE_1L_5L,
112 LEGACY_TARGET_RATE_5S,
113 LEGACY_TARGET_RATE_11L,
114 LEGACY_TARGET_RATE_11S
118 ALL_TARGET_LEGACY_6_24,
119 ALL_TARGET_LEGACY_36,
120 ALL_TARGET_LEGACY_48,
121 ALL_TARGET_LEGACY_54,
122 ALL_TARGET_LEGACY_1L_5L,
123 ALL_TARGET_LEGACY_5S,
124 ALL_TARGET_LEGACY_11L,
125 ALL_TARGET_LEGACY_11S,
126 ALL_TARGET_HT20_0_8_16,
127 ALL_TARGET_HT20_1_3_9_11_17_19,
140 ALL_TARGET_HT40_0_8_16,
141 ALL_TARGET_HT40_1_3_9_11_17_19,
163 enum CompressAlgorithm {
174 struct ar9300_base_eep_hdr {
176 /* 4 bits tx and 4 bits rx */
178 struct eepFlags opCapFlags;
182 /* takes lower byte in eeprom location */
184 /* offset in dB to be added to beginning
185 * of pdadc table in calibration
187 int8_t pwrTableOffset;
188 u8 params_for_tuning_caps[2];
190 * bit0 - enable tx temp comp
191 * bit1 - enable tx volt comp
192 * bit2 - enable fastClock - default to 1
193 * bit3 - enable doubling - default to 1
194 * bit4 - enable internal regulator - default to 1
197 /* misc flags: bit0 - turn down drivestrength */
198 u8 miscConfiguration;
199 u8 eepromWriteEnableGpio;
204 /* SW controlled internal regulator fields */
208 struct ar9300_modal_eep_header {
209 /* 4 idle, t1, t2, b (4 bits per setting) */
210 __le32 antCtrlCommon;
211 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
212 __le32 antCtrlCommon2;
213 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
214 __le16 antCtrlChain[AR9300_MAX_CHAINS];
215 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
216 u8 xatten1DB[AR9300_MAX_CHAINS];
217 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
218 u8 xatten1Margin[AR9300_MAX_CHAINS];
221 /* spur channels in usual fbin coding format */
222 u8 spurChans[AR_EEPROM_MODAL_SPURS];
223 /* 3 Check if the register is per chain */
224 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
228 u8 txFrameToDataStart;
233 int8_t adcDesiredSize;
238 __le32 papdRateMaskHt20;
239 __le32 papdRateMaskHt40;
240 __le16 switchcomspdt;
241 u8 xlna_bias_strength;
245 struct ar9300_cal_data_per_freq_op_loop {
247 /* pdadc voltage at power measurement */
249 /* pcdac used for power measurement */
251 /* range is -60 to -127 create a mapping equation 1db resolution */
252 int8_t rxNoisefloorCal;
253 /*range is same as noisefloor */
254 int8_t rxNoisefloorPower;
255 /* temp measured when noisefloor cal was performed */
259 struct cal_tgt_pow_legacy {
263 struct cal_tgt_pow_ht {
267 struct cal_ctl_data_2g {
268 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
271 struct cal_ctl_data_5g {
272 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
275 #define MAX_BASE_EXTENSION_FUTURE 2
277 struct ar9300_BaseExtension_1 {
279 u8 future[MAX_BASE_EXTENSION_FUTURE];
283 * BIT 0 - TX Gain Cap enable.
284 * BIT 1 - Uncompressed Checksum enable.
285 * BIT 2/3 - MinCCApwr enable 2g/5g.
288 int8_t tempslopextension[8];
289 int8_t quick_drop_low;
290 int8_t quick_drop_high;
293 struct ar9300_BaseExtension_2 {
295 int8_t tempSlopeHigh;
296 u8 xatten1DBLow[AR9300_MAX_CHAINS];
297 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
298 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
299 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
302 struct ar9300_eeprom {
306 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
308 struct ar9300_base_eep_hdr baseEepHeader;
310 struct ar9300_modal_eep_header modalHeader2G;
311 struct ar9300_BaseExtension_1 base_ext1;
312 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
313 struct ar9300_cal_data_per_freq_op_loop
314 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
315 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
316 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
317 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
318 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
319 struct cal_tgt_pow_legacy
320 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
321 struct cal_tgt_pow_legacy
322 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
323 struct cal_tgt_pow_ht
324 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
325 struct cal_tgt_pow_ht
326 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
327 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
328 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
329 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
330 struct ar9300_modal_eep_header modalHeader5G;
331 struct ar9300_BaseExtension_2 base_ext2;
332 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
333 struct ar9300_cal_data_per_freq_op_loop
334 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
335 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
336 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
337 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
338 struct cal_tgt_pow_legacy
339 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
340 struct cal_tgt_pow_ht
341 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
342 struct cal_tgt_pow_ht
343 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
344 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
345 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
346 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
349 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
350 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
351 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);
352 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);
354 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
356 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
357 struct ath9k_channel *chan);
359 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
360 int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray);