1 #ifndef AR9003_EEPROM_H
2 #define AR9003_EEPROM_H
4 #include <linux/types.h>
6 #define AR9300_EEP_VER 0xD000
7 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
8 #define AR9300_EEP_MINOR_VER_1 0x1
9 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
11 /* 16-bit offset location start of calibration struct */
12 #define AR9300_EEP_START_LOC 256
13 #define AR9300_NUM_5G_CAL_PIERS 8
14 #define AR9300_NUM_2G_CAL_PIERS 3
15 #define AR9300_NUM_5G_20_TARGET_POWERS 8
16 #define AR9300_NUM_5G_40_TARGET_POWERS 8
17 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
18 #define AR9300_NUM_2G_20_TARGET_POWERS 3
19 #define AR9300_NUM_2G_40_TARGET_POWERS 3
20 /* #define AR9300_NUM_CTLS 21 */
21 #define AR9300_NUM_CTLS_5G 9
22 #define AR9300_NUM_CTLS_2G 12
23 #define AR9300_NUM_BAND_EDGES_5G 8
24 #define AR9300_NUM_BAND_EDGES_2G 4
25 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
26 #define AR9300_EEPMISC_WOW 0x02
27 #define AR9300_CUSTOMER_DATA_SIZE 20
29 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
30 #define AR9300_MAX_CHAINS 3
31 #define AR9300_ANT_16S 25
32 #define AR9300_FUTURE_MODAL_SZ 6
34 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
35 #define AR9300_PAPRD_SCALE_1 0x0e000000
36 #define AR9300_PAPRD_SCALE_1_S 25
37 #define AR9300_PAPRD_SCALE_2 0x70000000
38 #define AR9300_PAPRD_SCALE_2_S 28
40 /* Delta from which to start power to pdadc table */
41 /* This offset is used in both open loop and closed loop power control
42 * schemes. In open loop power control, it is not really needed, but for
43 * the "sake of consistency" it was kept. For certain AP designs, this
44 * value is overwritten by the value in the flag "pwrTableOffset" just
45 * before writing the pdadc vs pwr into the chip registers.
47 #define AR9300_PWR_TABLE_OFFSET 0
49 /* byte addressable */
50 #define AR9300_EEPROM_SIZE (16*1024)
52 #define AR9300_BASE_ADDR_4K 0xfff
53 #define AR9300_BASE_ADDR 0x3ff
54 #define AR9300_BASE_ADDR_512 0x1ff
56 #define AR9300_OTP_BASE 0x14000
57 #define AR9300_OTP_STATUS 0x15f18
58 #define AR9300_OTP_STATUS_TYPE 0x7
59 #define AR9300_OTP_STATUS_VALID 0x4
60 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
61 #define AR9300_OTP_STATUS_SM_BUSY 0x1
62 #define AR9300_OTP_READ_DATA 0x15f1c
64 enum targetPowerHTRates {
65 HT_TARGET_RATE_0_8_16,
66 HT_TARGET_RATE_1_3_9_11_17_19,
81 enum targetPowerLegacyRates {
82 LEGACY_TARGET_RATE_6_24,
83 LEGACY_TARGET_RATE_36,
84 LEGACY_TARGET_RATE_48,
88 enum targetPowerCckRates {
89 LEGACY_TARGET_RATE_1L_5L,
90 LEGACY_TARGET_RATE_5S,
91 LEGACY_TARGET_RATE_11L,
92 LEGACY_TARGET_RATE_11S
96 ALL_TARGET_LEGACY_6_24,
100 ALL_TARGET_LEGACY_1L_5L,
101 ALL_TARGET_LEGACY_5S,
102 ALL_TARGET_LEGACY_11L,
103 ALL_TARGET_LEGACY_11S,
104 ALL_TARGET_HT20_0_8_16,
105 ALL_TARGET_HT20_1_3_9_11_17_19,
118 ALL_TARGET_HT40_0_8_16,
119 ALL_TARGET_HT40_1_3_9_11_17_19,
141 enum CompressAlgorithm {
152 struct ar9300_base_eep_hdr {
154 /* 4 bits tx and 4 bits rx */
156 struct eepFlags opCapFlags;
160 /* takes lower byte in eeprom location */
162 /* offset in dB to be added to beginning
163 * of pdadc table in calibration
165 int8_t pwrTableOffset;
166 u8 params_for_tuning_caps[2];
168 * bit0 - enable tx temp comp
169 * bit1 - enable tx volt comp
170 * bit2 - enable fastClock - default to 1
171 * bit3 - enable doubling - default to 1
172 * bit4 - enable internal regulator - default to 1
175 /* misc flags: bit0 - turn down drivestrength */
176 u8 miscConfiguration;
177 u8 eepromWriteEnableGpio;
182 /* SW controlled internal regulator fields */
186 struct ar9300_modal_eep_header {
187 /* 4 idle, t1, t2, b (4 bits per setting) */
188 __le32 antCtrlCommon;
189 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
190 __le32 antCtrlCommon2;
191 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
192 __le16 antCtrlChain[AR9300_MAX_CHAINS];
193 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
194 u8 xatten1DB[AR9300_MAX_CHAINS];
195 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
196 u8 xatten1Margin[AR9300_MAX_CHAINS];
199 /* spur channels in usual fbin coding format */
200 u8 spurChans[AR_EEPROM_MODAL_SPURS];
201 /* 3 Check if the register is per chain */
202 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
203 u8 ob[AR9300_MAX_CHAINS];
204 u8 db_stage2[AR9300_MAX_CHAINS];
205 u8 db_stage3[AR9300_MAX_CHAINS];
206 u8 db_stage4[AR9300_MAX_CHAINS];
208 u8 txFrameToDataStart;
213 int8_t adcDesiredSize;
218 __le32 papdRateMaskHt20;
219 __le32 papdRateMaskHt40;
223 struct ar9300_cal_data_per_freq_op_loop {
225 /* pdadc voltage at power measurement */
227 /* pcdac used for power measurement */
229 /* range is -60 to -127 create a mapping equation 1db resolution */
230 int8_t rxNoisefloorCal;
231 /*range is same as noisefloor */
232 int8_t rxNoisefloorPower;
233 /* temp measured when noisefloor cal was performed */
237 struct cal_tgt_pow_legacy {
241 struct cal_tgt_pow_ht {
245 struct cal_ctl_data_2g {
246 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
249 struct cal_ctl_data_5g {
250 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
253 struct ar9300_BaseExtension_1 {
258 struct ar9300_BaseExtension_2 {
260 int8_t tempSlopeHigh;
261 u8 xatten1DBLow[AR9300_MAX_CHAINS];
262 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
263 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
264 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
267 struct ar9300_eeprom {
271 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
273 struct ar9300_base_eep_hdr baseEepHeader;
275 struct ar9300_modal_eep_header modalHeader2G;
276 struct ar9300_BaseExtension_1 base_ext1;
277 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
278 struct ar9300_cal_data_per_freq_op_loop
279 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
280 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
281 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
282 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
283 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
284 struct cal_tgt_pow_legacy
285 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
286 struct cal_tgt_pow_legacy
287 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
288 struct cal_tgt_pow_ht
289 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
290 struct cal_tgt_pow_ht
291 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
292 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
293 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
294 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
295 struct ar9300_modal_eep_header modalHeader5G;
296 struct ar9300_BaseExtension_2 base_ext2;
297 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
298 struct ar9300_cal_data_per_freq_op_loop
299 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
300 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
301 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
302 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
303 struct cal_tgt_pow_legacy
304 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
305 struct cal_tgt_pow_ht
306 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
307 struct cal_tgt_pow_ht
308 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
309 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
310 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
311 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
314 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
315 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
317 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);