2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p0_initvals.h"
20 #include "ar9003_2p2_initvals.h"
22 /* General hardware code for the AR9003 hadware family */
24 static bool ar9003_hw_macversion_supported(u32 macversion)
27 case AR_SREV_VERSION_9300:
36 static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)
39 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
42 ARRAY_SIZE(ar9300_2p0_mac_core), 2);
43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
44 ar9300_2p0_mac_postamble,
45 ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
48 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
50 ar9300_2p0_baseband_core,
51 ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
53 ar9300_2p0_baseband_postamble,
54 ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
59 ar9300_2p0_radio_core,
60 ARRAY_SIZE(ar9300_2p0_radio_core), 2);
61 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
62 ar9300_2p0_radio_postamble,
63 ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
66 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
67 ar9300_2p0_soc_preamble,
68 ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
69 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
70 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
71 ar9300_2p0_soc_postamble,
72 ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
75 INIT_INI_ARRAY(&ah->iniModesRxGain,
76 ar9300Common_rx_gain_table_2p0,
77 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
78 INIT_INI_ARRAY(&ah->iniModesTxGain,
79 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
80 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
83 /* Load PCIE SERDES settings from INI */
87 INIT_INI_ARRAY(&ah->iniPcieSerdes,
88 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
89 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
94 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
95 ar9300PciePhy_clkreq_enable_L1_2p0,
96 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
99 /* Fast clock modal settings */
100 INIT_INI_ARRAY(&ah->iniModesAdditional,
101 ar9300Modes_fast_clock_2p0,
102 ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
107 static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)
110 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
111 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
113 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
114 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
115 ar9300_2p2_mac_postamble,
116 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
119 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
120 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
121 ar9300_2p2_baseband_core,
122 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
123 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
124 ar9300_2p2_baseband_postamble,
125 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
128 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
129 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
130 ar9300_2p2_radio_core,
131 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
132 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
133 ar9300_2p2_radio_postamble,
134 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
137 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
138 ar9300_2p2_soc_preamble,
139 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
140 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
141 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
142 ar9300_2p2_soc_postamble,
143 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
146 INIT_INI_ARRAY(&ah->iniModesRxGain,
147 ar9300Common_rx_gain_table_2p2,
148 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
149 INIT_INI_ARRAY(&ah->iniModesTxGain,
150 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
151 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
154 /* Load PCIE SERDES settings from INI */
158 INIT_INI_ARRAY(&ah->iniPcieSerdes,
159 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
160 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
165 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
166 ar9300PciePhy_clkreq_enable_L1_2p2,
167 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
170 /* Fast clock modal settings */
171 INIT_INI_ARRAY(&ah->iniModesAdditional,
172 ar9300Modes_fast_clock_2p2,
173 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
178 * The AR9003 family uses a new INI format (pre, core, post
179 * arrays per subsystem).
181 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
183 if (AR_SREV_9300_20(ah))
184 ar9003_2p0_hw_init_mode_regs(ah);
186 ar9003_2p2_hw_init_mode_regs(ah);
189 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
191 switch (ar9003_hw_get_tx_gain_idx(ah)) {
194 if (AR_SREV_9300_20(ah))
195 INIT_INI_ARRAY(&ah->iniModesTxGain,
196 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
197 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
200 INIT_INI_ARRAY(&ah->iniModesTxGain,
201 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
202 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
206 if (AR_SREV_9300_20(ah))
207 INIT_INI_ARRAY(&ah->iniModesTxGain,
208 ar9300Modes_high_ob_db_tx_gain_table_2p0,
209 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
212 INIT_INI_ARRAY(&ah->iniModesTxGain,
213 ar9300Modes_high_ob_db_tx_gain_table_2p2,
214 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
218 if (AR_SREV_9300_20(ah))
219 INIT_INI_ARRAY(&ah->iniModesTxGain,
220 ar9300Modes_low_ob_db_tx_gain_table_2p0,
221 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
224 INIT_INI_ARRAY(&ah->iniModesTxGain,
225 ar9300Modes_low_ob_db_tx_gain_table_2p2,
226 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
232 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
234 switch (ar9003_hw_get_rx_gain_idx(ah)) {
237 if (AR_SREV_9300_20(ah))
238 INIT_INI_ARRAY(&ah->iniModesRxGain,
239 ar9300Common_rx_gain_table_2p0,
240 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
243 INIT_INI_ARRAY(&ah->iniModesRxGain,
244 ar9300Common_rx_gain_table_2p2,
245 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
249 if (AR_SREV_9300_20(ah))
250 INIT_INI_ARRAY(&ah->iniModesRxGain,
251 ar9300Common_wo_xlna_rx_gain_table_2p0,
252 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
255 INIT_INI_ARRAY(&ah->iniModesRxGain,
256 ar9300Common_wo_xlna_rx_gain_table_2p2,
257 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
263 /* set gain table pointers according to values read from the eeprom */
264 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
266 ar9003_tx_gain_table_apply(ah);
267 ar9003_rx_gain_table_apply(ah);
271 * Helper for ASPM support.
273 * Disable PLL when in L0s as well as receiver clock when in L1.
274 * This power saving option must be enabled through the SerDes.
276 * Programming the SerDes must go through the same 288 bit serial shift
277 * register as the other analog registers. Hence the 9 writes.
279 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
283 if (ah->is_pciexpress != true)
286 /* Do not touch SerDes registers */
287 if (ah->config.pcie_powersave_enable == 2)
290 /* Nothing to do on restore for 11N */
292 /* set bit 19 to allow forcing of pcie core into L1 state */
293 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
295 /* Several PCIe massages to ensure proper behaviour */
296 if (ah->config.pcie_waen)
297 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
299 REG_WRITE(ah, AR_WA, ah->WARegVal);
303 * Configire PCIE after Ini init. SERDES values now come from ini file
304 * This enables PCIe low power mode.
306 if (ah->config.pcieSerDesWrite) {
308 struct ar5416IniArray *array;
310 array = power_off ? &ah->iniPcieSerdes :
311 &ah->iniPcieSerdesLowPower;
313 for (i = 0; i < array->ia_rows; i++) {
316 INI_RA(array, i, 1));
321 /* Sets up the AR9003 hardware familiy callbacks */
322 void ar9003_hw_attach_ops(struct ath_hw *ah)
324 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
325 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
327 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
328 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
329 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
331 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
333 ar9003_hw_attach_phy_ops(ah);
334 ar9003_hw_attach_calib_ops(ah);
335 ar9003_hw_attach_mac_ops(ah);