2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
24 #include "ar955x_1p0_initvals.h"
25 #include "ar9580_1p0_initvals.h"
26 #include "ar9462_2p0_initvals.h"
27 #include "ar9565_1p0_initvals.h"
29 /* General hardware code for the AR9003 hadware family */
32 * The AR9003 family uses a new INI format (pre, core, post
33 * arrays per subsystem). This provides support for the
34 * AR9003 2.2 chipsets.
36 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
38 if (AR_SREV_9330_11(ah)) {
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
42 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
43 ar9331_1p1_mac_postamble);
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
47 ar9331_1p1_baseband_core);
48 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
49 ar9331_1p1_baseband_postamble);
52 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
53 ar9331_1p1_radio_core);
56 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
57 ar9331_1p1_soc_preamble);
58 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
59 ar9331_1p1_soc_postamble);
62 INIT_INI_ARRAY(&ah->iniModesRxGain,
63 ar9331_common_rx_gain_1p1);
64 INIT_INI_ARRAY(&ah->iniModesTxGain,
65 ar9331_modes_lowest_ob_db_tx_gain_1p1);
67 /* Japan 2484 Mhz CCK */
68 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
69 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
71 /* additional clock settings */
73 INIT_INI_ARRAY(&ah->iniAdditional,
76 INIT_INI_ARRAY(&ah->iniAdditional,
78 } else if (AR_SREV_9330_12(ah)) {
80 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
82 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
83 ar9331_1p2_mac_postamble);
86 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
87 ar9331_1p2_baseband_core);
88 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
89 ar9331_1p2_baseband_postamble);
92 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
93 ar9331_1p2_radio_core);
96 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
97 ar9331_1p2_soc_preamble);
98 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
99 ar9331_1p2_soc_postamble);
102 INIT_INI_ARRAY(&ah->iniModesRxGain,
103 ar9331_common_rx_gain_1p2);
104 INIT_INI_ARRAY(&ah->iniModesTxGain,
105 ar9331_modes_lowest_ob_db_tx_gain_1p2);
107 /* Japan 2484 Mhz CCK */
108 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
109 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
111 /* additional clock settings */
112 if (ah->is_clk_25mhz)
113 INIT_INI_ARRAY(&ah->iniAdditional,
114 ar9331_1p2_xtal_25M);
116 INIT_INI_ARRAY(&ah->iniAdditional,
117 ar9331_1p2_xtal_40M);
118 } else if (AR_SREV_9340(ah)) {
120 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
121 ar9340_1p0_mac_core);
122 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
123 ar9340_1p0_mac_postamble);
126 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
127 ar9340_1p0_baseband_core);
128 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
129 ar9340_1p0_baseband_postamble);
132 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
133 ar9340_1p0_radio_core);
134 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
135 ar9340_1p0_radio_postamble);
138 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
139 ar9340_1p0_soc_preamble);
140 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
141 ar9340_1p0_soc_postamble);
144 INIT_INI_ARRAY(&ah->iniModesRxGain,
145 ar9340Common_wo_xlna_rx_gain_table_1p0);
146 INIT_INI_ARRAY(&ah->iniModesTxGain,
147 ar9340Modes_high_ob_db_tx_gain_table_1p0);
149 INIT_INI_ARRAY(&ah->iniModesFastClock,
150 ar9340Modes_fast_clock_1p0);
152 if (!ah->is_clk_25mhz)
153 INIT_INI_ARRAY(&ah->iniAdditional,
154 ar9340_1p0_radio_core_40M);
155 } else if (AR_SREV_9485_11(ah)) {
157 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
158 ar9485_1_1_mac_core);
159 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
160 ar9485_1_1_mac_postamble);
163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
164 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
165 ar9485_1_1_baseband_core);
166 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
167 ar9485_1_1_baseband_postamble);
170 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
171 ar9485_1_1_radio_core);
172 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
173 ar9485_1_1_radio_postamble);
176 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
177 ar9485_1_1_soc_preamble);
180 INIT_INI_ARRAY(&ah->iniModesRxGain,
181 ar9485Common_wo_xlna_rx_gain_1_1);
182 INIT_INI_ARRAY(&ah->iniModesTxGain,
183 ar9485_modes_lowest_ob_db_tx_gain_1_1);
185 /* Japan 2484 Mhz CCK */
186 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
187 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
189 /* Load PCIE SERDES settings from INI */
193 INIT_INI_ARRAY(&ah->iniPcieSerdes,
194 ar9485_1_1_pcie_phy_clkreq_disable_L1);
198 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
199 ar9485_1_1_pcie_phy_clkreq_disable_L1);
200 } else if (AR_SREV_9462_20(ah)) {
202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
203 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
204 ar9462_2p0_mac_postamble);
206 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
207 ar9462_2p0_baseband_core);
208 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
209 ar9462_2p0_baseband_postamble);
211 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
212 ar9462_2p0_radio_core);
213 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
214 ar9462_2p0_radio_postamble);
215 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
216 ar9462_2p0_radio_postamble_sys2ant);
218 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
219 ar9462_2p0_soc_preamble);
220 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
221 ar9462_2p0_soc_postamble);
223 INIT_INI_ARRAY(&ah->iniModesRxGain,
224 ar9462_common_rx_gain_table_2p0);
226 /* Awake -> Sleep Setting */
227 INIT_INI_ARRAY(&ah->iniPcieSerdes,
228 ar9462_pciephy_clkreq_disable_L1_2p0);
229 /* Sleep -> Awake Setting */
230 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
231 ar9462_pciephy_clkreq_disable_L1_2p0);
233 /* Fast clock modal settings */
234 INIT_INI_ARRAY(&ah->iniModesFastClock,
235 ar9462_modes_fast_clock_2p0);
237 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
238 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
239 } else if (AR_SREV_9550(ah)) {
241 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
242 ar955x_1p0_mac_core);
243 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
244 ar955x_1p0_mac_postamble);
247 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
248 ar955x_1p0_baseband_core);
249 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
250 ar955x_1p0_baseband_postamble);
253 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
254 ar955x_1p0_radio_core);
255 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
256 ar955x_1p0_radio_postamble);
259 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
260 ar955x_1p0_soc_preamble);
261 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
262 ar955x_1p0_soc_postamble);
265 INIT_INI_ARRAY(&ah->iniModesRxGain,
266 ar955x_1p0_common_wo_xlna_rx_gain_table);
267 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
268 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
269 INIT_INI_ARRAY(&ah->iniModesTxGain,
270 ar955x_1p0_modes_xpa_tx_gain_table);
272 /* Fast clock modal settings */
273 INIT_INI_ARRAY(&ah->iniModesFastClock,
274 ar955x_1p0_modes_fast_clock);
275 } else if (AR_SREV_9580(ah)) {
277 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
278 ar9580_1p0_mac_core);
279 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
280 ar9580_1p0_mac_postamble);
283 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
284 ar9580_1p0_baseband_core);
285 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
286 ar9580_1p0_baseband_postamble);
289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
290 ar9580_1p0_radio_core);
291 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
292 ar9580_1p0_radio_postamble);
295 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
296 ar9580_1p0_soc_preamble);
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
298 ar9580_1p0_soc_postamble);
301 INIT_INI_ARRAY(&ah->iniModesRxGain,
302 ar9580_1p0_rx_gain_table);
303 INIT_INI_ARRAY(&ah->iniModesTxGain,
304 ar9580_1p0_low_ob_db_tx_gain_table);
306 INIT_INI_ARRAY(&ah->iniModesFastClock,
307 ar9580_1p0_modes_fast_clock);
308 } else if (AR_SREV_9565(ah)) {
309 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
310 ar9565_1p0_mac_core);
311 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
312 ar9565_1p0_mac_postamble);
314 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
315 ar9565_1p0_baseband_core);
316 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
317 ar9565_1p0_baseband_postamble);
319 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
320 ar9565_1p0_radio_core);
321 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
322 ar9565_1p0_radio_postamble);
324 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
325 ar9565_1p0_soc_preamble);
326 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
327 ar9565_1p0_soc_postamble);
329 INIT_INI_ARRAY(&ah->iniModesRxGain,
330 ar9565_1p0_Common_rx_gain_table);
331 INIT_INI_ARRAY(&ah->iniModesTxGain,
332 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
334 INIT_INI_ARRAY(&ah->iniPcieSerdes,
335 ar9565_1p0_pciephy_clkreq_disable_L1);
336 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
337 ar9565_1p0_pciephy_clkreq_disable_L1);
339 INIT_INI_ARRAY(&ah->iniModesFastClock,
340 ar9565_1p0_modes_fast_clock);
343 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
344 ar9300_2p2_mac_core);
345 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
346 ar9300_2p2_mac_postamble);
349 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
350 ar9300_2p2_baseband_core);
351 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
352 ar9300_2p2_baseband_postamble);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
356 ar9300_2p2_radio_core);
357 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
358 ar9300_2p2_radio_postamble);
361 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
362 ar9300_2p2_soc_preamble);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
364 ar9300_2p2_soc_postamble);
367 INIT_INI_ARRAY(&ah->iniModesRxGain,
368 ar9300Common_rx_gain_table_2p2);
369 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
372 /* Load PCIE SERDES settings from INI */
376 INIT_INI_ARRAY(&ah->iniPcieSerdes,
377 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
381 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
382 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
384 /* Fast clock modal settings */
385 INIT_INI_ARRAY(&ah->iniModesFastClock,
386 ar9300Modes_fast_clock_2p2);
390 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
392 if (AR_SREV_9330_12(ah))
393 INIT_INI_ARRAY(&ah->iniModesTxGain,
394 ar9331_modes_lowest_ob_db_tx_gain_1p2);
395 else if (AR_SREV_9330_11(ah))
396 INIT_INI_ARRAY(&ah->iniModesTxGain,
397 ar9331_modes_lowest_ob_db_tx_gain_1p1);
398 else if (AR_SREV_9340(ah))
399 INIT_INI_ARRAY(&ah->iniModesTxGain,
400 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
401 else if (AR_SREV_9485_11(ah))
402 INIT_INI_ARRAY(&ah->iniModesTxGain,
403 ar9485_modes_lowest_ob_db_tx_gain_1_1);
404 else if (AR_SREV_9550(ah))
405 INIT_INI_ARRAY(&ah->iniModesTxGain,
406 ar955x_1p0_modes_xpa_tx_gain_table);
407 else if (AR_SREV_9580(ah))
408 INIT_INI_ARRAY(&ah->iniModesTxGain,
409 ar9580_1p0_lowest_ob_db_tx_gain_table);
410 else if (AR_SREV_9462_20(ah))
411 INIT_INI_ARRAY(&ah->iniModesTxGain,
412 ar9462_modes_low_ob_db_tx_gain_table_2p0);
413 else if (AR_SREV_9565(ah))
414 INIT_INI_ARRAY(&ah->iniModesTxGain,
415 ar9565_1p0_modes_low_ob_db_tx_gain_table);
417 INIT_INI_ARRAY(&ah->iniModesTxGain,
418 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
421 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
423 if (AR_SREV_9330_12(ah))
424 INIT_INI_ARRAY(&ah->iniModesTxGain,
425 ar9331_modes_high_ob_db_tx_gain_1p2);
426 else if (AR_SREV_9330_11(ah))
427 INIT_INI_ARRAY(&ah->iniModesTxGain,
428 ar9331_modes_high_ob_db_tx_gain_1p1);
429 else if (AR_SREV_9340(ah))
430 INIT_INI_ARRAY(&ah->iniModesTxGain,
431 ar9340Modes_high_ob_db_tx_gain_table_1p0);
432 else if (AR_SREV_9485_11(ah))
433 INIT_INI_ARRAY(&ah->iniModesTxGain,
434 ar9485Modes_high_ob_db_tx_gain_1_1);
435 else if (AR_SREV_9580(ah))
436 INIT_INI_ARRAY(&ah->iniModesTxGain,
437 ar9580_1p0_high_ob_db_tx_gain_table);
438 else if (AR_SREV_9550(ah))
439 INIT_INI_ARRAY(&ah->iniModesTxGain,
440 ar955x_1p0_modes_no_xpa_tx_gain_table);
441 else if (AR_SREV_9462_20(ah))
442 INIT_INI_ARRAY(&ah->iniModesTxGain,
443 ar9462_modes_high_ob_db_tx_gain_table_2p0);
444 else if (AR_SREV_9565(ah))
445 INIT_INI_ARRAY(&ah->iniModesTxGain,
446 ar9565_1p0_modes_high_ob_db_tx_gain_table);
448 INIT_INI_ARRAY(&ah->iniModesTxGain,
449 ar9300Modes_high_ob_db_tx_gain_table_2p2);
452 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
454 if (AR_SREV_9330_12(ah))
455 INIT_INI_ARRAY(&ah->iniModesTxGain,
456 ar9331_modes_low_ob_db_tx_gain_1p2);
457 else if (AR_SREV_9330_11(ah))
458 INIT_INI_ARRAY(&ah->iniModesTxGain,
459 ar9331_modes_low_ob_db_tx_gain_1p1);
460 else if (AR_SREV_9340(ah))
461 INIT_INI_ARRAY(&ah->iniModesTxGain,
462 ar9340Modes_low_ob_db_tx_gain_table_1p0);
463 else if (AR_SREV_9485_11(ah))
464 INIT_INI_ARRAY(&ah->iniModesTxGain,
465 ar9485Modes_low_ob_db_tx_gain_1_1);
466 else if (AR_SREV_9580(ah))
467 INIT_INI_ARRAY(&ah->iniModesTxGain,
468 ar9580_1p0_low_ob_db_tx_gain_table);
469 else if (AR_SREV_9565(ah))
470 INIT_INI_ARRAY(&ah->iniModesTxGain,
471 ar9565_1p0_modes_low_ob_db_tx_gain_table);
473 INIT_INI_ARRAY(&ah->iniModesTxGain,
474 ar9300Modes_low_ob_db_tx_gain_table_2p2);
477 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
479 if (AR_SREV_9330_12(ah))
480 INIT_INI_ARRAY(&ah->iniModesTxGain,
481 ar9331_modes_high_power_tx_gain_1p2);
482 else if (AR_SREV_9330_11(ah))
483 INIT_INI_ARRAY(&ah->iniModesTxGain,
484 ar9331_modes_high_power_tx_gain_1p1);
485 else if (AR_SREV_9340(ah))
486 INIT_INI_ARRAY(&ah->iniModesTxGain,
487 ar9340Modes_high_power_tx_gain_table_1p0);
488 else if (AR_SREV_9485_11(ah))
489 INIT_INI_ARRAY(&ah->iniModesTxGain,
490 ar9485Modes_high_power_tx_gain_1_1);
491 else if (AR_SREV_9580(ah))
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9580_1p0_high_power_tx_gain_table);
494 else if (AR_SREV_9565(ah))
495 INIT_INI_ARRAY(&ah->iniModesTxGain,
496 ar9565_1p0_modes_high_power_tx_gain_table);
498 INIT_INI_ARRAY(&ah->iniModesTxGain,
499 ar9300Modes_high_power_tx_gain_table_2p2);
502 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
504 if (AR_SREV_9340(ah))
505 INIT_INI_ARRAY(&ah->iniModesTxGain,
506 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
507 else if (AR_SREV_9580(ah))
508 INIT_INI_ARRAY(&ah->iniModesTxGain,
509 ar9580_1p0_mixed_ob_db_tx_gain_table);
512 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
514 switch (ar9003_hw_get_tx_gain_idx(ah)) {
517 ar9003_tx_gain_table_mode0(ah);
520 ar9003_tx_gain_table_mode1(ah);
523 ar9003_tx_gain_table_mode2(ah);
526 ar9003_tx_gain_table_mode3(ah);
529 ar9003_tx_gain_table_mode4(ah);
534 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
536 if (AR_SREV_9330_12(ah))
537 INIT_INI_ARRAY(&ah->iniModesRxGain,
538 ar9331_common_rx_gain_1p2);
539 else if (AR_SREV_9330_11(ah))
540 INIT_INI_ARRAY(&ah->iniModesRxGain,
541 ar9331_common_rx_gain_1p1);
542 else if (AR_SREV_9340(ah))
543 INIT_INI_ARRAY(&ah->iniModesRxGain,
544 ar9340Common_rx_gain_table_1p0);
545 else if (AR_SREV_9485_11(ah))
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9485Common_wo_xlna_rx_gain_1_1);
548 else if (AR_SREV_9550(ah)) {
549 INIT_INI_ARRAY(&ah->iniModesRxGain,
550 ar955x_1p0_common_rx_gain_table);
551 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
552 ar955x_1p0_common_rx_gain_bounds);
553 } else if (AR_SREV_9580(ah))
554 INIT_INI_ARRAY(&ah->iniModesRxGain,
555 ar9580_1p0_rx_gain_table);
556 else if (AR_SREV_9462_20(ah))
557 INIT_INI_ARRAY(&ah->iniModesRxGain,
558 ar9462_common_rx_gain_table_2p0);
560 INIT_INI_ARRAY(&ah->iniModesRxGain,
561 ar9300Common_rx_gain_table_2p2);
564 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
566 if (AR_SREV_9330_12(ah))
567 INIT_INI_ARRAY(&ah->iniModesRxGain,
568 ar9331_common_wo_xlna_rx_gain_1p2);
569 else if (AR_SREV_9330_11(ah))
570 INIT_INI_ARRAY(&ah->iniModesRxGain,
571 ar9331_common_wo_xlna_rx_gain_1p1);
572 else if (AR_SREV_9340(ah))
573 INIT_INI_ARRAY(&ah->iniModesRxGain,
574 ar9340Common_wo_xlna_rx_gain_table_1p0);
575 else if (AR_SREV_9485_11(ah))
576 INIT_INI_ARRAY(&ah->iniModesRxGain,
577 ar9485Common_wo_xlna_rx_gain_1_1);
578 else if (AR_SREV_9462_20(ah))
579 INIT_INI_ARRAY(&ah->iniModesRxGain,
580 ar9462_common_wo_xlna_rx_gain_table_2p0);
581 else if (AR_SREV_9550(ah)) {
582 INIT_INI_ARRAY(&ah->iniModesRxGain,
583 ar955x_1p0_common_wo_xlna_rx_gain_table);
584 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
585 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
586 } else if (AR_SREV_9580(ah))
587 INIT_INI_ARRAY(&ah->iniModesRxGain,
588 ar9580_1p0_wo_xlna_rx_gain_table);
589 else if (AR_SREV_9565(ah))
590 INIT_INI_ARRAY(&ah->iniModesRxGain,
591 ar9565_1p0_common_wo_xlna_rx_gain_table);
593 INIT_INI_ARRAY(&ah->iniModesRxGain,
594 ar9300Common_wo_xlna_rx_gain_table_2p2);
597 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
599 if (AR_SREV_9462_20(ah))
600 INIT_INI_ARRAY(&ah->iniModesRxGain,
601 ar9462_common_mixed_rx_gain_table_2p0);
604 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
606 switch (ar9003_hw_get_rx_gain_idx(ah)) {
609 ar9003_rx_gain_table_mode0(ah);
612 ar9003_rx_gain_table_mode1(ah);
615 ar9003_rx_gain_table_mode2(ah);
620 /* set gain table pointers according to values read from the eeprom */
621 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
623 ar9003_tx_gain_table_apply(ah);
624 ar9003_rx_gain_table_apply(ah);
628 * Helper for ASPM support.
630 * Disable PLL when in L0s as well as receiver clock when in L1.
631 * This power saving option must be enabled through the SerDes.
633 * Programming the SerDes must go through the same 288 bit serial shift
634 * register as the other analog registers. Hence the 9 writes.
636 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
639 /* Nothing to do on restore for 11N */
640 if (!power_off /* !restore */) {
641 /* set bit 19 to allow forcing of pcie core into L1 state */
642 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
644 /* Several PCIe massages to ensure proper behaviour */
645 if (ah->config.pcie_waen)
646 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
648 REG_WRITE(ah, AR_WA, ah->WARegVal);
652 * Configire PCIE after Ini init. SERDES values now come from ini file
653 * This enables PCIe low power mode.
655 if (ah->config.pcieSerDesWrite) {
657 struct ar5416IniArray *array;
659 array = power_off ? &ah->iniPcieSerdes :
660 &ah->iniPcieSerdesLowPower;
662 for (i = 0; i < array->ia_rows; i++) {
665 INI_RA(array, i, 1));
670 /* Sets up the AR9003 hardware familiy callbacks */
671 void ar9003_hw_attach_ops(struct ath_hw *ah)
673 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
674 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
676 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
677 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
679 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
681 ar9003_hw_attach_phy_ops(ah);
682 ar9003_hw_attach_calib_ops(ah);
683 ar9003_hw_attach_mac_ops(ah);