2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
25 /* General hardware code for the AR9003 hadware family */
28 * The AR9003 family uses a new INI format (pre, core, post
29 * arrays per subsystem). This provides support for the
30 * AR9003 2.2 chipsets.
32 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
34 if (AR_SREV_9330_11(ah)) {
36 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
37 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
39 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
41 ar9331_1p1_mac_postamble,
42 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
45 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
47 ar9331_1p1_baseband_core,
48 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
50 ar9331_1p1_baseband_postamble,
51 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
54 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
55 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
56 ar9331_1p1_radio_core,
57 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
62 ar9331_1p1_soc_preamble,
63 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
66 ar9331_1p1_soc_postamble,
67 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
70 INIT_INI_ARRAY(&ah->iniModesRxGain,
71 ar9331_common_rx_gain_1p1,
72 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
73 INIT_INI_ARRAY(&ah->iniModesTxGain,
74 ar9331_modes_lowest_ob_db_tx_gain_1p1,
75 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
78 /* additional clock settings */
80 INIT_INI_ARRAY(&ah->iniModesAdditional,
82 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
84 INIT_INI_ARRAY(&ah->iniModesAdditional,
86 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
87 } else if (AR_SREV_9330_12(ah)) {
89 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
90 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
92 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
94 ar9331_1p2_mac_postamble,
95 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
98 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
99 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
100 ar9331_1p2_baseband_core,
101 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
103 ar9331_1p2_baseband_postamble,
104 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
107 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
108 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
109 ar9331_1p2_radio_core,
110 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
111 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
114 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
115 ar9331_1p2_soc_preamble,
116 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
117 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
119 ar9331_1p2_soc_postamble,
120 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
123 INIT_INI_ARRAY(&ah->iniModesRxGain,
124 ar9331_common_rx_gain_1p2,
125 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
126 INIT_INI_ARRAY(&ah->iniModesTxGain,
127 ar9331_modes_lowest_ob_db_tx_gain_1p2,
128 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
131 /* additional clock settings */
132 if (ah->is_clk_25mhz)
133 INIT_INI_ARRAY(&ah->iniModesAdditional,
135 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
137 INIT_INI_ARRAY(&ah->iniModesAdditional,
139 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
140 } else if (AR_SREV_9340(ah)) {
142 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
143 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
145 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
146 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
147 ar9340_1p0_mac_postamble,
148 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
151 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
152 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
153 ar9340_1p0_baseband_core,
154 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
155 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
156 ar9340_1p0_baseband_postamble,
157 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
160 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
161 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
162 ar9340_1p0_radio_core,
163 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
164 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
165 ar9340_1p0_radio_postamble,
166 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
169 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
170 ar9340_1p0_soc_preamble,
171 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
172 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
173 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
174 ar9340_1p0_soc_postamble,
175 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
178 INIT_INI_ARRAY(&ah->iniModesRxGain,
179 ar9340Common_wo_xlna_rx_gain_table_1p0,
180 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
182 INIT_INI_ARRAY(&ah->iniModesTxGain,
183 ar9340Modes_high_ob_db_tx_gain_table_1p0,
184 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
187 INIT_INI_ARRAY(&ah->iniModesAdditional,
188 ar9340Modes_fast_clock_1p0,
189 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
192 INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
193 ar9340_1p0_radio_core_40M,
194 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
196 } else if (AR_SREV_9485_11(ah)) {
198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
199 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
201 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
203 ar9485_1_1_mac_postamble,
204 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
207 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
208 ARRAY_SIZE(ar9485_1_1), 2);
209 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
210 ar9485_1_1_baseband_core,
211 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
212 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
213 ar9485_1_1_baseband_postamble,
214 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
217 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
219 ar9485_1_1_radio_core,
220 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
221 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
222 ar9485_1_1_radio_postamble,
223 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
227 ar9485_1_1_soc_preamble,
228 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
229 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
230 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
233 INIT_INI_ARRAY(&ah->iniModesRxGain,
234 ar9485Common_wo_xlna_rx_gain_1_1,
235 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
236 INIT_INI_ARRAY(&ah->iniModesTxGain,
237 ar9485_modes_lowest_ob_db_tx_gain_1_1,
238 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
241 /* Load PCIE SERDES settings from INI */
245 INIT_INI_ARRAY(&ah->iniPcieSerdes,
246 ar9485_1_1_pcie_phy_clkreq_disable_L1,
247 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
252 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
253 ar9485_1_1_pcie_phy_clkreq_disable_L1,
254 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
258 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
259 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
261 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
262 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
263 ar9300_2p2_mac_postamble,
264 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
267 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
268 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
269 ar9300_2p2_baseband_core,
270 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
271 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
272 ar9300_2p2_baseband_postamble,
273 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
276 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
278 ar9300_2p2_radio_core,
279 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
280 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
281 ar9300_2p2_radio_postamble,
282 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
285 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
286 ar9300_2p2_soc_preamble,
287 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
288 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
289 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
290 ar9300_2p2_soc_postamble,
291 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
294 INIT_INI_ARRAY(&ah->iniModesRxGain,
295 ar9300Common_rx_gain_table_2p2,
296 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
297 INIT_INI_ARRAY(&ah->iniModesTxGain,
298 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
299 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
302 /* Load PCIE SERDES settings from INI */
306 INIT_INI_ARRAY(&ah->iniPcieSerdes,
307 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
308 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
313 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
314 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
315 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
318 /* Fast clock modal settings */
319 INIT_INI_ARRAY(&ah->iniModesAdditional,
320 ar9300Modes_fast_clock_2p2,
321 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
326 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
328 switch (ar9003_hw_get_tx_gain_idx(ah)) {
331 if (AR_SREV_9330_12(ah))
332 INIT_INI_ARRAY(&ah->iniModesTxGain,
333 ar9331_modes_lowest_ob_db_tx_gain_1p2,
334 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
336 else if (AR_SREV_9330_11(ah))
337 INIT_INI_ARRAY(&ah->iniModesTxGain,
338 ar9331_modes_lowest_ob_db_tx_gain_1p1,
339 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
341 else if (AR_SREV_9340(ah))
342 INIT_INI_ARRAY(&ah->iniModesTxGain,
343 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
344 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
346 else if (AR_SREV_9485_11(ah))
347 INIT_INI_ARRAY(&ah->iniModesTxGain,
348 ar9485_modes_lowest_ob_db_tx_gain_1_1,
349 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
352 INIT_INI_ARRAY(&ah->iniModesTxGain,
353 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
354 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
358 if (AR_SREV_9330_12(ah))
359 INIT_INI_ARRAY(&ah->iniModesTxGain,
360 ar9331_modes_high_ob_db_tx_gain_1p2,
361 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
363 else if (AR_SREV_9330_11(ah))
364 INIT_INI_ARRAY(&ah->iniModesTxGain,
365 ar9331_modes_high_ob_db_tx_gain_1p1,
366 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
368 else if (AR_SREV_9340(ah))
369 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
371 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
373 else if (AR_SREV_9485_11(ah))
374 INIT_INI_ARRAY(&ah->iniModesTxGain,
375 ar9485Modes_high_ob_db_tx_gain_1_1,
376 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
379 INIT_INI_ARRAY(&ah->iniModesTxGain,
380 ar9300Modes_high_ob_db_tx_gain_table_2p2,
381 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
385 if (AR_SREV_9330_12(ah))
386 INIT_INI_ARRAY(&ah->iniModesTxGain,
387 ar9331_modes_low_ob_db_tx_gain_1p2,
388 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
390 else if (AR_SREV_9330_11(ah))
391 INIT_INI_ARRAY(&ah->iniModesTxGain,
392 ar9331_modes_low_ob_db_tx_gain_1p1,
393 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
395 else if (AR_SREV_9340(ah))
396 INIT_INI_ARRAY(&ah->iniModesTxGain,
397 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
398 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
400 else if (AR_SREV_9485_11(ah))
401 INIT_INI_ARRAY(&ah->iniModesTxGain,
402 ar9485Modes_low_ob_db_tx_gain_1_1,
403 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
406 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 ar9300Modes_low_ob_db_tx_gain_table_2p2,
408 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
412 if (AR_SREV_9330_12(ah))
413 INIT_INI_ARRAY(&ah->iniModesTxGain,
414 ar9331_modes_high_power_tx_gain_1p2,
415 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
417 else if (AR_SREV_9330_11(ah))
418 INIT_INI_ARRAY(&ah->iniModesTxGain,
419 ar9331_modes_high_power_tx_gain_1p1,
420 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
422 else if (AR_SREV_9340(ah))
423 INIT_INI_ARRAY(&ah->iniModesTxGain,
424 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
425 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
427 else if (AR_SREV_9485_11(ah))
428 INIT_INI_ARRAY(&ah->iniModesTxGain,
429 ar9485Modes_high_power_tx_gain_1_1,
430 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
433 INIT_INI_ARRAY(&ah->iniModesTxGain,
434 ar9300Modes_high_power_tx_gain_table_2p2,
435 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
441 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
443 switch (ar9003_hw_get_rx_gain_idx(ah)) {
446 if (AR_SREV_9330_12(ah))
447 INIT_INI_ARRAY(&ah->iniModesRxGain,
448 ar9331_common_rx_gain_1p2,
449 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
451 else if (AR_SREV_9330_11(ah))
452 INIT_INI_ARRAY(&ah->iniModesRxGain,
453 ar9331_common_rx_gain_1p1,
454 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
456 else if (AR_SREV_9340(ah))
457 INIT_INI_ARRAY(&ah->iniModesRxGain,
458 ar9340Common_rx_gain_table_1p0,
459 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
461 else if (AR_SREV_9485_11(ah))
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9485Common_wo_xlna_rx_gain_1_1,
464 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
467 INIT_INI_ARRAY(&ah->iniModesRxGain,
468 ar9300Common_rx_gain_table_2p2,
469 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
473 if (AR_SREV_9330_12(ah))
474 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9331_common_wo_xlna_rx_gain_1p2,
476 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
478 else if (AR_SREV_9330_11(ah))
479 INIT_INI_ARRAY(&ah->iniModesRxGain,
480 ar9331_common_wo_xlna_rx_gain_1p1,
481 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
483 else if (AR_SREV_9340(ah))
484 INIT_INI_ARRAY(&ah->iniModesRxGain,
485 ar9340Common_wo_xlna_rx_gain_table_1p0,
486 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
488 else if (AR_SREV_9485_11(ah))
489 INIT_INI_ARRAY(&ah->iniModesRxGain,
490 ar9485Common_wo_xlna_rx_gain_1_1,
491 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
494 INIT_INI_ARRAY(&ah->iniModesRxGain,
495 ar9300Common_wo_xlna_rx_gain_table_2p2,
496 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
502 /* set gain table pointers according to values read from the eeprom */
503 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
505 ar9003_tx_gain_table_apply(ah);
506 ar9003_rx_gain_table_apply(ah);
510 * Helper for ASPM support.
512 * Disable PLL when in L0s as well as receiver clock when in L1.
513 * This power saving option must be enabled through the SerDes.
515 * Programming the SerDes must go through the same 288 bit serial shift
516 * register as the other analog registers. Hence the 9 writes.
518 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
522 if (ah->is_pciexpress != true)
525 /* Do not touch SerDes registers */
526 if (ah->config.pcie_powersave_enable == 2)
529 /* Nothing to do on restore for 11N */
531 /* set bit 19 to allow forcing of pcie core into L1 state */
532 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
534 /* Several PCIe massages to ensure proper behaviour */
535 if (ah->config.pcie_waen)
536 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
538 REG_WRITE(ah, AR_WA, ah->WARegVal);
542 * Configire PCIE after Ini init. SERDES values now come from ini file
543 * This enables PCIe low power mode.
545 if (ah->config.pcieSerDesWrite) {
547 struct ar5416IniArray *array;
549 array = power_off ? &ah->iniPcieSerdes :
550 &ah->iniPcieSerdesLowPower;
552 for (i = 0; i < array->ia_rows; i++) {
555 INI_RA(array, i, 1));
560 /* Sets up the AR9003 hardware familiy callbacks */
561 void ar9003_hw_attach_ops(struct ath_hw *ah)
563 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
564 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
566 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
567 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
569 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
571 ar9003_hw_attach_phy_ops(ah);
572 ar9003_hw_attach_calib_ops(ah);
573 ar9003_hw_attach_mac_ops(ah);