drivers/net/wireless/ath/ath9k/ar9003_mci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_mci.h"
  21
  22 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
  23 {
  24         if (!AR_SREV_9462_20(ah))
  25                 return;
  26
  27         REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
  28                       AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1);
  29         udelay(1);
  30         REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
  31                       AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0);
  32 }
  33
  34 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
  35                                         u32 bit_position, int time_out)
  36 {
  37         struct ath_common *common = ath9k_hw_common(ah);
  38
  39         while (time_out) {
  40
  41                 if (REG_READ(ah, address) & bit_position) {
  42
  43                         REG_WRITE(ah, address, bit_position);
  44
  45                         if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
  46
  47                                 if (bit_position &
  48                                     AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
  49                                         ar9003_mci_reset_req_wakeup(ah);
  50
  51                                 if (bit_position &
  52                                     (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
  53                                      AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
  54                                         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
  55                                         AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
  56
  57                                 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
  58                                           AR_MCI_INTERRUPT_RX_MSG);
  59                         }
  60                         break;
  61                 }
  62
  63                 udelay(10);
  64                 time_out -= 10;
  65
  66                 if (time_out < 0)
  67                         break;
  68         }
  69
  70         if (time_out <= 0) {
  71                 ath_dbg(common, MCI,
  72                         "MCI Wait for Reg 0x%08x = 0x%08x timeout\n",
  73                         address, bit_position);
  74                 ath_dbg(common, MCI,
  75                         "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x\n",
  76                         REG_READ(ah, AR_MCI_INTERRUPT_RAW),
  77                         REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
  78                 time_out = 0;
  79         }
  80
  81         return time_out;
  82 }
  83
  84 void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
  85 {
  86         u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
  87
  88         if (!ATH9K_HW_CAP_MCI)
  89                 return;
  90
  91         ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
  92                                 wait_done, false);
  93         udelay(5);
  94 }
  95
  96 void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
  97 {
  98         u32 payload = 0x00000000;
  99
 100         if (!ATH9K_HW_CAP_MCI)
 101                 return;
 102
 103         ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
 104                                 wait_done, false);
 105 }
 106
 107 static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
 108 {
 109         ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP,
 110                                 NULL, 0, wait_done, false);
 111         udelay(5);
 112 }
 113
 114 void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
 115 {
 116         if (!ATH9K_HW_CAP_MCI)
 117                 return;
 118
 119         ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
 120                                 NULL, 0, wait_done, false);
 121 }
 122
 123 static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done)
 124 {
 125         u32 payload = 0x70000000;
 126
 127         ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1,
 128                                 wait_done, false);
 129 }
 130
 131 static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done)
 132 {
 133         ar9003_mci_send_message(ah, MCI_SYS_SLEEPING,
 134                                 MCI_FLAG_DISABLE_TIMESTAMP,
 135                                 NULL, 0, wait_done, false);
 136 }
 137
 138 static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
 139                                                bool wait_done)
 140 {
 141         struct ath_common *common = ath9k_hw_common(ah);
 142         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 143         u32 payload[4] = {0, 0, 0, 0};
 144
 145         if (!mci->bt_version_known &&
 146                         (mci->bt_state != MCI_BT_SLEEP)) {
 147                 ath_dbg(common, MCI, "MCI Send Coex version query\n");
 148                 MCI_GPM_SET_TYPE_OPCODE(payload,
 149                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY);
 150                 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 151                                 wait_done, true);
 152         }
 153 }
 154
 155 static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
 156                                                      bool wait_done)
 157 {
 158         struct ath_common *common = ath9k_hw_common(ah);
 159         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 160         u32 payload[4] = {0, 0, 0, 0};
 161
 162         ath_dbg(common, MCI, "MCI Send Coex version response\n");
 163         MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
 164                         MCI_GPM_COEX_VERSION_RESPONSE);
 165         *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) =
 166                 mci->wlan_ver_major;
 167         *(((u8 *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) =
 168                 mci->wlan_ver_minor;
 169         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
 170 }
 171
 172 static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
 173                                                   bool wait_done)
 174 {
 175         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 176         u32 *payload = &mci->wlan_channels[0];
 177
 178         if ((mci->wlan_channels_update == true) &&
 179                         (mci->bt_state != MCI_BT_SLEEP)) {
 180                 MCI_GPM_SET_TYPE_OPCODE(payload,
 181                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_WLAN_CHANNELS);
 182                 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 183                                         wait_done, true);
 184                 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff);
 185         }
 186 }
 187
 188 static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
 189                                                 bool wait_done, u8 query_type)
 190 {
 191         struct ath_common *common = ath9k_hw_common(ah);
 192         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 193         u32 payload[4] = {0, 0, 0, 0};
 194         bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO |
 195                                              MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
 196
 197         if (mci->bt_state != MCI_BT_SLEEP) {
 198
 199                 ath_dbg(common, MCI, "MCI Send Coex BT Status Query 0x%02X\n",
 200                         query_type);
 201
 202                 MCI_GPM_SET_TYPE_OPCODE(payload,
 203                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY);
 204
 205                 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type;
 206                 /*
 207                  * If bt_status_query message is  not sent successfully,
 208                  * then need_flush_btinfo should be set again.
 209                  */
 210                 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 211                                              wait_done, true)) {
 212                         if (query_btinfo) {
 213                                 mci->need_flush_btinfo = true;
 214
 215                                 ath_dbg(common, MCI,
 216                                         "MCI send bt_status_query fail, set flush flag again\n");
 217                         }
 218                 }
 219
 220                 if (query_btinfo)
 221                         mci->query_bt = false;
 222         }
 223 }
 224
 225 void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
 226                                       bool wait_done)
 227 {
 228         struct ath_common *common = ath9k_hw_common(ah);
 229         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 230         u32 payload[4] = {0, 0, 0, 0};
 231
 232         if (!ATH9K_HW_CAP_MCI)
 233                 return;
 234
 235         ath_dbg(common, MCI, "MCI Send Coex %s BT GPM\n",
 236                 (halt) ? "halt" : "unhalt");
 237
 238         MCI_GPM_SET_TYPE_OPCODE(payload,
 239                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_HALT_BT_GPM);
 240
 241         if (halt) {
 242                 mci->query_bt = true;
 243                 /* Send next unhalt no matter halt sent or not */
 244                 mci->unhalt_bt_gpm = true;
 245                 mci->need_flush_btinfo = true;
 246                 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
 247                         MCI_GPM_COEX_BT_GPM_HALT;
 248         } else
 249                 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
 250                         MCI_GPM_COEX_BT_GPM_UNHALT;
 251
 252         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
 253 }
 254
 255
 256 static void ar9003_mci_prep_interface(struct ath_hw *ah)
 257 {
 258         struct ath_common *common = ath9k_hw_common(ah);
 259         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 260         u32 saved_mci_int_en;
 261         u32 mci_timeout = 150;
 262
 263         mci->bt_state = MCI_BT_SLEEP;
 264         saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
 265
 266         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 267         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 268                   REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
 269         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 270                   REG_READ(ah, AR_MCI_INTERRUPT_RAW));
 271
 272         /* Remote Reset */
 273         ath_dbg(common, MCI, "MCI Reset sequence start\n");
 274         ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");
 275         ar9003_mci_remote_reset(ah, true);
 276
 277         ath_dbg(common, MCI, "MCI Send REQ_WAKE to remoter(BT)\n");
 278         ar9003_mci_send_req_wake(ah, true);
 279
 280         if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 281                                 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) {
 282
 283                 ath_dbg(common, MCI, "MCI SYS_WAKING from remote(BT)\n");
 284                 mci->bt_state = MCI_BT_AWAKE;
 285
 286                 /*
 287                  * we don't need to send more remote_reset at this moment.
 288                  * If BT receive first remote_reset, then BT HW will
 289                  * be cleaned up and will be able to receive req_wake
 290                  * and BT HW will respond sys_waking.
 291                  * In this case, WLAN will receive BT's HW sys_waking.
 292                  * Otherwise, if BT SW missed initial remote_reset,
 293                  * that remote_reset will still clean up BT MCI RX,
 294                  * and the req_wake will wake BT up,
 295                  * and BT SW will respond this req_wake with a remote_reset and
 296                  * sys_waking. In this case, WLAN will receive BT's SW
 297                  * sys_waking. In either case, BT's RX is cleaned up. So we
 298                  * don't need to reply BT's remote_reset now, if any.
 299                  * Similarly, if in any case, WLAN can receive BT's sys_waking,
 300                  * that means WLAN's RX is also fine.
 301                  */
 302
 303                 /* Send SYS_WAKING to BT */
 304
 305                 ath_dbg(common, MCI, "MCI send SW SYS_WAKING to remote BT\n");
 306
 307                 ar9003_mci_send_sys_waking(ah, true);
 308                 udelay(10);
 309
 310                 /*
 311                  * Set BT priority interrupt value to be 0xff to
 312                  * avoid having too many BT PRIORITY interrupts.
 313                  */
 314
 315                 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
 316                 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
 317                 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
 318                 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
 319                 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
 320
 321                 /*
 322                  * A contention reset will be received after send out
 323                  * sys_waking. Also BT priority interrupt bits will be set.
 324                  * Clear those bits before the next step.
 325                  */
 326
 327                 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 328                           AR_MCI_INTERRUPT_RX_MSG_CONT_RST);
 329                 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 330                           AR_MCI_INTERRUPT_BT_PRI);
 331
 332                 if (mci->is_2g) {
 333                         /* Send LNA_TRANS */
 334                         ath_dbg(common, MCI, "MCI send LNA_TRANS to BT\n");
 335                         ar9003_mci_send_lna_transfer(ah, true);
 336                         udelay(5);
 337                 }
 338
 339                 if ((mci->is_2g && !mci->update_2g5g)) {
 340                         if (ar9003_mci_wait_for_interrupt(ah,
 341                                 AR_MCI_INTERRUPT_RX_MSG_RAW,
 342                                 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
 343                                 mci_timeout))
 344                                 ath_dbg(common, MCI,
 345                                         "MCI WLAN has control over the LNA & BT obeys it\n");
 346                         else
 347                                 ath_dbg(common, MCI,
 348                                         "MCI BT didn't respond to LNA_TRANS\n");
 349                 }
 350         }
 351
 352         /* Clear the extra redundant SYS_WAKING from BT */
 353         if ((mci->bt_state == MCI_BT_AWAKE) &&
 354                 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 355                                 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) &&
 356                 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 357                                 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) {
 358
 359                         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 360                                   AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING);
 361                         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 362                                   AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
 363         }
 364
 365         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
 366 }
 367
 368 void ar9003_mci_disable_interrupt(struct ath_hw *ah)
 369 {
 370         if (!ATH9K_HW_CAP_MCI)
 371                 return;
 372
 373         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 374         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
 375 }
 376
 377 void ar9003_mci_enable_interrupt(struct ath_hw *ah)
 378 {
 379         if (!ATH9K_HW_CAP_MCI)
 380                 return;
 381
 382         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
 383         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
 384                   AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
 385 }
 386
 387 bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
 388 {
 389         u32 intr;
 390
 391         if (!ATH9K_HW_CAP_MCI)
 392                 return false;
 393
 394         intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
 395         return ((intr & ints) == ints);
 396 }
 397
 398 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
 399                               u32 *rx_msg_intr)
 400 {
 401         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 402
 403         if (!ATH9K_HW_CAP_MCI)
 404                 return;
 405
 406         *raw_intr = mci->raw_intr;
 407         *rx_msg_intr = mci->rx_msg_intr;
 408
 409         /* Clean int bits after the values are read. */
 410         mci->raw_intr = 0;
 411         mci->rx_msg_intr = 0;
 412 }
 413 EXPORT_SYMBOL(ar9003_mci_get_interrupt);
 414
 415 void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
 416 {
 417         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 418
 419         if (!ATH9K_HW_CAP_MCI)
 420                 return;
 421
 422         if (!mci->update_2g5g &&
 423             (mci->is_2g != is_2g))
 424                 mci->update_2g5g = true;
 425
 426         mci->is_2g = is_2g;
 427 }
 428
 429 static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index)
 430 {
 431         struct ath_common *common = ath9k_hw_common(ah);
 432         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 433         u32 *payload;
 434         u32 recv_type, offset;
 435
 436         if (msg_index == MCI_GPM_INVALID)
 437                 return false;
 438
 439         offset = msg_index << 4;
 440
 441         payload = (u32 *)(mci->gpm_buf + offset);
 442         recv_type = MCI_GPM_TYPE(payload);
 443
 444         if (recv_type == MCI_GPM_RSVD_PATTERN) {
 445                 ath_dbg(common, MCI, "MCI Skip RSVD GPM\n");
 446                 return false;
 447         }
 448
 449         return true;
 450 }
 451
 452 static void ar9003_mci_observation_set_up(struct ath_hw *ah)
 453 {
 454         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 455         if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) {
 456
 457                 ath9k_hw_cfg_output(ah, 3,
 458                                         AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
 459                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
 460                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
 461                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
 462
 463         } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) {
 464
 465                 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
 466                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
 467                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
 468                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
 469                 ath9k_hw_cfg_output(ah, 5, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 470
 471         } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) {
 472
 473                 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
 474                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
 475                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
 476                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
 477
 478         } else
 479                 return;
 480
 481         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 482
 483         if (AR_SREV_9462_20_OR_LATER(ah)) {
 484                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
 485                               AR_GLB_DS_JTAG_DISABLE, 1);
 486                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
 487                               AR_GLB_WLAN_UART_INTF_EN, 0);
 488                 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL,
 489                             ATH_MCI_CONFIG_MCI_OBS_GPIO);
 490         }
 491
 492         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
 493         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
 494         REG_WRITE(ah, AR_OBS, 0x4b);
 495         REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
 496         REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
 497         REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
 498         REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
 499         REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS,
 500                       AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07);
 501 }
 502
 503 static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done,
 504                                                 u8 opcode, u32 bt_flags)
 505 {
 506         struct ath_common *common = ath9k_hw_common(ah);
 507         u32 pld[4] = {0, 0, 0, 0};
 508
 509         MCI_GPM_SET_TYPE_OPCODE(pld,
 510                         MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
 511
 512         *(((u8 *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP)  = opcode;
 513         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
 514         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = (bt_flags >> 8) & 0xFF;
 515         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF;
 516         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF;
 517
 518         ath_dbg(common, MCI,
 519                 "MCI BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n",
 520                 opcode == MCI_GPM_COEX_BT_FLAGS_READ ? "READ" :
 521                 opcode == MCI_GPM_COEX_BT_FLAGS_SET ? "SET" : "CLEAR",
 522                 bt_flags);
 523
 524         return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16,
 525                                                         wait_done, true);
 526 }
 527
 528 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 529                       bool is_full_sleep)
 530 {
 531         struct ath_common *common = ath9k_hw_common(ah);
 532         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 533         u32 regval, thresh;
 534
 535         if (!ATH9K_HW_CAP_MCI)
 536                 return;
 537
 538         ath_dbg(common, MCI, "MCI full_sleep = %d, is_2g = %d\n",
 539                 is_full_sleep, is_2g);
 540
 541         /*
 542          * GPM buffer and scheduling message buffer are not allocated
 543          */
 544
 545         if (!mci->gpm_addr && !mci->sched_addr) {
 546                 ath_dbg(common, MCI,
 547                         "MCI GPM and schedule buffers are not allocated\n");
 548                 return;
 549         }
 550
 551         if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
 552                 ath_dbg(common, MCI, "MCI it's deadbeef, quit mci_reset\n");
 553                 return;
 554         }
 555
 556         /* Program MCI DMA related registers */
 557         REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
 558         REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
 559         REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
 560
 561         /*
 562         * To avoid MCI state machine be affected by incoming remote MCI msgs,
 563         * MCI mode will be enabled later, right before reset the MCI TX and RX.
 564         */
 565
 566         regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
 567                  SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
 568                  SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
 569                  SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
 570                  SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
 571                  SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
 572                  SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
 573                  SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
 574                  SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 575
 576         if (is_2g && (AR_SREV_9462_20(ah)) &&
 577                 !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) {
 578
 579                 regval |= SM(1, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 580                 ath_dbg(common, MCI, "MCI sched one step look ahead\n");
 581
 582                 if (!(mci->config &
 583                       ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
 584
 585                         thresh = MS(mci->config,
 586                                     ATH_MCI_CONFIG_AGGR_THRESH);
 587                         thresh &= 7;
 588                         regval |= SM(1,
 589                                      AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN);
 590                         regval |= SM(thresh, AR_BTCOEX_CTRL_AGGR_THRESH);
 591
 592                         REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
 593                                       AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
 594                         REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
 595                                       AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
 596
 597                 } else
 598                         ath_dbg(common, MCI, "MCI sched aggr thresh: off\n");
 599         } else
 600                 ath_dbg(common, MCI, "MCI SCHED one step look ahead off\n");
 601
 602         REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
 603
 604         if (AR_SREV_9462_20(ah)) {
 605                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
 606                             AR_BTCOEX_CTRL_SPDT_ENABLE);
 607                 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
 608                               AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
 609         }
 610
 611         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1);
 612         REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
 613
 614         thresh = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);
 615         REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, thresh);
 616         REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
 617
 618         /* Resetting the Rx and Tx paths of MCI */
 619         regval = REG_READ(ah, AR_MCI_COMMAND2);
 620         regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
 621         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 622
 623         udelay(1);
 624
 625         regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX);
 626         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 627
 628         if (is_full_sleep) {
 629                 ar9003_mci_mute_bt(ah);
 630                 udelay(100);
 631         }
 632
 633         regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
 634         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 635         udelay(1);
 636         regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
 637         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 638
 639         ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
 640         REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
 641                   (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
 642                    SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM)));
 643
 644         REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
 645                         AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 646
 647         if (AR_SREV_9462_20_OR_LATER(ah))
 648                 ar9003_mci_observation_set_up(ah);
 649
 650         mci->ready = true;
 651         ar9003_mci_prep_interface(ah);
 652
 653         if (en_int)
 654                 ar9003_mci_enable_interrupt(ah);
 655 }
 656
 657 void ar9003_mci_mute_bt(struct ath_hw *ah)
 658 {
 659         struct ath_common *common = ath9k_hw_common(ah);
 660
 661         if (!ATH9K_HW_CAP_MCI)
 662                 return;
 663
 664         /* disable all MCI messages */
 665         REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
 666         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
 667         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
 668         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
 669         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
 670         REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 671
 672         /* wait pending HW messages to flush out */
 673         udelay(10);
 674
 675         /*
 676          * Send LNA_TAKE and SYS_SLEEPING when
 677          * 1. reset not after resuming from full sleep
 678          * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment
 679          */
 680
 681         ath_dbg(common, MCI, "MCI Send LNA take\n");
 682         ar9003_mci_send_lna_take(ah, true);
 683
 684         udelay(5);
 685
 686         ath_dbg(common, MCI, "MCI Send sys sleeping\n");
 687         ar9003_mci_send_sys_sleeping(ah, true);
 688 }
 689
 690 void ar9003_mci_sync_bt_state(struct ath_hw *ah)
 691 {
 692         struct ath_common *common = ath9k_hw_common(ah);
 693         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 694         u32 cur_bt_state;
 695
 696         if (!ATH9K_HW_CAP_MCI)
 697                 return;
 698
 699         cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
 700
 701         if (mci->bt_state != cur_bt_state) {
 702                 ath_dbg(common, MCI,
 703                         "MCI BT state mismatches. old: %d, new: %d\n",
 704                         mci->bt_state, cur_bt_state);
 705                 mci->bt_state = cur_bt_state;
 706         }
 707
 708         if (mci->bt_state != MCI_BT_SLEEP) {
 709
 710                 ar9003_mci_send_coex_version_query(ah, true);
 711                 ar9003_mci_send_coex_wlan_channels(ah, true);
 712
 713                 if (mci->unhalt_bt_gpm == true) {
 714                         ath_dbg(common, MCI, "MCI unhalt BT GPM\n");
 715                         ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
 716                 }
 717         }
 718 }
 719
 720 static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
 721 {
 722         struct ath_common *common = ath9k_hw_common(ah);
 723         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 724         u32 new_flags, to_set, to_clear;
 725
 726         if (AR_SREV_9462_20(ah) &&
 727             mci->update_2g5g &&
 728             (mci->bt_state != MCI_BT_SLEEP)) {
 729
 730                 if (mci->is_2g) {
 731                         new_flags = MCI_2G_FLAGS;
 732                         to_clear = MCI_2G_FLAGS_CLEAR_MASK;
 733                         to_set = MCI_2G_FLAGS_SET_MASK;
 734                 } else {
 735                         new_flags = MCI_5G_FLAGS;
 736                         to_clear = MCI_5G_FLAGS_CLEAR_MASK;
 737                         to_set = MCI_5G_FLAGS_SET_MASK;
 738                 }
 739
 740                 ath_dbg(common, MCI,
 741                         "MCI BT_MCI_FLAGS: %s 0x%08x clr=0x%08x, set=0x%08x\n",
 742                 mci->is_2g ? "2G" : "5G", new_flags, to_clear, to_set);
 743
 744                 if (to_clear)
 745                         ar9003_mci_send_coex_bt_flags(ah, wait_done,
 746                                         MCI_GPM_COEX_BT_FLAGS_CLEAR, to_clear);
 747
 748                 if (to_set)
 749                         ar9003_mci_send_coex_bt_flags(ah, wait_done,
 750                                         MCI_GPM_COEX_BT_FLAGS_SET, to_set);
 751         }
 752 }
 753
 754 static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
 755                                         u32 *payload, bool queue)
 756 {
 757         struct ath_common *common = ath9k_hw_common(ah);
 758         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 759         u8 type, opcode;
 760
 761         if (queue) {
 762
 763                 if (payload)
 764                         ath_dbg(common, MCI,
 765                                 "MCI ERROR: Send fail: %02x: %02x %02x %02x\n",
 766                                 header,
 767                                 *(((u8 *)payload) + 4),
 768                                 *(((u8 *)payload) + 5),
 769                                 *(((u8 *)payload) + 6));
 770                 else
 771                         ath_dbg(common, MCI, "MCI ERROR: Send fail: %02x\n",
 772                                 header);
 773         }
 774
 775         /* check if the message is to be queued */
 776         if (header != MCI_GPM)
 777                 return;
 778
 779         type = MCI_GPM_TYPE(payload);
 780         opcode = MCI_GPM_OPCODE(payload);
 781
 782         if (type != MCI_GPM_COEX_AGENT)
 783                 return;
 784
 785         switch (opcode) {
 786         case MCI_GPM_COEX_BT_UPDATE_FLAGS:
 787
 788                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==
 789                     MCI_GPM_COEX_BT_FLAGS_READ)
 790                         break;
 791
 792                 mci->update_2g5g = queue;
 793
 794                 if (queue)
 795                         ath_dbg(common, MCI,
 796                                 "MCI BT_MCI_FLAGS: 2G5G status <queued> %s\n",
 797                                 mci->is_2g ? "2G" : "5G");
 798                 else
 799                         ath_dbg(common, MCI,
 800                                 "MCI BT_MCI_FLAGS: 2G5G status <sent> %s\n",
 801                                 mci->is_2g ? "2G" : "5G");
 802
 803                 break;
 804
 805         case MCI_GPM_COEX_WLAN_CHANNELS:
 806
 807                 mci->wlan_channels_update = queue;
 808                 if (queue)
 809                         ath_dbg(common, MCI, "MCI WLAN channel map <queued>\n");
 810                 else
 811                         ath_dbg(common, MCI, "MCI WLAN channel map <sent>\n");
 812                 break;
 813
 814         case MCI_GPM_COEX_HALT_BT_GPM:
 815
 816                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
 817                                 MCI_GPM_COEX_BT_GPM_UNHALT) {
 818
 819                         mci->unhalt_bt_gpm = queue;
 820
 821                         if (queue)
 822                                 ath_dbg(common, MCI,
 823                                         "MCI UNHALT BT GPM <queued>\n");
 824                         else {
 825                                 mci->halted_bt_gpm = false;
 826                                 ath_dbg(common, MCI,
 827                                         "MCI UNHALT BT GPM <sent>\n");
 828                         }
 829                 }
 830
 831                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
 832                                 MCI_GPM_COEX_BT_GPM_HALT) {
 833
 834                         mci->halted_bt_gpm = !queue;
 835
 836                         if (queue)
 837                                 ath_dbg(common, MCI,
 838                                         "MCI HALT BT GPM <not sent>\n");
 839                         else
 840                                 ath_dbg(common, MCI,
 841                                         "MCI UNHALT BT GPM <sent>\n");
 842                 }
 843
 844                 break;
 845         default:
 846                 break;
 847         }
 848 }
 849
 850 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
 851 {
 852         struct ath_common *common = ath9k_hw_common(ah);
 853         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 854
 855         if (!ATH9K_HW_CAP_MCI)
 856                 return;
 857
 858         if (mci->update_2g5g) {
 859                 if (mci->is_2g) {
 860
 861                         ar9003_mci_send_2g5g_status(ah, true);
 862                         ath_dbg(common, MCI, "MCI Send LNA trans\n");
 863                         ar9003_mci_send_lna_transfer(ah, true);
 864                         udelay(5);
 865
 866                         REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
 867                                     AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 868
 869                         if (AR_SREV_9462_20(ah)) {
 870                                 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
 871                                             AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
 872                                 if (!(mci->config &
 873                                       ATH_MCI_CONFIG_DISABLE_OSLA)) {
 874                                         REG_SET_BIT(ah, AR_BTCOEX_CTRL,
 875                                         AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 876                                 }
 877                         }
 878                 } else {
 879                         ath_dbg(common, MCI, "MCI Send LNA take\n");
 880                         ar9003_mci_send_lna_take(ah, true);
 881                         udelay(5);
 882
 883                         REG_SET_BIT(ah, AR_MCI_TX_CTRL,
 884                                     AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 885
 886                         if (AR_SREV_9462_20(ah)) {
 887                                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
 888                                             AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
 889                                 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
 890                                         AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 891                         }
 892
 893                         ar9003_mci_send_2g5g_status(ah, true);
 894                 }
 895         }
 896 }
 897
 898 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
 899                              u32 *payload, u8 len, bool wait_done,
 900                              bool check_bt)
 901 {
 902         struct ath_common *common = ath9k_hw_common(ah);
 903         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 904         bool msg_sent = false;
 905         u32 regval;
 906         u32 saved_mci_int_en;
 907         int i;
 908
 909         if (!ATH9K_HW_CAP_MCI)
 910                 return false;
 911
 912         saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
 913         regval = REG_READ(ah, AR_BTCOEX_CTRL);
 914
 915         if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) {
 916
 917                 ath_dbg(common, MCI,
 918                         "MCI Not sending 0x%x. MCI is not enabled. full_sleep = %d\n",
 919                         header,
 920                         (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0);
 921
 922                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 923                 return false;
 924
 925         } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) {
 926
 927                 ath_dbg(common, MCI,
 928                         "MCI Don't send message 0x%x. BT is in sleep state\n",
 929                         header);
 930
 931                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 932                 return false;
 933         }
 934
 935         if (wait_done)
 936                 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 937
 938         /* Need to clear SW_MSG_DONE raw bit before wait */
 939
 940         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 941                   (AR_MCI_INTERRUPT_SW_MSG_DONE |
 942                    AR_MCI_INTERRUPT_MSG_FAIL_MASK));
 943
 944         if (payload) {
 945                 for (i = 0; (i * 4) < len; i++)
 946                         REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
 947                                   *(payload + i));
 948         }
 949
 950         REG_WRITE(ah, AR_MCI_COMMAND0,
 951                   (SM((flag & MCI_FLAG_DISABLE_TIMESTAMP),
 952                       AR_MCI_COMMAND0_DISABLE_TIMESTAMP) |
 953                    SM(len, AR_MCI_COMMAND0_LEN) |
 954                    SM(header, AR_MCI_COMMAND0_HEADER)));
 955
 956         if (wait_done &&
 957             !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
 958                                         AR_MCI_INTERRUPT_SW_MSG_DONE, 500)))
 959                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 960         else {
 961                 ar9003_mci_queue_unsent_gpm(ah, header, payload, false);
 962                 msg_sent = true;
 963         }
 964
 965         if (wait_done)
 966                 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
 967
 968         return msg_sent;
 969 }
 970 EXPORT_SYMBOL(ar9003_mci_send_message);
 971
 972 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
 973                       u16 len, u32 sched_addr)
 974 {
 975         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 976
 977         if (!ATH9K_HW_CAP_MCI)
 978                 return;
 979
 980         mci->gpm_addr = gpm_addr;
 981         mci->gpm_buf = gpm_buf;
 982         mci->gpm_len = len;
 983         mci->sched_addr = sched_addr;
 984
 985         ar9003_mci_reset(ah, true, true, true);
 986 }
 987 EXPORT_SYMBOL(ar9003_mci_setup);
 988
 989 void ar9003_mci_cleanup(struct ath_hw *ah)
 990 {
 991         if (!ATH9K_HW_CAP_MCI)
 992                 return;
 993
 994         /* Turn off MCI and Jupiter mode. */
 995         REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
 996         ar9003_mci_disable_interrupt(ah);
 997 }
 998 EXPORT_SYMBOL(ar9003_mci_cleanup);
 999
1000 static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type,
1001                                          u8 gpm_opcode, u32 *p_gpm)
1002 {
1003         struct ath_common *common = ath9k_hw_common(ah);
1004         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1005         u8 *p_data = (u8 *) p_gpm;
1006
1007         if (gpm_type != MCI_GPM_COEX_AGENT)
1008                 return;
1009
1010         switch (gpm_opcode) {
1011         case MCI_GPM_COEX_VERSION_QUERY:
1012                 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n");
1013                 ar9003_mci_send_coex_version_response(ah, true);
1014                 break;
1015         case MCI_GPM_COEX_VERSION_RESPONSE:
1016                 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n");
1017                 mci->bt_ver_major =
1018                         *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION);
1019                 mci->bt_ver_minor =
1020                         *(p_data + MCI_GPM_COEX_B_MINOR_VERSION);
1021                 mci->bt_version_known = true;
1022                 ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n",
1023                         mci->bt_ver_major, mci->bt_ver_minor);
1024                 break;
1025         case MCI_GPM_COEX_STATUS_QUERY:
1026                 ath_dbg(common, MCI,
1027                         "MCI Recv GPM COEX Status Query = 0x%02X\n",
1028                         *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP));
1029                 mci->wlan_channels_update = true;
1030                 ar9003_mci_send_coex_wlan_channels(ah, true);
1031                 break;
1032         case MCI_GPM_COEX_BT_PROFILE_INFO:
1033                 mci->query_bt = true;
1034                 ath_dbg(common, MCI, "MCI Recv GPM COEX BT_Profile_Info\n");
1035                 break;
1036         case MCI_GPM_COEX_BT_STATUS_UPDATE:
1037                 mci->query_bt = true;
1038                 ath_dbg(common, MCI,
1039                         "MCI Recv GPM COEX BT_Status_Update SEQ=%d (drop&query)\n",
1040                         *(p_gpm + 3));
1041                 break;
1042         default:
1043                 break;
1044         }
1045 }
1046
1047 u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
1048                             u8 gpm_opcode, int time_out)
1049 {
1050         struct ath_common *common = ath9k_hw_common(ah);
1051         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1052         u32 *p_gpm = NULL, mismatch = 0, more_data;
1053         u32 offset;
1054         u8 recv_type = 0, recv_opcode = 0;
1055         bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
1056
1057         if (!ATH9K_HW_CAP_MCI)
1058                 return 0;
1059
1060         more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
1061
1062         while (time_out > 0) {
1063                 if (p_gpm) {
1064                         MCI_GPM_RECYCLE(p_gpm);
1065                         p_gpm = NULL;
1066                 }
1067
1068                 if (more_data != MCI_GPM_MORE)
1069                         time_out = ar9003_mci_wait_for_interrupt(ah,
1070                                         AR_MCI_INTERRUPT_RX_MSG_RAW,
1071                                         AR_MCI_INTERRUPT_RX_MSG_GPM,
1072                                         time_out);
1073
1074                 if (!time_out)
1075                         break;
1076
1077                 offset = ar9003_mci_state(ah,
1078                                 MCI_STATE_NEXT_GPM_OFFSET, &more_data);
1079
1080                 if (offset == MCI_GPM_INVALID)
1081                         continue;
1082
1083                 p_gpm = (u32 *) (mci->gpm_buf + offset);
1084                 recv_type = MCI_GPM_TYPE(p_gpm);
1085                 recv_opcode = MCI_GPM_OPCODE(p_gpm);
1086
1087                 if (MCI_GPM_IS_CAL_TYPE(recv_type)) {
1088
1089                         if (recv_type == gpm_type) {
1090
1091                                 if ((gpm_type == MCI_GPM_BT_CAL_DONE) &&
1092                                     !b_is_bt_cal_done) {
1093                                         gpm_type = MCI_GPM_BT_CAL_GRANT;
1094                                         ath_dbg(common, MCI,
1095                                                 "MCI Recv BT_CAL_DONE wait BT_CAL_GRANT\n");
1096                                         continue;
1097                                 }
1098
1099                                 break;
1100                         }
1101                 } else if ((recv_type == gpm_type) &&
1102                            (recv_opcode == gpm_opcode))
1103                         break;
1104
1105                 /* not expected message */
1106
1107                 /*
1108                  * check if it's cal_grant
1109                  *
1110                  * When we're waiting for cal_grant in reset routine,
1111                  * it's possible that BT sends out cal_request at the
1112                  * same time. Since BT's calibration doesn't happen
1113                  * that often, we'll let BT completes calibration then
1114                  * we continue to wait for cal_grant from BT.
1115                  * Orginal: Wait BT_CAL_GRANT.
1116                  * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT->wait
1117                  * BT_CAL_DONE -> Wait BT_CAL_GRANT.
1118                  */
1119
1120                 if ((gpm_type == MCI_GPM_BT_CAL_GRANT) &&
1121                     (recv_type == MCI_GPM_BT_CAL_REQ)) {
1122
1123                         u32 payload[4] = {0, 0, 0, 0};
1124
1125                         gpm_type = MCI_GPM_BT_CAL_DONE;
1126                         ath_dbg(common, MCI,
1127                                 "MCI Rcv BT_CAL_REQ, send WLAN_CAL_GRANT\n");
1128
1129                         MCI_GPM_SET_CAL_TYPE(payload,
1130                                         MCI_GPM_WLAN_CAL_GRANT);
1131
1132                         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
1133                                                 false, false);
1134
1135                         ath_dbg(common, MCI, "MCI now wait for BT_CAL_DONE\n");
1136
1137                         continue;
1138                 } else {
1139                         ath_dbg(common, MCI, "MCI GPM subtype not match 0x%x\n",
1140                                 *(p_gpm + 1));
1141                         mismatch++;
1142                         ar9003_mci_process_gpm_extra(ah, recv_type,
1143                                         recv_opcode, p_gpm);
1144                 }
1145         }
1146         if (p_gpm) {
1147                 MCI_GPM_RECYCLE(p_gpm);
1148                 p_gpm = NULL;
1149         }
1150
1151         if (time_out <= 0) {
1152                 time_out = 0;
1153                 ath_dbg(common, MCI,
1154                         "MCI GPM received timeout, mismatch = %d\n", mismatch);
1155         } else
1156                 ath_dbg(common, MCI, "MCI Receive GPM type=0x%x, code=0x%x\n",
1157                         gpm_type, gpm_opcode);
1158
1159         while (more_data == MCI_GPM_MORE) {
1160
1161                 ath_dbg(common, MCI, "MCI discard remaining GPM\n");
1162                 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
1163                                           &more_data);
1164
1165                 if (offset == MCI_GPM_INVALID)
1166                         break;
1167
1168                 p_gpm = (u32 *) (mci->gpm_buf + offset);
1169                 recv_type = MCI_GPM_TYPE(p_gpm);
1170                 recv_opcode = MCI_GPM_OPCODE(p_gpm);
1171
1172                 if (!MCI_GPM_IS_CAL_TYPE(recv_type))
1173                         ar9003_mci_process_gpm_extra(ah, recv_type,
1174                                                      recv_opcode, p_gpm);
1175
1176                 MCI_GPM_RECYCLE(p_gpm);
1177         }
1178
1179         return time_out;
1180 }
1181
1182 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1183 {
1184         struct ath_common *common = ath9k_hw_common(ah);
1185         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1186         u32 value = 0, more_gpm = 0, gpm_ptr;
1187         u8 query_type;
1188
1189         if (!ATH9K_HW_CAP_MCI)
1190                 return 0;
1191
1192         switch (state_type) {
1193         case MCI_STATE_ENABLE:
1194                 if (mci->ready) {
1195
1196                         value = REG_READ(ah, AR_BTCOEX_CTRL);
1197
1198                         if ((value == 0xdeadbeef) || (value == 0xffffffff))
1199                                 value = 0;
1200                 }
1201                 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
1202                 break;
1203         case MCI_STATE_INIT_GPM_OFFSET:
1204                 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1205                 ath_dbg(common, MCI, "MCI GPM initial WRITE_PTR=%d\n", value);
1206                 mci->gpm_idx = value;
1207                 break;
1208         case MCI_STATE_NEXT_GPM_OFFSET:
1209         case MCI_STATE_LAST_GPM_OFFSET:
1210                 /*
1211                 * This could be useful to avoid new GPM message interrupt which
1212                 * may lead to spurious interrupt after power sleep, or multiple
1213                 * entry of ath_mci_intr().
1214                 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
1215                 * alleviate this effect, but clearing GPM RX interrupt bit is
1216                 * safe, because whether this is called from hw or driver code
1217                 * there must be an interrupt bit set/triggered initially
1218                 */
1219                 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1220                           AR_MCI_INTERRUPT_RX_MSG_GPM);
1221
1222                 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1223                 value = gpm_ptr;
1224
1225                 if (value == 0)
1226                         value = mci->gpm_len - 1;
1227                 else if (value >= mci->gpm_len) {
1228                         if (value != 0xFFFF) {
1229                                 value = 0;
1230                                 ath_dbg(common, MCI,
1231                                         "MCI GPM offset out of range\n");
1232                         }
1233                 } else
1234                         value--;
1235
1236                 if (value == 0xFFFF) {
1237                         value = MCI_GPM_INVALID;
1238                         more_gpm = MCI_GPM_NOMORE;
1239                         ath_dbg(common, MCI,
1240                                 "MCI GPM ptr invalid @ptr=%d, offset=%d, more=GPM_NOMORE\n",
1241                                 gpm_ptr, value);
1242                 } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) {
1243
1244                         if (gpm_ptr == mci->gpm_idx) {
1245                                 value = MCI_GPM_INVALID;
1246                                 more_gpm = MCI_GPM_NOMORE;
1247
1248                                 ath_dbg(common, MCI,
1249                                         "MCI GPM message not available @ptr=%d, @offset=%d, more=GPM_NOMORE\n",
1250                                         gpm_ptr, value);
1251                         } else {
1252                                 for (;;) {
1253
1254                                         u32 temp_index;
1255
1256                                         /* skip reserved GPM if any */
1257
1258                                         if (value != mci->gpm_idx)
1259                                                 more_gpm = MCI_GPM_MORE;
1260                                         else
1261                                                 more_gpm = MCI_GPM_NOMORE;
1262
1263                                         temp_index = mci->gpm_idx;
1264                                         mci->gpm_idx++;
1265
1266                                         if (mci->gpm_idx >=
1267                                             mci->gpm_len)
1268                                                 mci->gpm_idx = 0;
1269
1270                                         ath_dbg(common, MCI,
1271                                                 "MCI GPM message got ptr=%d, @offset=%d, more=%d\n",
1272                                                 gpm_ptr, temp_index,
1273                                                 (more_gpm == MCI_GPM_MORE));
1274
1275                                         if (ar9003_mci_is_gpm_valid(ah,
1276                                                                 temp_index)) {
1277                                                 value = temp_index;
1278                                                 break;
1279                                         }
1280
1281                                         if (more_gpm == MCI_GPM_NOMORE) {
1282                                                 value = MCI_GPM_INVALID;
1283                                                 break;
1284                                         }
1285                                 }
1286                         }
1287                         if (p_data)
1288                                 *p_data = more_gpm;
1289                         }
1290
1291                         if (value != MCI_GPM_INVALID)
1292                                 value <<= 4;
1293
1294                         break;
1295         case MCI_STATE_LAST_SCHD_MSG_OFFSET:
1296                 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1297                                     AR_MCI_RX_LAST_SCHD_MSG_INDEX);
1298                 /* Make it in bytes */
1299                 value <<= 4;
1300                 break;
1301
1302         case MCI_STATE_REMOTE_SLEEP:
1303                 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1304                            AR_MCI_RX_REMOTE_SLEEP) ?
1305                         MCI_BT_SLEEP : MCI_BT_AWAKE;
1306                 break;
1307
1308         case MCI_STATE_CONT_RSSI_POWER:
1309                 value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER);
1310                         break;
1311
1312         case MCI_STATE_CONT_PRIORITY:
1313                 value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY);
1314                 break;
1315
1316         case MCI_STATE_CONT_TXRX:
1317                 value = MS(mci->cont_status, AR_MCI_CONT_TXRX);
1318                 break;
1319
1320         case MCI_STATE_BT:
1321                 value = mci->bt_state;
1322                 break;
1323
1324         case MCI_STATE_SET_BT_SLEEP:
1325                 mci->bt_state = MCI_BT_SLEEP;
1326                 break;
1327
1328         case MCI_STATE_SET_BT_AWAKE:
1329                 mci->bt_state = MCI_BT_AWAKE;
1330                 ar9003_mci_send_coex_version_query(ah, true);
1331                 ar9003_mci_send_coex_wlan_channels(ah, true);
1332
1333                 if (mci->unhalt_bt_gpm) {
1334
1335                         ath_dbg(common, MCI, "MCI unhalt BT GPM\n");
1336                         ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
1337                 }
1338
1339                 ar9003_mci_2g5g_switch(ah, true);
1340                 break;
1341
1342         case MCI_STATE_SET_BT_CAL_START:
1343                 mci->bt_state = MCI_BT_CAL_START;
1344                 break;
1345
1346         case MCI_STATE_SET_BT_CAL:
1347                 mci->bt_state = MCI_BT_CAL;
1348                 break;
1349
1350         case MCI_STATE_RESET_REQ_WAKE:
1351                 ar9003_mci_reset_req_wakeup(ah);
1352                 mci->update_2g5g = true;
1353
1354                 if ((AR_SREV_9462_20_OR_LATER(ah)) &&
1355                     (mci->config & ATH_MCI_CONFIG_MCI_OBS_MASK)) {
1356                         /* Check if we still have control of the GPIOs */
1357                         if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1358                                       ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1359                                         ATH_MCI_CONFIG_MCI_OBS_GPIO) {
1360
1361                                 ath_dbg(common, MCI,
1362                                         "MCI reconfigure observation\n");
1363                                 ar9003_mci_observation_set_up(ah);
1364                         }
1365                 }
1366                 break;
1367
1368         case MCI_STATE_SEND_WLAN_COEX_VERSION:
1369                 ar9003_mci_send_coex_version_response(ah, true);
1370                 break;
1371
1372         case MCI_STATE_SET_BT_COEX_VERSION:
1373
1374                 if (!p_data)
1375                         ath_dbg(common, MCI,
1376                                 "MCI Set BT Coex version with NULL data!!\n");
1377                 else {
1378                         mci->bt_ver_major = (*p_data >> 8) & 0xff;
1379                         mci->bt_ver_minor = (*p_data) & 0xff;
1380                         mci->bt_version_known = true;
1381                         ath_dbg(common, MCI, "MCI BT version set: %d.%d\n",
1382                                 mci->bt_ver_major, mci->bt_ver_minor);
1383                 }
1384                 break;
1385
1386         case MCI_STATE_SEND_WLAN_CHANNELS:
1387                 if (p_data) {
1388                         if (((mci->wlan_channels[1] & 0xffff0000) ==
1389                              (*(p_data + 1) & 0xffff0000)) &&
1390                             (mci->wlan_channels[2] == *(p_data + 2)) &&
1391                             (mci->wlan_channels[3] == *(p_data + 3)))
1392                                 break;
1393
1394                         mci->wlan_channels[0] = *p_data++;
1395                         mci->wlan_channels[1] = *p_data++;
1396                         mci->wlan_channels[2] = *p_data++;
1397                         mci->wlan_channels[3] = *p_data++;
1398                 }
1399                 mci->wlan_channels_update = true;
1400                 ar9003_mci_send_coex_wlan_channels(ah, true);
1401                 break;
1402
1403         case MCI_STATE_SEND_VERSION_QUERY:
1404                 ar9003_mci_send_coex_version_query(ah, true);
1405                 break;
1406
1407         case MCI_STATE_SEND_STATUS_QUERY:
1408                 query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
1409
1410                 ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
1411                 break;
1412
1413         case MCI_STATE_NEED_FLUSH_BT_INFO:
1414                         /*
1415                          * btcoex_hw.mci.unhalt_bt_gpm means whether it's
1416                          * needed to send UNHALT message. It's set whenever
1417                          * there's a request to send HALT message.
1418                          * mci_halted_bt_gpm means whether HALT message is sent
1419                          * out successfully.
1420                          *
1421                          * Checking (mci_unhalt_bt_gpm == false) instead of
1422                          * checking (ah->mci_halted_bt_gpm == false) will make
1423                          * sure currently is in UNHALT-ed mode and BT can
1424                          * respond to status query.
1425                          */
1426                         value = (!mci->unhalt_bt_gpm &&
1427                                  mci->need_flush_btinfo) ? 1 : 0;
1428                         if (p_data)
1429                                 mci->need_flush_btinfo =
1430                                         (*p_data != 0) ? true : false;
1431                         break;
1432
1433         case MCI_STATE_RECOVER_RX:
1434
1435                 ath_dbg(common, MCI, "MCI hw RECOVER_RX\n");
1436                 ar9003_mci_prep_interface(ah);
1437                 mci->query_bt = true;
1438                 mci->need_flush_btinfo = true;
1439                 ar9003_mci_send_coex_wlan_channels(ah, true);
1440                 ar9003_mci_2g5g_switch(ah, true);
1441                 break;
1442
1443         case MCI_STATE_NEED_FTP_STOMP:
1444                 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
1445                 break;
1446
1447         case MCI_STATE_NEED_TUNING:
1448                 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING);
1449                 break;
1450
1451         default:
1452                 break;
1453
1454         }
1455
1456         return value;
1457 }
1458 EXPORT_SYMBOL(ar9003_mci_state);