drivers/net/wireless/ath/ath9k/ar9003_mci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_mci.h"
  21
  22 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
  23 {
  24         if (!AR_SREV_9462_20(ah))
  25                 return;
  26
  27         REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
  28                       AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1);
  29         udelay(1);
  30         REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
  31                       AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0);
  32 }
  33
  34 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
  35                                         u32 bit_position, int time_out)
  36 {
  37         struct ath_common *common = ath9k_hw_common(ah);
  38
  39         while (time_out) {
  40
  41                 if (REG_READ(ah, address) & bit_position) {
  42
  43                         REG_WRITE(ah, address, bit_position);
  44
  45                         if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
  46
  47                                 if (bit_position &
  48                                     AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
  49                                         ar9003_mci_reset_req_wakeup(ah);
  50
  51                                 if (bit_position &
  52                                     (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
  53                                      AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
  54                                         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
  55                                         AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
  56
  57                                 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
  58                                           AR_MCI_INTERRUPT_RX_MSG);
  59                         }
  60                         break;
  61                 }
  62
  63                 udelay(10);
  64                 time_out -= 10;
  65
  66                 if (time_out < 0)
  67                         break;
  68         }
  69
  70         if (time_out <= 0) {
  71                 ath_dbg(common, MCI,
  72                         "MCI Wait for Reg 0x%08x = 0x%08x timeout\n",
  73                         address, bit_position);
  74                 ath_dbg(common, MCI,
  75                         "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x\n",
  76                         REG_READ(ah, AR_MCI_INTERRUPT_RAW),
  77                         REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
  78                 time_out = 0;
  79         }
  80
  81         return time_out;
  82 }
  83
  84 void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
  85 {
  86         u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
  87
  88         ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
  89                                 wait_done, false);
  90         udelay(5);
  91 }
  92
  93 void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
  94 {
  95         u32 payload = 0x00000000;
  96
  97         ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
  98                                 wait_done, false);
  99 }
 100
 101 static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
 102 {
 103         ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP,
 104                                 NULL, 0, wait_done, false);
 105         udelay(5);
 106 }
 107
 108 void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
 109 {
 110         ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
 111                                 NULL, 0, wait_done, false);
 112 }
 113
 114 static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done)
 115 {
 116         u32 payload = 0x70000000;
 117
 118         ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1,
 119                                 wait_done, false);
 120 }
 121
 122 static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done)
 123 {
 124         ar9003_mci_send_message(ah, MCI_SYS_SLEEPING,
 125                                 MCI_FLAG_DISABLE_TIMESTAMP,
 126                                 NULL, 0, wait_done, false);
 127 }
 128
 129 static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
 130                                                bool wait_done)
 131 {
 132         struct ath_common *common = ath9k_hw_common(ah);
 133         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 134         u32 payload[4] = {0, 0, 0, 0};
 135
 136         if (!mci->bt_version_known &&
 137                         (mci->bt_state != MCI_BT_SLEEP)) {
 138                 ath_dbg(common, MCI, "MCI Send Coex version query\n");
 139                 MCI_GPM_SET_TYPE_OPCODE(payload,
 140                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY);
 141                 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 142                                 wait_done, true);
 143         }
 144 }
 145
 146 static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
 147                                                      bool wait_done)
 148 {
 149         struct ath_common *common = ath9k_hw_common(ah);
 150         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 151         u32 payload[4] = {0, 0, 0, 0};
 152
 153         ath_dbg(common, MCI, "MCI Send Coex version response\n");
 154         MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
 155                         MCI_GPM_COEX_VERSION_RESPONSE);
 156         *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) =
 157                 mci->wlan_ver_major;
 158         *(((u8 *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) =
 159                 mci->wlan_ver_minor;
 160         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
 161 }
 162
 163 static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
 164                                                   bool wait_done)
 165 {
 166         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 167         u32 *payload = &mci->wlan_channels[0];
 168
 169         if ((mci->wlan_channels_update == true) &&
 170                         (mci->bt_state != MCI_BT_SLEEP)) {
 171                 MCI_GPM_SET_TYPE_OPCODE(payload,
 172                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_WLAN_CHANNELS);
 173                 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 174                                         wait_done, true);
 175                 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff);
 176         }
 177 }
 178
 179 static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
 180                                                 bool wait_done, u8 query_type)
 181 {
 182         struct ath_common *common = ath9k_hw_common(ah);
 183         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 184         u32 payload[4] = {0, 0, 0, 0};
 185         bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO |
 186                                              MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
 187
 188         if (mci->bt_state != MCI_BT_SLEEP) {
 189
 190                 ath_dbg(common, MCI, "MCI Send Coex BT Status Query 0x%02X\n",
 191                         query_type);
 192
 193                 MCI_GPM_SET_TYPE_OPCODE(payload,
 194                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY);
 195
 196                 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type;
 197                 /*
 198                  * If bt_status_query message is  not sent successfully,
 199                  * then need_flush_btinfo should be set again.
 200                  */
 201                 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
 202                                              wait_done, true)) {
 203                         if (query_btinfo) {
 204                                 mci->need_flush_btinfo = true;
 205
 206                                 ath_dbg(common, MCI,
 207                                         "MCI send bt_status_query fail, set flush flag again\n");
 208                         }
 209                 }
 210
 211                 if (query_btinfo)
 212                         mci->query_bt = false;
 213         }
 214 }
 215
 216 void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
 217                                       bool wait_done)
 218 {
 219         struct ath_common *common = ath9k_hw_common(ah);
 220         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 221         u32 payload[4] = {0, 0, 0, 0};
 222
 223         ath_dbg(common, MCI, "MCI Send Coex %s BT GPM\n",
 224                 (halt) ? "halt" : "unhalt");
 225
 226         MCI_GPM_SET_TYPE_OPCODE(payload,
 227                                 MCI_GPM_COEX_AGENT, MCI_GPM_COEX_HALT_BT_GPM);
 228
 229         if (halt) {
 230                 mci->query_bt = true;
 231                 /* Send next unhalt no matter halt sent or not */
 232                 mci->unhalt_bt_gpm = true;
 233                 mci->need_flush_btinfo = true;
 234                 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
 235                         MCI_GPM_COEX_BT_GPM_HALT;
 236         } else
 237                 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
 238                         MCI_GPM_COEX_BT_GPM_UNHALT;
 239
 240         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
 241 }
 242
 243
 244 static void ar9003_mci_prep_interface(struct ath_hw *ah)
 245 {
 246         struct ath_common *common = ath9k_hw_common(ah);
 247         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 248         u32 saved_mci_int_en;
 249         u32 mci_timeout = 150;
 250
 251         mci->bt_state = MCI_BT_SLEEP;
 252         saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
 253
 254         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 255         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 256                   REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
 257         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 258                   REG_READ(ah, AR_MCI_INTERRUPT_RAW));
 259
 260         /* Remote Reset */
 261         ath_dbg(common, MCI, "MCI Reset sequence start\n");
 262         ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");
 263         ar9003_mci_remote_reset(ah, true);
 264
 265         /*
 266          * This delay is required for the reset delay worst case value 255 in
 267          * MCI_COMMAND2 register
 268          */
 269
 270         if (AR_SREV_9462_10(ah))
 271                 udelay(252);
 272
 273         ath_dbg(common, MCI, "MCI Send REQ_WAKE to remoter(BT)\n");
 274         ar9003_mci_send_req_wake(ah, true);
 275
 276         if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 277                                 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) {
 278
 279                 ath_dbg(common, MCI, "MCI SYS_WAKING from remote(BT)\n");
 280                 mci->bt_state = MCI_BT_AWAKE;
 281
 282                 if (AR_SREV_9462_10(ah))
 283                         udelay(10);
 284                 /*
 285                  * we don't need to send more remote_reset at this moment.
 286                  * If BT receive first remote_reset, then BT HW will
 287                  * be cleaned up and will be able to receive req_wake
 288                  * and BT HW will respond sys_waking.
 289                  * In this case, WLAN will receive BT's HW sys_waking.
 290                  * Otherwise, if BT SW missed initial remote_reset,
 291                  * that remote_reset will still clean up BT MCI RX,
 292                  * and the req_wake will wake BT up,
 293                  * and BT SW will respond this req_wake with a remote_reset and
 294                  * sys_waking. In this case, WLAN will receive BT's SW
 295                  * sys_waking. In either case, BT's RX is cleaned up. So we
 296                  * don't need to reply BT's remote_reset now, if any.
 297                  * Similarly, if in any case, WLAN can receive BT's sys_waking,
 298                  * that means WLAN's RX is also fine.
 299                  */
 300
 301                 /* Send SYS_WAKING to BT */
 302
 303                 ath_dbg(common, MCI, "MCI send SW SYS_WAKING to remote BT\n");
 304
 305                 ar9003_mci_send_sys_waking(ah, true);
 306                 udelay(10);
 307
 308                 /*
 309                  * Set BT priority interrupt value to be 0xff to
 310                  * avoid having too many BT PRIORITY interrupts.
 311                  */
 312
 313                 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
 314                 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
 315                 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
 316                 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
 317                 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
 318
 319                 /*
 320                  * A contention reset will be received after send out
 321                  * sys_waking. Also BT priority interrupt bits will be set.
 322                  * Clear those bits before the next step.
 323                  */
 324
 325                 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 326                           AR_MCI_INTERRUPT_RX_MSG_CONT_RST);
 327                 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 328                           AR_MCI_INTERRUPT_BT_PRI);
 329
 330                 if (AR_SREV_9462_10(ah) || mci->is_2g) {
 331                         /* Send LNA_TRANS */
 332                         ath_dbg(common, MCI, "MCI send LNA_TRANS to BT\n");
 333                         ar9003_mci_send_lna_transfer(ah, true);
 334                         udelay(5);
 335                 }
 336
 337                 if (AR_SREV_9462_10(ah) || (mci->is_2g &&
 338                                             !mci->update_2g5g)) {
 339                         if (ar9003_mci_wait_for_interrupt(ah,
 340                                 AR_MCI_INTERRUPT_RX_MSG_RAW,
 341                                 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
 342                                 mci_timeout))
 343                                 ath_dbg(common, MCI,
 344                                         "MCI WLAN has control over the LNA & BT obeys it\n");
 345                         else
 346                                 ath_dbg(common, MCI,
 347                                         "MCI BT didn't respond to LNA_TRANS\n");
 348                 }
 349
 350                 if (AR_SREV_9462_10(ah)) {
 351                         /* Send another remote_reset to deassert BT clk_req. */
 352                         ath_dbg(common, MCI,
 353                                 "MCI another remote_reset to deassert clk_req\n");
 354                         ar9003_mci_remote_reset(ah, true);
 355                         udelay(252);
 356                 }
 357         }
 358
 359         /* Clear the extra redundant SYS_WAKING from BT */
 360         if ((mci->bt_state == MCI_BT_AWAKE) &&
 361                 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 362                                 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) &&
 363                 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 364                                 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) {
 365
 366                         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
 367                                   AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING);
 368                         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 369                                   AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
 370         }
 371
 372         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
 373 }
 374
 375 void ar9003_mci_disable_interrupt(struct ath_hw *ah)
 376 {
 377         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 378         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
 379 }
 380
 381 void ar9003_mci_enable_interrupt(struct ath_hw *ah)
 382 {
 383
 384         REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
 385         REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
 386                   AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
 387 }
 388
 389 bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
 390 {
 391         u32 intr;
 392
 393         intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
 394         return ((intr & ints) == ints);
 395 }
 396
 397 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
 398                               u32 *rx_msg_intr)
 399 {
 400         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 401         *raw_intr = mci->raw_intr;
 402         *rx_msg_intr = mci->rx_msg_intr;
 403
 404         /* Clean int bits after the values are read. */
 405         mci->raw_intr = 0;
 406         mci->rx_msg_intr = 0;
 407 }
 408 EXPORT_SYMBOL(ar9003_mci_get_interrupt);
 409
 410 void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
 411 {
 412         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 413
 414         if (!mci->update_2g5g &&
 415             (mci->is_2g != is_2g))
 416                 mci->update_2g5g = true;
 417
 418         mci->is_2g = is_2g;
 419 }
 420
 421 static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index)
 422 {
 423         struct ath_common *common = ath9k_hw_common(ah);
 424         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 425         u32 *payload;
 426         u32 recv_type, offset;
 427
 428         if (msg_index == MCI_GPM_INVALID)
 429                 return false;
 430
 431         offset = msg_index << 4;
 432
 433         payload = (u32 *)(mci->gpm_buf + offset);
 434         recv_type = MCI_GPM_TYPE(payload);
 435
 436         if (recv_type == MCI_GPM_RSVD_PATTERN) {
 437                 ath_dbg(common, MCI, "MCI Skip RSVD GPM\n");
 438                 return false;
 439         }
 440
 441         return true;
 442 }
 443
 444 static void ar9003_mci_observation_set_up(struct ath_hw *ah)
 445 {
 446         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 447         if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) {
 448
 449                 ath9k_hw_cfg_output(ah, 3,
 450                                         AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
 451                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
 452                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
 453                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
 454
 455         } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) {
 456
 457                 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
 458                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
 459                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
 460                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
 461                 ath9k_hw_cfg_output(ah, 5, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 462
 463         } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) {
 464
 465                 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
 466                 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
 467                 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
 468                 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
 469
 470         } else
 471                 return;
 472
 473         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 474
 475         if (AR_SREV_9462_20_OR_LATER(ah)) {
 476                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
 477                               AR_GLB_DS_JTAG_DISABLE, 1);
 478                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
 479                               AR_GLB_WLAN_UART_INTF_EN, 0);
 480                 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL,
 481                             ATH_MCI_CONFIG_MCI_OBS_GPIO);
 482         }
 483
 484         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
 485         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
 486         REG_WRITE(ah, AR_OBS, 0x4b);
 487         REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
 488         REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
 489         REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
 490         REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
 491         REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS,
 492                       AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07);
 493 }
 494
 495 static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done,
 496                                                 u8 opcode, u32 bt_flags)
 497 {
 498         struct ath_common *common = ath9k_hw_common(ah);
 499         u32 pld[4] = {0, 0, 0, 0};
 500
 501         MCI_GPM_SET_TYPE_OPCODE(pld,
 502                         MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
 503
 504         *(((u8 *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP)  = opcode;
 505         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
 506         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = (bt_flags >> 8) & 0xFF;
 507         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF;
 508         *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF;
 509
 510         ath_dbg(common, MCI,
 511                 "MCI BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n",
 512                 opcode == MCI_GPM_COEX_BT_FLAGS_READ ? "READ" :
 513                 opcode == MCI_GPM_COEX_BT_FLAGS_SET ? "SET" : "CLEAR",
 514                 bt_flags);
 515
 516         return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16,
 517                                                         wait_done, true);
 518 }
 519
 520 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
 521                       bool is_full_sleep)
 522 {
 523         struct ath_common *common = ath9k_hw_common(ah);
 524         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 525         u32 regval, thresh;
 526
 527         ath_dbg(common, MCI, "MCI full_sleep = %d, is_2g = %d\n",
 528                 is_full_sleep, is_2g);
 529
 530         /*
 531          * GPM buffer and scheduling message buffer are not allocated
 532          */
 533
 534         if (!mci->gpm_addr && !mci->sched_addr) {
 535                 ath_dbg(common, MCI,
 536                         "MCI GPM and schedule buffers are not allocated\n");
 537                 return;
 538         }
 539
 540         if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
 541                 ath_dbg(common, MCI, "MCI it's deadbeef, quit mci_reset\n");
 542                 return;
 543         }
 544
 545         /* Program MCI DMA related registers */
 546         REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
 547         REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
 548         REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
 549
 550         /*
 551         * To avoid MCI state machine be affected by incoming remote MCI msgs,
 552         * MCI mode will be enabled later, right before reset the MCI TX and RX.
 553         */
 554
 555         regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
 556                  SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
 557                  SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
 558                  SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
 559                  SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
 560                  SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
 561                  SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
 562                  SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
 563                  SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 564
 565         if (is_2g && (AR_SREV_9462_20(ah)) &&
 566                 !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) {
 567
 568                 regval |= SM(1, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 569                 ath_dbg(common, MCI, "MCI sched one step look ahead\n");
 570
 571                 if (!(mci->config &
 572                       ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
 573
 574                         thresh = MS(mci->config,
 575                                     ATH_MCI_CONFIG_AGGR_THRESH);
 576                         thresh &= 7;
 577                         regval |= SM(1,
 578                                      AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN);
 579                         regval |= SM(thresh, AR_BTCOEX_CTRL_AGGR_THRESH);
 580
 581                         REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
 582                                       AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
 583                         REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
 584                                       AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
 585
 586                 } else
 587                         ath_dbg(common, MCI, "MCI sched aggr thresh: off\n");
 588         } else
 589                 ath_dbg(common, MCI, "MCI SCHED one step look ahead off\n");
 590
 591         if (AR_SREV_9462_10(ah))
 592                 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
 593
 594         REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
 595
 596         if (AR_SREV_9462_20(ah)) {
 597                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
 598                             AR_BTCOEX_CTRL_SPDT_ENABLE);
 599                 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
 600                               AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
 601         }
 602
 603         REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1);
 604         REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
 605
 606         thresh = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);
 607         REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, thresh);
 608         REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
 609
 610         /* Resetting the Rx and Tx paths of MCI */
 611         regval = REG_READ(ah, AR_MCI_COMMAND2);
 612         regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
 613         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 614
 615         udelay(1);
 616
 617         regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX);
 618         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 619
 620         if (is_full_sleep) {
 621                 ar9003_mci_mute_bt(ah);
 622                 udelay(100);
 623         }
 624
 625         regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
 626         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 627         udelay(1);
 628         regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
 629         REG_WRITE(ah, AR_MCI_COMMAND2, regval);
 630
 631         ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
 632         REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
 633                   (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
 634                    SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM)));
 635
 636         REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
 637                         AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 638
 639         if (AR_SREV_9462_20_OR_LATER(ah))
 640                 ar9003_mci_observation_set_up(ah);
 641
 642         mci->ready = true;
 643         ar9003_mci_prep_interface(ah);
 644
 645         if (en_int)
 646                 ar9003_mci_enable_interrupt(ah);
 647 }
 648
 649 void ar9003_mci_mute_bt(struct ath_hw *ah)
 650 {
 651         struct ath_common *common = ath9k_hw_common(ah);
 652
 653         /* disable all MCI messages */
 654         REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
 655         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
 656         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
 657         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
 658         REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
 659         REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 660
 661         /* wait pending HW messages to flush out */
 662         udelay(10);
 663
 664         /*
 665          * Send LNA_TAKE and SYS_SLEEPING when
 666          * 1. reset not after resuming from full sleep
 667          * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment
 668          */
 669
 670         ath_dbg(common, MCI, "MCI Send LNA take\n");
 671         ar9003_mci_send_lna_take(ah, true);
 672
 673         udelay(5);
 674
 675         ath_dbg(common, MCI, "MCI Send sys sleeping\n");
 676         ar9003_mci_send_sys_sleeping(ah, true);
 677 }
 678
 679 void ar9003_mci_sync_bt_state(struct ath_hw *ah)
 680 {
 681         struct ath_common *common = ath9k_hw_common(ah);
 682         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 683         u32 cur_bt_state;
 684
 685         cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
 686
 687         if (mci->bt_state != cur_bt_state) {
 688                 ath_dbg(common, MCI,
 689                         "MCI BT state mismatches. old: %d, new: %d\n",
 690                         mci->bt_state, cur_bt_state);
 691                 mci->bt_state = cur_bt_state;
 692         }
 693
 694         if (mci->bt_state != MCI_BT_SLEEP) {
 695
 696                 ar9003_mci_send_coex_version_query(ah, true);
 697                 ar9003_mci_send_coex_wlan_channels(ah, true);
 698
 699                 if (mci->unhalt_bt_gpm == true) {
 700                         ath_dbg(common, MCI, "MCI unhalt BT GPM\n");
 701                         ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
 702                 }
 703         }
 704 }
 705
 706 static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
 707 {
 708         struct ath_common *common = ath9k_hw_common(ah);
 709         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 710         u32 new_flags, to_set, to_clear;
 711
 712         if (AR_SREV_9462_20(ah) &&
 713             mci->update_2g5g &&
 714             (mci->bt_state != MCI_BT_SLEEP)) {
 715
 716                 if (mci->is_2g) {
 717                         new_flags = MCI_2G_FLAGS;
 718                         to_clear = MCI_2G_FLAGS_CLEAR_MASK;
 719                         to_set = MCI_2G_FLAGS_SET_MASK;
 720                 } else {
 721                         new_flags = MCI_5G_FLAGS;
 722                         to_clear = MCI_5G_FLAGS_CLEAR_MASK;
 723                         to_set = MCI_5G_FLAGS_SET_MASK;
 724                 }
 725
 726                 ath_dbg(common, MCI,
 727                         "MCI BT_MCI_FLAGS: %s 0x%08x clr=0x%08x, set=0x%08x\n",
 728                 mci->is_2g ? "2G" : "5G", new_flags, to_clear, to_set);
 729
 730                 if (to_clear)
 731                         ar9003_mci_send_coex_bt_flags(ah, wait_done,
 732                                         MCI_GPM_COEX_BT_FLAGS_CLEAR, to_clear);
 733
 734                 if (to_set)
 735                         ar9003_mci_send_coex_bt_flags(ah, wait_done,
 736                                         MCI_GPM_COEX_BT_FLAGS_SET, to_set);
 737         }
 738
 739         if (AR_SREV_9462_10(ah) && (mci->bt_state != MCI_BT_SLEEP))
 740                 mci->update_2g5g = false;
 741 }
 742
 743 static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
 744                                         u32 *payload, bool queue)
 745 {
 746         struct ath_common *common = ath9k_hw_common(ah);
 747         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 748         u8 type, opcode;
 749
 750         if (queue) {
 751
 752                 if (payload)
 753                         ath_dbg(common, MCI,
 754                                 "MCI ERROR: Send fail: %02x: %02x %02x %02x\n",
 755                                 header,
 756                                 *(((u8 *)payload) + 4),
 757                                 *(((u8 *)payload) + 5),
 758                                 *(((u8 *)payload) + 6));
 759                 else
 760                         ath_dbg(common, MCI, "MCI ERROR: Send fail: %02x\n",
 761                                 header);
 762         }
 763
 764         /* check if the message is to be queued */
 765         if (header != MCI_GPM)
 766                 return;
 767
 768         type = MCI_GPM_TYPE(payload);
 769         opcode = MCI_GPM_OPCODE(payload);
 770
 771         if (type != MCI_GPM_COEX_AGENT)
 772                 return;
 773
 774         switch (opcode) {
 775         case MCI_GPM_COEX_BT_UPDATE_FLAGS:
 776
 777                 if (AR_SREV_9462_10(ah))
 778                         break;
 779
 780                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==
 781                                 MCI_GPM_COEX_BT_FLAGS_READ)
 782                         break;
 783
 784                 mci->update_2g5g = queue;
 785
 786                 if (queue)
 787                         ath_dbg(common, MCI,
 788                                 "MCI BT_MCI_FLAGS: 2G5G status <queued> %s\n",
 789                                 mci->is_2g ? "2G" : "5G");
 790                 else
 791                         ath_dbg(common, MCI,
 792                                 "MCI BT_MCI_FLAGS: 2G5G status <sent> %s\n",
 793                                 mci->is_2g ? "2G" : "5G");
 794
 795                 break;
 796
 797         case MCI_GPM_COEX_WLAN_CHANNELS:
 798
 799                 mci->wlan_channels_update = queue;
 800                 if (queue)
 801                         ath_dbg(common, MCI, "MCI WLAN channel map <queued>\n");
 802                 else
 803                         ath_dbg(common, MCI, "MCI WLAN channel map <sent>\n");
 804                 break;
 805
 806         case MCI_GPM_COEX_HALT_BT_GPM:
 807
 808                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
 809                                 MCI_GPM_COEX_BT_GPM_UNHALT) {
 810
 811                         mci->unhalt_bt_gpm = queue;
 812
 813                         if (queue)
 814                                 ath_dbg(common, MCI,
 815                                         "MCI UNHALT BT GPM <queued>\n");
 816                         else {
 817                                 mci->halted_bt_gpm = false;
 818                                 ath_dbg(common, MCI,
 819                                         "MCI UNHALT BT GPM <sent>\n");
 820                         }
 821                 }
 822
 823                 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
 824                                 MCI_GPM_COEX_BT_GPM_HALT) {
 825
 826                         mci->halted_bt_gpm = !queue;
 827
 828                         if (queue)
 829                                 ath_dbg(common, MCI,
 830                                         "MCI HALT BT GPM <not sent>\n");
 831                         else
 832                                 ath_dbg(common, MCI,
 833                                         "MCI UNHALT BT GPM <sent>\n");
 834                 }
 835
 836                 break;
 837         default:
 838                 break;
 839         }
 840 }
 841
 842 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
 843 {
 844         struct ath_common *common = ath9k_hw_common(ah);
 845         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 846
 847         if (mci->update_2g5g) {
 848                 if (mci->is_2g) {
 849
 850                         ar9003_mci_send_2g5g_status(ah, true);
 851                         ath_dbg(common, MCI, "MCI Send LNA trans\n");
 852                         ar9003_mci_send_lna_transfer(ah, true);
 853                         udelay(5);
 854
 855                         REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
 856                                     AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 857
 858                         if (AR_SREV_9462_20(ah)) {
 859                                 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
 860                                             AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
 861                                 if (!(mci->config &
 862                                       ATH_MCI_CONFIG_DISABLE_OSLA)) {
 863                                         REG_SET_BIT(ah, AR_BTCOEX_CTRL,
 864                                         AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 865                                 }
 866                         }
 867                 } else {
 868                         ath_dbg(common, MCI, "MCI Send LNA take\n");
 869                         ar9003_mci_send_lna_take(ah, true);
 870                         udelay(5);
 871
 872                         REG_SET_BIT(ah, AR_MCI_TX_CTRL,
 873                                     AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
 874
 875                         if (AR_SREV_9462_20(ah)) {
 876                                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
 877                                             AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
 878                                 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
 879                                         AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
 880                         }
 881
 882                         ar9003_mci_send_2g5g_status(ah, true);
 883                 }
 884         }
 885 }
 886
 887 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
 888                              u32 *payload, u8 len, bool wait_done,
 889                              bool check_bt)
 890 {
 891         struct ath_common *common = ath9k_hw_common(ah);
 892         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 893         bool msg_sent = false;
 894         u32 regval;
 895         u32 saved_mci_int_en;
 896         int i;
 897
 898         saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
 899         regval = REG_READ(ah, AR_BTCOEX_CTRL);
 900
 901         if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) {
 902
 903                 ath_dbg(common, MCI,
 904                         "MCI Not sending 0x%x. MCI is not enabled. full_sleep = %d\n",
 905                         header,
 906                         (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0);
 907
 908                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 909                 return false;
 910
 911         } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) {
 912
 913                 ath_dbg(common, MCI,
 914                         "MCI Don't send message 0x%x. BT is in sleep state\n",
 915                         header);
 916
 917                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 918                 return false;
 919         }
 920
 921         if (wait_done)
 922                 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
 923
 924         /* Need to clear SW_MSG_DONE raw bit before wait */
 925
 926         REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
 927                   (AR_MCI_INTERRUPT_SW_MSG_DONE |
 928                    AR_MCI_INTERRUPT_MSG_FAIL_MASK));
 929
 930         if (payload) {
 931                 for (i = 0; (i * 4) < len; i++)
 932                         REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
 933                                   *(payload + i));
 934         }
 935
 936         REG_WRITE(ah, AR_MCI_COMMAND0,
 937                   (SM((flag & MCI_FLAG_DISABLE_TIMESTAMP),
 938                       AR_MCI_COMMAND0_DISABLE_TIMESTAMP) |
 939                    SM(len, AR_MCI_COMMAND0_LEN) |
 940                    SM(header, AR_MCI_COMMAND0_HEADER)));
 941
 942         if (wait_done &&
 943             !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
 944                                         AR_MCI_INTERRUPT_SW_MSG_DONE, 500)))
 945                 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
 946         else {
 947                 ar9003_mci_queue_unsent_gpm(ah, header, payload, false);
 948                 msg_sent = true;
 949         }
 950
 951         if (wait_done)
 952                 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
 953
 954         return msg_sent;
 955 }
 956 EXPORT_SYMBOL(ar9003_mci_send_message);
 957
 958 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
 959                       u16 len, u32 sched_addr)
 960 {
 961         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 962         void *sched_buf = (void *)((char *) gpm_buf + (sched_addr - gpm_addr));
 963
 964         mci->gpm_addr = gpm_addr;
 965         mci->gpm_buf = gpm_buf;
 966         mci->gpm_len = len;
 967         mci->sched_addr = sched_addr;
 968         mci->sched_buf = sched_buf;
 969
 970         ar9003_mci_reset(ah, true, true, true);
 971 }
 972 EXPORT_SYMBOL(ar9003_mci_setup);
 973
 974 void ar9003_mci_cleanup(struct ath_hw *ah)
 975 {
 976         struct ath_common *common = ath9k_hw_common(ah);
 977
 978         /* Turn off MCI and Jupiter mode. */
 979         REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
 980         ath_dbg(common, MCI, "MCI ar9003_mci_cleanup\n");
 981         ar9003_mci_disable_interrupt(ah);
 982 }
 983 EXPORT_SYMBOL(ar9003_mci_cleanup);
 984
 985 static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type,
 986                                          u8 gpm_opcode, u32 *p_gpm)
 987 {
 988         struct ath_common *common = ath9k_hw_common(ah);
 989         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
 990         u8 *p_data = (u8 *) p_gpm;
 991
 992         if (gpm_type != MCI_GPM_COEX_AGENT)
 993                 return;
 994
 995         switch (gpm_opcode) {
 996         case MCI_GPM_COEX_VERSION_QUERY:
 997                 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n");
 998                 ar9003_mci_send_coex_version_response(ah, true);
 999                 break;
1000         case MCI_GPM_COEX_VERSION_RESPONSE:
1001                 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n");
1002                 mci->bt_ver_major =
1003                         *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION);
1004                 mci->bt_ver_minor =
1005                         *(p_data + MCI_GPM_COEX_B_MINOR_VERSION);
1006                 mci->bt_version_known = true;
1007                 ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n",
1008                         mci->bt_ver_major, mci->bt_ver_minor);
1009                 break;
1010         case MCI_GPM_COEX_STATUS_QUERY:
1011                 ath_dbg(common, MCI,
1012                         "MCI Recv GPM COEX Status Query = 0x%02X\n",
1013                         *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP));
1014                 mci->wlan_channels_update = true;
1015                 ar9003_mci_send_coex_wlan_channels(ah, true);
1016                 break;
1017         case MCI_GPM_COEX_BT_PROFILE_INFO:
1018                 mci->query_bt = true;
1019                 ath_dbg(common, MCI, "MCI Recv GPM COEX BT_Profile_Info\n");
1020                 break;
1021         case MCI_GPM_COEX_BT_STATUS_UPDATE:
1022                 mci->query_bt = true;
1023                 ath_dbg(common, MCI,
1024                         "MCI Recv GPM COEX BT_Status_Update SEQ=%d (drop&query)\n",
1025                         *(p_gpm + 3));
1026                 break;
1027         default:
1028                 break;
1029         }
1030 }
1031
1032 u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
1033                             u8 gpm_opcode, int time_out)
1034 {
1035         struct ath_common *common = ath9k_hw_common(ah);
1036         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1037         u32 *p_gpm = NULL, mismatch = 0, more_data;
1038         u32 offset;
1039         u8 recv_type = 0, recv_opcode = 0;
1040         bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
1041
1042         more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
1043
1044         while (time_out > 0) {
1045                 if (p_gpm) {
1046                         MCI_GPM_RECYCLE(p_gpm);
1047                         p_gpm = NULL;
1048                 }
1049
1050                 if (more_data != MCI_GPM_MORE)
1051                         time_out = ar9003_mci_wait_for_interrupt(ah,
1052                                         AR_MCI_INTERRUPT_RX_MSG_RAW,
1053                                         AR_MCI_INTERRUPT_RX_MSG_GPM,
1054                                         time_out);
1055
1056                 if (!time_out)
1057                         break;
1058
1059                 offset = ar9003_mci_state(ah,
1060                                 MCI_STATE_NEXT_GPM_OFFSET, &more_data);
1061
1062                 if (offset == MCI_GPM_INVALID)
1063                         continue;
1064
1065                 p_gpm = (u32 *) (mci->gpm_buf + offset);
1066                 recv_type = MCI_GPM_TYPE(p_gpm);
1067                 recv_opcode = MCI_GPM_OPCODE(p_gpm);
1068
1069                 if (MCI_GPM_IS_CAL_TYPE(recv_type)) {
1070
1071                         if (recv_type == gpm_type) {
1072
1073                                 if ((gpm_type == MCI_GPM_BT_CAL_DONE) &&
1074                                     !b_is_bt_cal_done) {
1075                                         gpm_type = MCI_GPM_BT_CAL_GRANT;
1076                                         ath_dbg(common, MCI,
1077                                                 "MCI Recv BT_CAL_DONE wait BT_CAL_GRANT\n");
1078                                         continue;
1079                                 }
1080
1081                                 break;
1082                         }
1083                 } else if ((recv_type == gpm_type) &&
1084                            (recv_opcode == gpm_opcode))
1085                         break;
1086
1087                 /* not expected message */
1088
1089                 /*
1090                  * check if it's cal_grant
1091                  *
1092                  * When we're waiting for cal_grant in reset routine,
1093                  * it's possible that BT sends out cal_request at the
1094                  * same time. Since BT's calibration doesn't happen
1095                  * that often, we'll let BT completes calibration then
1096                  * we continue to wait for cal_grant from BT.
1097                  * Orginal: Wait BT_CAL_GRANT.
1098                  * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT->wait
1099                  * BT_CAL_DONE -> Wait BT_CAL_GRANT.
1100                  */
1101
1102                 if ((gpm_type == MCI_GPM_BT_CAL_GRANT) &&
1103                     (recv_type == MCI_GPM_BT_CAL_REQ)) {
1104
1105                         u32 payload[4] = {0, 0, 0, 0};
1106
1107                         gpm_type = MCI_GPM_BT_CAL_DONE;
1108                         ath_dbg(common, MCI,
1109                                 "MCI Rcv BT_CAL_REQ, send WLAN_CAL_GRANT\n");
1110
1111                         MCI_GPM_SET_CAL_TYPE(payload,
1112                                         MCI_GPM_WLAN_CAL_GRANT);
1113
1114                         ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
1115                                                 false, false);
1116
1117                         ath_dbg(common, MCI, "MCI now wait for BT_CAL_DONE\n");
1118
1119                         continue;
1120                 } else {
1121                         ath_dbg(common, MCI, "MCI GPM subtype not match 0x%x\n",
1122                                 *(p_gpm + 1));
1123                         mismatch++;
1124                         ar9003_mci_process_gpm_extra(ah, recv_type,
1125                                         recv_opcode, p_gpm);
1126                 }
1127         }
1128         if (p_gpm) {
1129                 MCI_GPM_RECYCLE(p_gpm);
1130                 p_gpm = NULL;
1131         }
1132
1133         if (time_out <= 0) {
1134                 time_out = 0;
1135                 ath_dbg(common, MCI,
1136                         "MCI GPM received timeout, mismatch = %d\n", mismatch);
1137         } else
1138                 ath_dbg(common, MCI, "MCI Receive GPM type=0x%x, code=0x%x\n",
1139                         gpm_type, gpm_opcode);
1140
1141         while (more_data == MCI_GPM_MORE) {
1142
1143                 ath_dbg(common, MCI, "MCI discard remaining GPM\n");
1144                 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
1145                                           &more_data);
1146
1147                 if (offset == MCI_GPM_INVALID)
1148                         break;
1149
1150                 p_gpm = (u32 *) (mci->gpm_buf + offset);
1151                 recv_type = MCI_GPM_TYPE(p_gpm);
1152                 recv_opcode = MCI_GPM_OPCODE(p_gpm);
1153
1154                 if (!MCI_GPM_IS_CAL_TYPE(recv_type))
1155                         ar9003_mci_process_gpm_extra(ah, recv_type,
1156                                                      recv_opcode, p_gpm);
1157
1158                 MCI_GPM_RECYCLE(p_gpm);
1159         }
1160
1161         return time_out;
1162 }
1163
1164 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1165 {
1166         struct ath_common *common = ath9k_hw_common(ah);
1167         struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1168         u32 value = 0, more_gpm = 0, gpm_ptr;
1169         u8 query_type;
1170
1171         switch (state_type) {
1172         case MCI_STATE_ENABLE:
1173                 if (mci->ready) {
1174
1175                         value = REG_READ(ah, AR_BTCOEX_CTRL);
1176
1177                         if ((value == 0xdeadbeef) || (value == 0xffffffff))
1178                                 value = 0;
1179                 }
1180                 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
1181                 break;
1182         case MCI_STATE_INIT_GPM_OFFSET:
1183                 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1184                 ath_dbg(common, MCI, "MCI GPM initial WRITE_PTR=%d\n", value);
1185                 mci->gpm_idx = value;
1186                 break;
1187         case MCI_STATE_NEXT_GPM_OFFSET:
1188         case MCI_STATE_LAST_GPM_OFFSET:
1189                 /*
1190                 * This could be useful to avoid new GPM message interrupt which
1191                 * may lead to spurious interrupt after power sleep, or multiple
1192                 * entry of ath_mci_intr().
1193                 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
1194                 * alleviate this effect, but clearing GPM RX interrupt bit is
1195                 * safe, because whether this is called from hw or driver code
1196                 * there must be an interrupt bit set/triggered initially
1197                 */
1198                 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1199                           AR_MCI_INTERRUPT_RX_MSG_GPM);
1200
1201                 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1202                 value = gpm_ptr;
1203
1204                 if (value == 0)
1205                         value = mci->gpm_len - 1;
1206                 else if (value >= mci->gpm_len) {
1207                         if (value != 0xFFFF) {
1208                                 value = 0;
1209                                 ath_dbg(common, MCI,
1210                                         "MCI GPM offset out of range\n");
1211                         }
1212                 } else
1213                         value--;
1214
1215                 if (value == 0xFFFF) {
1216                         value = MCI_GPM_INVALID;
1217                         more_gpm = MCI_GPM_NOMORE;
1218                         ath_dbg(common, MCI,
1219                                 "MCI GPM ptr invalid @ptr=%d, offset=%d, more=GPM_NOMORE\n",
1220                                 gpm_ptr, value);
1221                 } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) {
1222
1223                         if (gpm_ptr == mci->gpm_idx) {
1224                                 value = MCI_GPM_INVALID;
1225                                 more_gpm = MCI_GPM_NOMORE;
1226
1227                                 ath_dbg(common, MCI,
1228                                         "MCI GPM message not available @ptr=%d, @offset=%d, more=GPM_NOMORE\n",
1229                                         gpm_ptr, value);
1230                         } else {
1231                                 for (;;) {
1232
1233                                         u32 temp_index;
1234
1235                                         /* skip reserved GPM if any */
1236
1237                                         if (value != mci->gpm_idx)
1238                                                 more_gpm = MCI_GPM_MORE;
1239                                         else
1240                                                 more_gpm = MCI_GPM_NOMORE;
1241
1242                                         temp_index = mci->gpm_idx;
1243                                         mci->gpm_idx++;
1244
1245                                         if (mci->gpm_idx >=
1246                                             mci->gpm_len)
1247                                                 mci->gpm_idx = 0;
1248
1249                                         ath_dbg(common, MCI,
1250                                                 "MCI GPM message got ptr=%d, @offset=%d, more=%d\n",
1251                                                 gpm_ptr, temp_index,
1252                                                 (more_gpm == MCI_GPM_MORE));
1253
1254                                         if (ar9003_mci_is_gpm_valid(ah,
1255                                                                 temp_index)) {
1256                                                 value = temp_index;
1257                                                 break;
1258                                         }
1259
1260                                         if (more_gpm == MCI_GPM_NOMORE) {
1261                                                 value = MCI_GPM_INVALID;
1262                                                 break;
1263                                         }
1264                                 }
1265                         }
1266                         if (p_data)
1267                                 *p_data = more_gpm;
1268                         }
1269
1270                         if (value != MCI_GPM_INVALID)
1271                                 value <<= 4;
1272
1273                         break;
1274         case MCI_STATE_LAST_SCHD_MSG_OFFSET:
1275                 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1276                                     AR_MCI_RX_LAST_SCHD_MSG_INDEX);
1277                 /* Make it in bytes */
1278                 value <<= 4;
1279                 break;
1280
1281         case MCI_STATE_REMOTE_SLEEP:
1282                 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1283                            AR_MCI_RX_REMOTE_SLEEP) ?
1284                         MCI_BT_SLEEP : MCI_BT_AWAKE;
1285                 break;
1286
1287         case MCI_STATE_CONT_RSSI_POWER:
1288                 value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER);
1289                         break;
1290
1291         case MCI_STATE_CONT_PRIORITY:
1292                 value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY);
1293                 break;
1294
1295         case MCI_STATE_CONT_TXRX:
1296                 value = MS(mci->cont_status, AR_MCI_CONT_TXRX);
1297                 break;
1298
1299         case MCI_STATE_BT:
1300                 value = mci->bt_state;
1301                 break;
1302
1303         case MCI_STATE_SET_BT_SLEEP:
1304                 mci->bt_state = MCI_BT_SLEEP;
1305                 break;
1306
1307         case MCI_STATE_SET_BT_AWAKE:
1308                 mci->bt_state = MCI_BT_AWAKE;
1309                 ar9003_mci_send_coex_version_query(ah, true);
1310                 ar9003_mci_send_coex_wlan_channels(ah, true);
1311
1312                 if (mci->unhalt_bt_gpm) {
1313
1314                         ath_dbg(common, MCI, "MCI unhalt BT GPM\n");
1315                         ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
1316                 }
1317
1318                 ar9003_mci_2g5g_switch(ah, true);
1319                 break;
1320
1321         case MCI_STATE_SET_BT_CAL_START:
1322                 mci->bt_state = MCI_BT_CAL_START;
1323                 break;
1324
1325         case MCI_STATE_SET_BT_CAL:
1326                 mci->bt_state = MCI_BT_CAL;
1327                 break;
1328
1329         case MCI_STATE_RESET_REQ_WAKE:
1330                 ar9003_mci_reset_req_wakeup(ah);
1331                 mci->update_2g5g = true;
1332
1333                 if ((AR_SREV_9462_20_OR_LATER(ah)) &&
1334                     (mci->config & ATH_MCI_CONFIG_MCI_OBS_MASK)) {
1335                         /* Check if we still have control of the GPIOs */
1336                         if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1337                                       ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1338                                         ATH_MCI_CONFIG_MCI_OBS_GPIO) {
1339
1340                                 ath_dbg(common, MCI,
1341                                         "MCI reconfigure observation\n");
1342                                 ar9003_mci_observation_set_up(ah);
1343                         }
1344                 }
1345                 break;
1346
1347         case MCI_STATE_SEND_WLAN_COEX_VERSION:
1348                 ar9003_mci_send_coex_version_response(ah, true);
1349                 break;
1350
1351         case MCI_STATE_SET_BT_COEX_VERSION:
1352
1353                 if (!p_data)
1354                         ath_dbg(common, MCI,
1355                                 "MCI Set BT Coex version with NULL data!!\n");
1356                 else {
1357                         mci->bt_ver_major = (*p_data >> 8) & 0xff;
1358                         mci->bt_ver_minor = (*p_data) & 0xff;
1359                         mci->bt_version_known = true;
1360                         ath_dbg(common, MCI, "MCI BT version set: %d.%d\n",
1361                                 mci->bt_ver_major, mci->bt_ver_minor);
1362                 }
1363                 break;
1364
1365         case MCI_STATE_SEND_WLAN_CHANNELS:
1366                 if (p_data) {
1367                         if (((mci->wlan_channels[1] & 0xffff0000) ==
1368                              (*(p_data + 1) & 0xffff0000)) &&
1369                             (mci->wlan_channels[2] == *(p_data + 2)) &&
1370                             (mci->wlan_channels[3] == *(p_data + 3)))
1371                                 break;
1372
1373                         mci->wlan_channels[0] = *p_data++;
1374                         mci->wlan_channels[1] = *p_data++;
1375                         mci->wlan_channels[2] = *p_data++;
1376                         mci->wlan_channels[3] = *p_data++;
1377                 }
1378                 mci->wlan_channels_update = true;
1379                 ar9003_mci_send_coex_wlan_channels(ah, true);
1380                 break;
1381
1382         case MCI_STATE_SEND_VERSION_QUERY:
1383                 ar9003_mci_send_coex_version_query(ah, true);
1384                 break;
1385
1386         case MCI_STATE_SEND_STATUS_QUERY:
1387                 query_type = (AR_SREV_9462_10(ah)) ?
1388                                 MCI_GPM_COEX_QUERY_BT_ALL_INFO :
1389                                 MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
1390
1391                 ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
1392                 break;
1393
1394         case MCI_STATE_NEED_FLUSH_BT_INFO:
1395                         /*
1396                          * btcoex_hw.mci.unhalt_bt_gpm means whether it's
1397                          * needed to send UNHALT message. It's set whenever
1398                          * there's a request to send HALT message.
1399                          * mci_halted_bt_gpm means whether HALT message is sent
1400                          * out successfully.
1401                          *
1402                          * Checking (mci_unhalt_bt_gpm == false) instead of
1403                          * checking (ah->mci_halted_bt_gpm == false) will make
1404                          * sure currently is in UNHALT-ed mode and BT can
1405                          * respond to status query.
1406                          */
1407                         value = (!mci->unhalt_bt_gpm &&
1408                                  mci->need_flush_btinfo) ? 1 : 0;
1409                         if (p_data)
1410                                 mci->need_flush_btinfo =
1411                                         (*p_data != 0) ? true : false;
1412                         break;
1413
1414         case MCI_STATE_RECOVER_RX:
1415
1416                 ath_dbg(common, MCI, "MCI hw RECOVER_RX\n");
1417                 ar9003_mci_prep_interface(ah);
1418                 mci->query_bt = true;
1419                 mci->need_flush_btinfo = true;
1420                 ar9003_mci_send_coex_wlan_channels(ah, true);
1421                 ar9003_mci_2g5g_switch(ah, true);
1422                 break;
1423
1424         case MCI_STATE_NEED_FTP_STOMP:
1425                 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
1426                 break;
1427
1428         case MCI_STATE_NEED_TUNING:
1429                 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING);
1430                 break;
1431
1432         default:
1433                 break;
1434
1435         }
1436
1437         return value;
1438 }
1439 EXPORT_SYMBOL(ar9003_mci_state);