2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
19 #include "ar9003_phy.h"
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
30 * register values to turn OFDM weak signal detection OFF
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
75 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 freq = centers.synth_center;
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) {
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
102 } else if (AR_SREV_9340(ah)) {
103 if (ah->is_clk_25mhz) {
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
110 channelSel = CHANSEL_2G(freq) >> 1;
112 channelSel = CHANSEL_2G(freq);
116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
119 channelSel = (freq * 2) / 75;
120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
121 channelSel = (channelSel << 17) | chan_frac;
123 channelSel = CHANSEL_5G(freq);
124 /* Doubler is ON, so, divide channelSel by 2. */
131 /* Enable fractional mode for all channels */
134 loadSynthChannel = 0;
136 reg32 = (bMode << 29);
137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
139 /* Enable Long shift Select for Synthesizer */
140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
143 /* Program Synth. setting */
144 reg32 = (channelSel << 2) | (fracMode << 30) |
145 (aModeRefSel << 28) | (loadSynthChannel << 31);
146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
148 /* Toggle Load Synth channel bit */
149 loadSynthChannel = 1;
150 reg32 = (channelSel << 2) | (fracMode << 30) |
151 (aModeRefSel << 28) | (loadSynthChannel << 31);
152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
155 ah->curchan_rad_index = -1;
161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
162 * @ah: atheros hardware structure
165 * For single-chip solutions. Converts to baseband spur frequency given the
166 * input channel frequency and compute register settings below.
168 * Spur mitigation for MRC CCK
170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
171 struct ath9k_channel *chan)
173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
174 int cur_bb_spur, negative = 0, cck_spur_freq;
176 int range, max_spur_cnts, synth_freq;
177 u8 *spur_fbin_ptr = NULL;
180 * Need to verify range +/- 10 MHz in control channel, otherwise spur
181 * is out-of-band and can be ignored.
184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
185 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
187 if (spur_fbin_ptr[0] == 0) /* No spur */
190 if (IS_CHAN_HT40(chan)) {
192 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
193 AR_PHY_GC_DYN2040_PRI_CH) == 0)
194 synth_freq = chan->channel + 10;
196 synth_freq = chan->channel - 10;
199 synth_freq = chan->channel;
202 range = AR_SREV_9462(ah) ? 5 : 10;
204 synth_freq = chan->channel;
207 for (i = 0; i < max_spur_cnts; i++) {
208 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
212 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
213 IS_CHAN_2GHZ(chan)) - synth_freq;
215 cur_bb_spur = spur_freq[i] - synth_freq;
217 if (cur_bb_spur < 0) {
219 cur_bb_spur = -cur_bb_spur;
221 if (cur_bb_spur < range) {
222 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
225 cck_spur_freq = -cck_spur_freq;
227 cck_spur_freq = cck_spur_freq & 0xfffff;
229 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
230 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
232 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
240 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
247 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
248 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
250 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
251 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
252 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
255 /* Clean all spur register fields */
256 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
258 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
259 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
261 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
262 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
263 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
264 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
265 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
266 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
268 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
269 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
270 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
271 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
273 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
279 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
280 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
281 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
282 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
283 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
284 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
286 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
287 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
288 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
289 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
290 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
291 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
292 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
293 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
294 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
295 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
296 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
299 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
302 int spur_delta_phase,
303 int spur_subchannel_sd)
307 /* OFDM Spur mitigation */
308 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
309 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
311 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
312 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
313 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
314 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
315 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
316 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
318 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
319 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
320 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
321 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
323 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
324 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
325 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
327 if (REG_READ_FIELD(ah, AR_PHY_MODE,
328 AR_PHY_MODE_DYNAMIC) == 0x1)
329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
330 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
332 mask_index = (freq_offset << 4) / 5;
334 mask_index = mask_index - 1;
336 mask_index = mask_index & 0x7f;
338 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
339 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
342 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
343 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
344 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
345 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
346 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
347 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
348 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
349 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
350 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
351 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
352 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
353 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
354 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
355 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
356 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
357 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
360 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
361 struct ath9k_channel *chan,
364 int spur_freq_sd = 0;
365 int spur_subchannel_sd = 0;
366 int spur_delta_phase = 0;
368 if (IS_CHAN_HT40(chan)) {
369 if (freq_offset < 0) {
370 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
371 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
372 spur_subchannel_sd = 1;
374 spur_subchannel_sd = 0;
376 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
379 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
380 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
381 spur_subchannel_sd = 0;
383 spur_subchannel_sd = 1;
385 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
389 spur_delta_phase = (freq_offset << 17) / 5;
392 spur_subchannel_sd = 0;
393 spur_freq_sd = (freq_offset << 9) /11;
394 spur_delta_phase = (freq_offset << 18) / 5;
397 spur_freq_sd = spur_freq_sd & 0x3ff;
398 spur_delta_phase = spur_delta_phase & 0xfffff;
400 ar9003_hw_spur_ofdm(ah,
407 /* Spur mitigation for OFDM */
408 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
409 struct ath9k_channel *chan)
417 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
419 if (IS_CHAN_5GHZ(chan)) {
420 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
424 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
428 if (spurChansPtr[0] == 0)
429 return; /* No spur in the mode */
431 if (IS_CHAN_HT40(chan)) {
433 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
434 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
435 synth_freq = chan->channel - 10;
437 synth_freq = chan->channel + 10;
440 synth_freq = chan->channel;
443 ar9003_hw_spur_ofdm_clear(ah);
445 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
446 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
447 if (abs(freq_offset) < range) {
448 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
454 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
455 struct ath9k_channel *chan)
457 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
458 ar9003_hw_spur_mitigate_ofdm(ah, chan);
461 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
462 struct ath9k_channel *chan)
466 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
468 if (chan && IS_CHAN_HALF_RATE(chan))
469 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
470 else if (chan && IS_CHAN_QUARTER_RATE(chan))
471 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
473 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
478 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
479 struct ath9k_channel *chan)
482 u32 enableDacFifo = 0;
485 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
487 /* Enable 11n HT, 20 MHz */
488 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
489 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
491 /* Configure baseband for dynamic 20/40 operation */
492 if (IS_CHAN_HT40(chan)) {
493 phymode |= AR_PHY_GC_DYN2040_EN;
494 /* Configure control (primary) channel at +-10MHz */
495 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
496 (chan->chanmode == CHANNEL_G_HT40PLUS))
497 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
501 /* make sure we preserve INI settings */
502 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
503 /* turn off Green Field detection for STA for now */
504 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
506 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
508 /* Configure MAC for 20/40 operation */
509 ath9k_hw_set11nmac2040(ah);
511 /* global transmit timeout (25 TUs default)*/
512 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
513 /* carrier sense timeout */
514 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
517 static void ar9003_hw_init_bb(struct ath_hw *ah,
518 struct ath9k_channel *chan)
523 * Wait for the frequency synth to settle (synth goes on
524 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
525 * Value is in 100ns increments.
527 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
529 synthDelay = (4 * synthDelay) / 22;
533 /* Activate the PHY (includes baseband activate + synthesizer on) */
534 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
537 * There is an issue if the AP starts the calibration before
538 * the base band timeout completes. This could result in the
539 * rx_clear false triggering. As a workaround we add delay an
540 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
543 udelay(synthDelay + BASE_ACTIVATE_DELAY);
546 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
550 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
551 AR_PHY_SWAP_ALT_CHAIN);
556 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
557 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
563 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
565 else if (AR_SREV_9462(ah))
566 /* xxx only when MCI support is enabled */
567 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
569 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
572 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
573 AR_PHY_SWAP_ALT_CHAIN);
578 * Override INI values with chip specific configuration.
580 static void ar9003_hw_override_ini(struct ath_hw *ah)
585 * Set the RX_ABORT and RX_DIS and clear it only after
586 * RXE is set for MAC. This prevents frames with
587 * corrupted descriptor status.
589 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
592 * For AR9280 and above, there is a new feature that allows
593 * Multicast search based on both MAC Address and Key ID. By default,
594 * this feature is enabled. But since the driver is not using this
595 * feature, we switch it off; otherwise multicast search based on
596 * MAC addr only will fail.
598 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
599 REG_WRITE(ah, AR_PCU_MISC_MODE2,
600 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
602 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
603 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
606 static void ar9003_hw_prog_ini(struct ath_hw *ah,
607 struct ar5416IniArray *iniArr,
610 unsigned int i, regWrites = 0;
612 /* New INI format: Array may be undefined (pre, core, post arrays) */
613 if (!iniArr->ia_array)
617 * New INI format: Pre, core, and post arrays for a given subsystem
618 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
619 * the array is non-modal and force the column to 1.
621 if (column >= iniArr->ia_columns)
624 for (i = 0; i < iniArr->ia_rows; i++) {
625 u32 reg = INI_RA(iniArr, i, 0);
626 u32 val = INI_RA(iniArr, i, column);
628 REG_WRITE(ah, reg, val);
634 static int ar9003_hw_process_ini(struct ath_hw *ah,
635 struct ath9k_channel *chan)
637 unsigned int regWrites = 0, i;
640 switch (chan->chanmode) {
645 case CHANNEL_A_HT40PLUS:
646 case CHANNEL_A_HT40MINUS:
654 case CHANNEL_G_HT40PLUS:
655 case CHANNEL_G_HT40MINUS:
663 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
664 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
665 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
666 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
667 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
668 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
669 ar9003_hw_prog_ini(ah,
670 &ah->ini_radio_post_sys2ant,
674 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
675 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
678 * For 5GHz channels requiring Fast Clock, apply
679 * different modal values.
681 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
682 REG_WRITE_ARRAY(&ah->iniModesFastClock,
683 modesIndex, regWrites);
685 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
687 if (AR_SREV_9462(ah))
688 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
690 if (chan->channel == 2484)
691 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
693 ah->modes_index = modesIndex;
694 ar9003_hw_override_ini(ah);
695 ar9003_hw_set_channel_regs(ah, chan);
696 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
697 ath9k_hw_apply_txpower(ah, chan, false);
699 if (AR_SREV_9462(ah)) {
700 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
701 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
702 ah->enabled_cals |= TX_IQ_CAL;
704 ah->enabled_cals &= ~TX_IQ_CAL;
706 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
707 ah->enabled_cals |= TX_CL_CAL;
709 ah->enabled_cals &= ~TX_CL_CAL;
715 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
716 struct ath9k_channel *chan)
723 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
724 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
726 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
727 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
729 REG_WRITE(ah, AR_PHY_MODE, rfMode);
732 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
734 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
737 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
738 struct ath9k_channel *chan)
740 u32 coef_scaled, ds_coef_exp, ds_coef_man;
741 u32 clockMhzScaled = 0x64000000;
742 struct chan_centers centers;
745 * half and quarter rate can divide the scaled clock by 2 or 4
746 * scale for selected channel bandwidth
748 if (IS_CHAN_HALF_RATE(chan))
749 clockMhzScaled = clockMhzScaled >> 1;
750 else if (IS_CHAN_QUARTER_RATE(chan))
751 clockMhzScaled = clockMhzScaled >> 2;
754 * ALGO -> coef = 1e8/fcarrier*fclock/40;
755 * scaled coef to provide precision for this floating calculation
757 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
758 coef_scaled = clockMhzScaled / centers.synth_center;
760 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
763 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
764 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
765 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
766 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
770 * scaled coeff is 9/10 that of normal coeff
772 coef_scaled = (9 * coef_scaled) / 10;
774 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
778 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
779 AR_PHY_SGI_DSC_MAN, ds_coef_man);
780 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
781 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
784 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
786 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
787 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
788 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
792 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
793 * Read the phy active delay register. Value is in 100ns increments.
795 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
797 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
798 if (IS_CHAN_B(ah->curchan))
799 synthDelay = (4 * synthDelay) / 22;
803 udelay(synthDelay + BASE_ACTIVATE_DELAY);
805 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
808 static bool ar9003_hw_ani_control(struct ath_hw *ah,
809 enum ath9k_ani_cmd cmd, int param)
811 struct ath_common *common = ath9k_hw_common(ah);
812 struct ath9k_channel *chan = ah->curchan;
813 struct ar5416AniState *aniState = &chan->ani;
816 switch (cmd & ah->ani_function) {
817 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
819 * on == 1 means ofdm weak signal detection is ON
820 * on == 1 is the default, for less noise immunity
822 * on == 0 means ofdm weak signal detection is OFF
823 * on == 0 means more noise imm
825 u32 on = param ? 1 : 0;
827 * make register setting for default
828 * (weak sig detect ON) come from INI file
830 int m1ThreshLow = on ?
831 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
832 int m2ThreshLow = on ?
833 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
835 aniState->iniDef.m1Thresh : m1Thresh_off;
837 aniState->iniDef.m2Thresh : m2Thresh_off;
838 int m2CountThr = on ?
839 aniState->iniDef.m2CountThr : m2CountThr_off;
840 int m2CountThrLow = on ?
841 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
842 int m1ThreshLowExt = on ?
843 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
844 int m2ThreshLowExt = on ?
845 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
846 int m1ThreshExt = on ?
847 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
848 int m2ThreshExt = on ?
849 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
851 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
852 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
854 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
855 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
857 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
858 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
859 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
860 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
861 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
862 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
863 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
864 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
867 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
868 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
869 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
870 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
871 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
872 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
873 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
874 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
877 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
878 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
880 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
881 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
883 if (!on != aniState->ofdmWeakSigDetectOff) {
885 "** ch %d: ofdm weak signal: %s=>%s\n",
887 !aniState->ofdmWeakSigDetectOff ?
891 ah->stats.ast_ani_ofdmon++;
893 ah->stats.ast_ani_ofdmoff++;
894 aniState->ofdmWeakSigDetectOff = !on;
898 case ATH9K_ANI_FIRSTEP_LEVEL:{
901 if (level >= ARRAY_SIZE(firstep_table)) {
903 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
904 level, ARRAY_SIZE(firstep_table));
909 * make register setting relative to default
910 * from INI file & cap value
912 value = firstep_table[level] -
913 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
914 aniState->iniDef.firstep;
915 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
916 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
917 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
918 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
919 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
920 AR_PHY_FIND_SIG_FIRSTEP,
923 * we need to set first step low register too
924 * make register setting relative to default
925 * from INI file & cap value
927 value2 = firstep_table[level] -
928 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
929 aniState->iniDef.firstepLow;
930 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
931 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
932 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
933 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
935 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
936 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
938 if (level != aniState->firstepLevel) {
940 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
942 aniState->firstepLevel,
944 ATH9K_ANI_FIRSTEP_LVL_NEW,
946 aniState->iniDef.firstep);
948 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
950 aniState->firstepLevel,
952 ATH9K_ANI_FIRSTEP_LVL_NEW,
954 aniState->iniDef.firstepLow);
955 if (level > aniState->firstepLevel)
956 ah->stats.ast_ani_stepup++;
957 else if (level < aniState->firstepLevel)
958 ah->stats.ast_ani_stepdown++;
959 aniState->firstepLevel = level;
963 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
966 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
968 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
969 level, ARRAY_SIZE(cycpwrThr1_table));
973 * make register setting relative to default
974 * from INI file & cap value
976 value = cycpwrThr1_table[level] -
977 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
978 aniState->iniDef.cycpwrThr1;
979 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
980 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
981 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
982 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
983 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
984 AR_PHY_TIMING5_CYCPWR_THR1,
988 * set AR_PHY_EXT_CCA for extension channel
989 * make register setting relative to default
990 * from INI file & cap value
992 value2 = cycpwrThr1_table[level] -
993 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
994 aniState->iniDef.cycpwrThr1Ext;
995 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
996 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
997 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
998 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
999 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1000 AR_PHY_EXT_CYCPWR_THR1, value2);
1002 if (level != aniState->spurImmunityLevel) {
1003 ath_dbg(common, ANI,
1004 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1006 aniState->spurImmunityLevel,
1008 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1010 aniState->iniDef.cycpwrThr1);
1011 ath_dbg(common, ANI,
1012 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1014 aniState->spurImmunityLevel,
1016 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1018 aniState->iniDef.cycpwrThr1Ext);
1019 if (level > aniState->spurImmunityLevel)
1020 ah->stats.ast_ani_spurup++;
1021 else if (level < aniState->spurImmunityLevel)
1022 ah->stats.ast_ani_spurdown++;
1023 aniState->spurImmunityLevel = level;
1027 case ATH9K_ANI_MRC_CCK:{
1029 * is_on == 1 means MRC CCK ON (default, less noise imm)
1030 * is_on == 0 means MRC CCK is OFF (more noise imm)
1032 bool is_on = param ? 1 : 0;
1033 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1034 AR_PHY_MRC_CCK_ENABLE, is_on);
1035 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1036 AR_PHY_MRC_CCK_MUX_REG, is_on);
1037 if (!is_on != aniState->mrcCCKOff) {
1038 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1040 !aniState->mrcCCKOff ? "on" : "off",
1041 is_on ? "on" : "off");
1043 ah->stats.ast_ani_ccklow++;
1045 ah->stats.ast_ani_cckhigh++;
1046 aniState->mrcCCKOff = !is_on;
1050 case ATH9K_ANI_PRESENT:
1053 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1057 ath_dbg(common, ANI,
1058 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1059 aniState->spurImmunityLevel,
1060 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1061 aniState->firstepLevel,
1062 !aniState->mrcCCKOff ? "on" : "off",
1063 aniState->listenTime,
1064 aniState->ofdmPhyErrCount,
1065 aniState->cckPhyErrCount);
1069 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1070 int16_t nfarray[NUM_NF_READINGS])
1072 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1073 #define AR_PHY_CH_MINCCA_PWR_S 20
1074 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1075 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1080 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1081 if (ah->rxchainmask & BIT(i)) {
1082 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1083 AR_PHY_CH_MINCCA_PWR);
1084 nfarray[i] = sign_extend32(nf, 8);
1086 if (IS_CHAN_HT40(ah->curchan)) {
1087 u8 ext_idx = AR9300_MAX_CHAINS + i;
1089 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1090 AR_PHY_CH_EXT_MINCCA_PWR);
1091 nfarray[ext_idx] = sign_extend32(nf, 8);
1097 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1099 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1100 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1101 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1102 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1103 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1104 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1106 if (AR_SREV_9330(ah))
1107 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1109 if (AR_SREV_9462(ah)) {
1110 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1111 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1112 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1113 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1118 * Initialize the ANI register values with default (ini) values.
1119 * This routine is called during a (full) hardware reset after
1120 * all the registers are initialised from the INI.
1122 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1124 struct ar5416AniState *aniState;
1125 struct ath_common *common = ath9k_hw_common(ah);
1126 struct ath9k_channel *chan = ah->curchan;
1127 struct ath9k_ani_default *iniDef;
1130 aniState = &ah->curchan->ani;
1131 iniDef = &aniState->iniDef;
1133 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1134 ah->hw_version.macVersion,
1135 ah->hw_version.macRev,
1138 chan->channelFlags);
1140 val = REG_READ(ah, AR_PHY_SFCORR);
1141 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1142 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1143 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1145 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1146 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1147 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1148 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1150 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1151 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1152 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1153 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1154 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1155 iniDef->firstep = REG_READ_FIELD(ah,
1157 AR_PHY_FIND_SIG_FIRSTEP);
1158 iniDef->firstepLow = REG_READ_FIELD(ah,
1159 AR_PHY_FIND_SIG_LOW,
1160 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1161 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1163 AR_PHY_TIMING5_CYCPWR_THR1);
1164 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1166 AR_PHY_EXT_CYCPWR_THR1);
1168 /* these levels just got reset to defaults by the INI */
1169 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1170 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1171 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1172 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1175 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1176 struct ath_hw_radar_conf *conf)
1178 u32 radar_0 = 0, radar_1 = 0;
1181 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1185 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1186 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1187 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1188 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1189 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1190 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1192 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1193 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1194 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1195 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1196 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1198 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1199 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1200 if (conf->ext_channel)
1201 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1203 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1206 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1208 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1210 conf->fir_power = -28;
1211 conf->radar_rssi = 0;
1212 conf->pulse_height = 10;
1213 conf->pulse_rssi = 24;
1214 conf->pulse_inband = 8;
1215 conf->pulse_maxlen = 255;
1216 conf->pulse_inband_step = 12;
1217 conf->radar_inband = 8;
1220 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1221 struct ath_hw_antcomb_conf *antconf)
1225 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1226 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1227 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1228 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1229 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1230 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1231 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1233 if (AR_SREV_9330_11(ah)) {
1234 antconf->lna1_lna2_delta = -9;
1235 antconf->div_group = 1;
1236 } else if (AR_SREV_9485(ah)) {
1237 antconf->lna1_lna2_delta = -9;
1238 antconf->div_group = 2;
1240 antconf->lna1_lna2_delta = -3;
1241 antconf->div_group = 0;
1245 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1246 struct ath_hw_antcomb_conf *antconf)
1250 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1251 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1252 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1253 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1254 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1255 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1256 regval |= ((antconf->main_lna_conf <<
1257 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1258 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1259 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1260 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1261 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1262 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1263 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1264 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1265 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1266 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1268 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1271 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1272 struct ath9k_channel *chan,
1275 unsigned int regWrites = 0;
1278 switch (chan->chanmode) {
1280 case CHANNEL_A_HT20:
1283 case CHANNEL_A_HT40PLUS:
1284 case CHANNEL_A_HT40MINUS:
1288 case CHANNEL_G_HT20:
1292 case CHANNEL_G_HT40PLUS:
1293 case CHANNEL_G_HT40MINUS:
1301 if (modesIndex == ah->modes_index) {
1302 *ini_reloaded = false;
1306 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1307 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1308 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1309 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1310 if (AR_SREV_9462_20(ah))
1311 ar9003_hw_prog_ini(ah,
1312 &ah->ini_radio_post_sys2ant,
1315 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1318 * For 5GHz channels requiring Fast Clock, apply
1319 * different modal values.
1321 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1322 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1324 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1326 ah->modes_index = modesIndex;
1327 *ini_reloaded = true;
1330 ar9003_hw_set_rfmode(ah, chan);
1334 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1336 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1337 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1338 static const u32 ar9300_cca_regs[6] = {
1347 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1348 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1349 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1350 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1351 priv_ops->init_bb = ar9003_hw_init_bb;
1352 priv_ops->process_ini = ar9003_hw_process_ini;
1353 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1354 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1355 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1356 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1357 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1358 priv_ops->ani_control = ar9003_hw_ani_control;
1359 priv_ops->do_getnf = ar9003_hw_do_getnf;
1360 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1361 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1362 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1364 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1365 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1367 ar9003_hw_set_nf_limits(ah);
1368 ar9003_hw_set_radar_conf(ah);
1369 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1372 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1374 struct ath_common *common = ath9k_hw_common(ah);
1375 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1376 u32 val, idle_count;
1379 /* disable IRQ, disable chip-reset for BB panic */
1380 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1381 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1382 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1383 AR_PHY_WATCHDOG_IRQ_ENABLE));
1385 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1386 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1387 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1388 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1389 AR_PHY_WATCHDOG_IDLE_ENABLE));
1391 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1395 /* enable IRQ, disable chip-reset for BB watchdog */
1396 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1397 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1398 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1399 ~AR_PHY_WATCHDOG_RST_ENABLE);
1401 /* bound limit to 10 secs */
1402 if (idle_tmo_ms > 10000)
1403 idle_tmo_ms = 10000;
1406 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1408 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1409 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1411 * Given we use fast clock now in 5 GHz, these time units should
1412 * be common for both 2 GHz and 5 GHz.
1414 idle_count = (100 * idle_tmo_ms) / 74;
1415 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1416 idle_count = (100 * idle_tmo_ms) / 37;
1419 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1420 * set idle time-out.
1422 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1423 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1424 AR_PHY_WATCHDOG_IDLE_MASK |
1425 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1427 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1431 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1434 * we want to avoid printing in ISR context so we save the
1435 * watchdog status to be printed later in bottom half context.
1437 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1440 * the watchdog timer should reset on status read but to be sure
1441 * sure we write 0 to the watchdog status bit.
1443 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1444 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1447 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1449 struct ath_common *common = ath9k_hw_common(ah);
1452 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1455 status = ah->bb_watchdog_last_status;
1456 ath_dbg(common, RESET,
1457 "\n==== BB update: BB status=0x%08x ====\n", status);
1458 ath_dbg(common, RESET,
1459 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1460 MS(status, AR_PHY_WATCHDOG_INFO),
1461 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1462 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1463 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1464 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1465 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1466 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1467 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1468 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1470 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1471 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1472 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1473 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1474 REG_READ(ah, AR_PHY_GEN_CTRL));
1476 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1477 if (common->cc_survey.cycles)
1478 ath_dbg(common, RESET,
1479 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1480 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1482 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1484 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1486 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1490 /* While receiving unsupported rate frame rx state machine
1491 * gets into a state 0xb and if phy_restart happens in that
1492 * state, BB would go hang. If RXSM is in 0xb state after
1493 * first bb panic, ensure to disable the phy_restart.
1495 if (!((MS(ah->bb_watchdog_last_status,
1496 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1497 ah->bb_hang_rx_ofdm))
1500 ah->bb_hang_rx_ofdm = true;
1501 val = REG_READ(ah, AR_PHY_RESTART);
1502 val &= ~AR_PHY_RESTART_ENA;
1504 REG_WRITE(ah, AR_PHY_RESTART, val);
1506 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);