2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/leds.h>
23 #include <linux/completion.h>
29 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
30 * should rely on this file or its contents.
35 /* Macro to expand scalars to 64-bit objects */
37 #define ito64(x) (sizeof(x) == 1) ? \
38 (((unsigned long long int)(x)) & (0xff)) : \
40 (((unsigned long long int)(x)) & 0xffff) : \
42 (((unsigned long long int)(x)) & 0xffffffff) : \
43 (unsigned long long int)(x))
45 /* increment with wrap-around */
46 #define INCR(_l, _sz) do { \
48 (_l) &= ((_sz) - 1); \
51 /* decrement with wrap-around */
52 #define DECR(_l, _sz) do { \
54 (_l) &= ((_sz) - 1); \
57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
59 #define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
70 /*************************/
71 /* Descriptor Management */
72 /*************************/
74 #define ATH_TXBUF_RESET(_bf) do { \
75 (_bf)->bf_stale = false; \
76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
82 #define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
87 * enum buffer_type - Buffer type flags
89 * @BUF_HT: Send this buffer using HT capabilities
90 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
91 * @BUF_AGGR: Indicates whether the buffer can be aggregated
92 * (used in aggregation scheduling)
93 * @BUF_RETRY: Indicates whether the buffer is retried
94 * @BUF_XRETRY: To denote excessive retries of the buffer
104 #define bf_nframes bf_state.bfs_nframes
105 #define bf_al bf_state.bfs_al
106 #define bf_frmlen bf_state.bfs_frmlen
107 #define bf_retries bf_state.bfs_retries
108 #define bf_seqno bf_state.bfs_seqno
109 #define bf_tidno bf_state.bfs_tidno
110 #define bf_keyix bf_state.bfs_keyix
111 #define bf_keytype bf_state.bfs_keytype
112 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
113 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
114 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
115 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
116 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
118 #define ATH_TXSTATUS_RING_SIZE 64
122 dma_addr_t dd_desc_paddr;
124 struct ath_buf *dd_bufptr;
127 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
128 struct list_head *head, const char *name,
129 int nbuf, int ndesc, bool is_tx);
130 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
131 struct list_head *head);
137 #define ATH_MAX_ANTENNA 3
138 #define ATH_RXBUF 512
139 #define ATH_TXBUF 512
140 #define ATH_TXBUF_RESERVE 5
141 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
142 #define ATH_TXMAXTRY 13
143 #define ATH_MGT_TXMAXTRY 4
145 #define TID_TO_WME_AC(_tid) \
146 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
147 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
148 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
151 #define ADDBA_EXCHANGE_ATTEMPTS 10
152 #define ATH_AGGR_DELIM_SZ 4
153 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
154 /* number of delimiters for encryption padding */
155 #define ATH_AGGR_ENCRYPTDELIM 10
156 /* minimum h/w qdepth to be sustained to maximize aggregation */
157 #define ATH_AGGR_MIN_QDEPTH 2
158 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
160 #define IEEE80211_SEQ_SEQ_SHIFT 4
161 #define IEEE80211_SEQ_MAX 4096
162 #define IEEE80211_WEP_IVLEN 3
163 #define IEEE80211_WEP_KIDLEN 1
164 #define IEEE80211_WEP_CRCLEN 4
165 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
166 (IEEE80211_WEP_IVLEN + \
167 IEEE80211_WEP_KIDLEN + \
168 IEEE80211_WEP_CRCLEN))
170 /* return whether a bit at index _n in bitmap _bm is set
171 * _sz is the size of the bitmap */
172 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
173 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
175 /* return block-ack bitmap index given sequence and starting sequence */
176 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
178 /* returns delimiter padding required given the packet length */
179 #define ATH_AGGR_GET_NDELIM(_len) \
180 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
181 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
183 #define BAW_WITHIN(_start, _bawsz, _seqno) \
184 ((((_seqno) - (_start)) & 4095) < (_bawsz))
186 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
188 #define ATH_TX_COMPLETE_POLL_INT 1000
190 enum ATH_AGGR_STATUS {
196 #define ATH_TXFIFO_DEPTH 8
201 struct list_head axq_q;
205 bool axq_tx_inprogress;
206 struct list_head axq_acq;
207 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
208 struct list_head txq_fifo_pending;
216 struct list_head list;
217 struct list_head tid_q;
220 struct ath_buf_state {
229 unsigned long bfs_paprd_timestamp;
231 enum ath9k_key_type bfs_keytype;
235 struct list_head list;
236 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
238 struct ath_buf *bf_next; /* next subframe in the aggregate */
239 struct sk_buff *bf_mpdu; /* enclosing frame structure */
240 void *bf_desc; /* virtual addr of desc */
241 dma_addr_t bf_daddr; /* physical addr of desc */
242 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
246 struct ath_buf_state bf_state;
247 struct ath_wiphy *aphy;
251 struct list_head list;
252 struct list_head buf_q;
254 struct ath_atx_ac *ac;
255 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
260 int baw_head; /* first un-acked tx buffer */
261 int baw_tail; /* next unused tx buffer slot */
268 struct ath_common *common;
269 struct ath_atx_tid tid[WME_NUM_TID];
270 struct ath_atx_ac ac[WME_NUM_AC];
275 #define AGGR_CLEANUP BIT(1)
276 #define AGGR_ADDBA_COMPLETE BIT(2)
277 #define AGGR_ADDBA_PROGRESS BIT(3)
279 struct ath_tx_control {
282 enum ath9k_internal_frame_type frame_type;
286 #define ATH_TX_ERROR 0x01
287 #define ATH_TX_XRETRY 0x02
288 #define ATH_TX_BAR 0x04
293 int hwq_map[WME_NUM_AC];
294 spinlock_t txbuflock;
295 struct list_head txbuf;
296 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
297 struct ath_descdma txdma;
298 int pending_frames[WME_NUM_AC];
302 struct sk_buff_head rx_fifo;
303 struct sk_buff_head rx_buffers;
311 unsigned int rxfilter;
312 spinlock_t rxbuflock;
313 struct list_head rxbuf;
314 struct ath_descdma rxdma;
315 struct ath_buf *rx_bufptr;
316 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
319 int ath_startrecv(struct ath_softc *sc);
320 bool ath_stoprecv(struct ath_softc *sc);
321 void ath_flushrecv(struct ath_softc *sc);
322 u32 ath_calcrxfilter(struct ath_softc *sc);
323 int ath_rx_init(struct ath_softc *sc, int nbufs);
324 void ath_rx_cleanup(struct ath_softc *sc);
325 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
326 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
327 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
328 int ath_tx_setup(struct ath_softc *sc, int haltype);
329 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
330 void ath_draintxq(struct ath_softc *sc,
331 struct ath_txq *txq, bool retry_tx);
332 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
333 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
334 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
335 int ath_tx_init(struct ath_softc *sc, int nbufs);
336 void ath_tx_cleanup(struct ath_softc *sc);
337 int ath_txq_update(struct ath_softc *sc, int qnum,
338 struct ath9k_tx_queue_info *q);
339 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
340 struct ath_tx_control *txctl);
341 void ath_tx_tasklet(struct ath_softc *sc);
342 void ath_tx_edma_tasklet(struct ath_softc *sc);
343 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
344 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
346 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
347 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
355 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
356 enum nl80211_iftype av_opmode;
357 struct ath_buf *av_bcbuf;
358 struct ath_tx_control av_btxctl;
359 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
362 /*******************/
363 /* Beacon Handling */
364 /*******************/
367 * Regardless of the number of beacons we stagger, (i.e. regardless of the
368 * number of BSSIDs) if a given beacon does not go out even after waiting this
369 * number of beacon intervals, the game's up.
371 #define BSTUCK_THRESH (9 * ATH_BCBUF)
373 #define ATH_DEFAULT_BINTVAL 100 /* TU */
374 #define ATH_DEFAULT_BMISS_LIMIT 10
375 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
377 struct ath_beacon_config {
387 OK, /* no change needed */
388 UPDATE, /* update pending */
389 COMMIT /* beacon sent, commit change */
390 } updateslot; /* slot time update fsm */
396 struct ieee80211_vif *bslot[ATH_BCBUF];
397 struct ath_wiphy *bslot_aphy[ATH_BCBUF];
400 struct ath9k_tx_queue_info beacon_qi;
401 struct ath_descdma bdma;
402 struct ath_txq *cabq;
403 struct list_head bbuf;
406 void ath_beacon_tasklet(unsigned long data);
407 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
408 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
409 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
410 int ath_beaconq_config(struct ath_softc *sc);
416 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
417 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
418 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
419 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
420 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
421 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
422 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
424 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
426 void ath_hw_check(struct work_struct *work);
427 void ath_paprd_calibrate(struct work_struct *work);
428 void ath_ani_calibrate(unsigned long data);
435 bool hw_timer_enabled;
436 spinlock_t btcoex_lock;
437 struct timer_list period_timer; /* Timer for BT period */
439 unsigned long bt_priority_time;
440 int bt_stomp_type; /* Types of BT stomping */
441 u32 btcoex_no_stomp; /* in usec */
442 u32 btcoex_period; /* in usec */
443 u32 btscan_no_stomp; /* in usec */
444 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
447 int ath_init_btcoex_timer(struct ath_softc *sc);
448 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
449 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
451 /********************/
453 /********************/
455 #define ATH_LED_PIN_DEF 1
456 #define ATH_LED_PIN_9287 8
457 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
458 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
468 struct ath_softc *sc;
469 struct led_classdev led_cdev;
470 enum ath_led_type led_type;
475 void ath_init_leds(struct ath_softc *sc);
476 void ath_deinit_leds(struct ath_softc *sc);
478 /* Antenna diversity/combining */
479 #define ATH_ANT_RX_CURRENT_SHIFT 4
480 #define ATH_ANT_RX_MAIN_SHIFT 2
481 #define ATH_ANT_RX_MASK 0x3
483 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
484 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
485 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
486 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
487 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
488 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
489 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
491 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
492 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
493 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
494 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
495 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
497 enum ath9k_ant_div_comb_lna_conf {
498 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
499 ATH_ANT_DIV_COMB_LNA2,
500 ATH_ANT_DIV_COMB_LNA1,
501 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
504 struct ath_ant_comb {
523 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
524 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
529 unsigned long scan_start_time;
532 /********************/
533 /* Main driver core */
534 /********************/
537 * Default cache line size, in bytes.
538 * Used when PCI device not fully initialized by bootrom/BIOS
540 #define DEFAULT_CACHELINE 32
541 #define ATH_REGCLASSIDS_MAX 10
542 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
543 #define ATH_MAX_SW_RETRIES 10
544 #define ATH_CHAN_MAX 255
545 #define IEEE80211_WEP_NKID 4 /* number of key ids */
547 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
548 #define ATH_RATE_DUMMY_MARKER 0
550 #define SC_OP_INVALID BIT(0)
551 #define SC_OP_BEACONS BIT(1)
552 #define SC_OP_RXAGGR BIT(2)
553 #define SC_OP_TXAGGR BIT(3)
554 #define SC_OP_OFFCHANNEL BIT(4)
555 #define SC_OP_PREAMBLE_SHORT BIT(5)
556 #define SC_OP_PROTECT_ENABLE BIT(6)
557 #define SC_OP_RXFLUSH BIT(7)
558 #define SC_OP_LED_ASSOCIATED BIT(8)
559 #define SC_OP_LED_ON BIT(9)
560 #define SC_OP_TSF_RESET BIT(11)
561 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
562 #define SC_OP_BT_SCAN BIT(13)
563 #define SC_OP_ANI_RUN BIT(14)
565 /* Powersave flags */
566 #define PS_WAIT_FOR_BEACON BIT(0)
567 #define PS_WAIT_FOR_CAB BIT(1)
568 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
569 #define PS_WAIT_FOR_TX_ACK BIT(3)
570 #define PS_BEACON_SYNC BIT(4)
573 struct ath_rate_table;
576 struct ieee80211_hw *hw;
579 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
580 struct ath_wiphy *pri_wiphy;
581 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
582 * have NULL entries */
583 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
586 struct ath_wiphy *next_wiphy;
587 struct work_struct chan_work;
588 int wiphy_select_failures;
589 unsigned long wiphy_select_first_fail;
590 struct delayed_work wiphy_work;
591 unsigned long wiphy_scheduler_int;
592 int wiphy_scheduler_index;
593 struct survey_info *cur_survey;
594 struct survey_info survey[ATH9K_NUM_CHANNELS];
596 struct tasklet_struct intr_tq;
597 struct tasklet_struct bcon_tasklet;
598 struct ath_hw *sc_ah;
601 spinlock_t sc_serial_rw;
602 spinlock_t sc_pm_lock;
603 spinlock_t sc_pcu_lock;
605 struct work_struct paprd_work;
606 struct work_struct hw_check_work;
607 struct completion paprd_complete;
610 u32 sc_flags; /* SC_OP_* */
611 u16 ps_flags; /* PS_* */
617 unsigned long ps_usecount;
619 struct ath_config config;
622 struct ath_beacon beacon;
623 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
625 struct ath_led radio_led;
626 struct ath_led assoc_led;
627 struct ath_led tx_led;
628 struct ath_led rx_led;
629 struct delayed_work ath_led_blink_work;
631 int led_off_duration;
637 #ifdef CONFIG_ATH9K_DEBUGFS
638 struct ath9k_debug debug;
640 struct ath_beacon_config cur_beacon_conf;
641 struct delayed_work tx_complete_work;
642 struct ath_btcoex btcoex;
644 struct ath_descdma txsdma;
646 struct ath_ant_comb ant_comb;
650 struct ath_softc *sc; /* shared for all virtual wiphys */
651 struct ieee80211_hw *hw;
652 struct ath9k_hw_cal_data caldata;
653 enum ath_wiphy_state {
666 void ath9k_tasklet(unsigned long data);
667 int ath_reset(struct ath_softc *sc, bool retry_tx);
668 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
669 int ath_cabq_update(struct ath_softc *);
671 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
673 common->bus_ops->read_cachesize(common, csz);
676 extern struct ieee80211_ops ath9k_ops;
677 extern int modparam_nohwcrypt;
678 extern int led_blink;
680 irqreturn_t ath_isr(int irq, void *dev);
681 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
682 const struct ath_bus_ops *bus_ops);
683 void ath9k_deinit_device(struct ath_softc *sc);
684 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
685 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
686 struct ath9k_channel *ichan);
687 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
688 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
689 struct ath9k_channel *hchan);
691 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
692 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
693 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
696 int ath_pci_init(void);
697 void ath_pci_exit(void);
699 static inline int ath_pci_init(void) { return 0; };
700 static inline void ath_pci_exit(void) {};
703 #ifdef CONFIG_ATHEROS_AR71XX
704 int ath_ahb_init(void);
705 void ath_ahb_exit(void);
707 static inline int ath_ahb_init(void) { return 0; };
708 static inline void ath_ahb_exit(void) {};
711 void ath9k_ps_wakeup(struct ath_softc *sc);
712 void ath9k_ps_restore(struct ath_softc *sc);
714 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
715 int ath9k_wiphy_add(struct ath_softc *sc);
716 int ath9k_wiphy_del(struct ath_wiphy *aphy);
717 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
718 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
719 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
720 int ath9k_wiphy_select(struct ath_wiphy *aphy);
721 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
722 void ath9k_wiphy_chan_work(struct work_struct *work);
723 bool ath9k_wiphy_started(struct ath_softc *sc);
724 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
725 struct ath_wiphy *selected);
726 bool ath9k_wiphy_scanning(struct ath_softc *sc);
727 void ath9k_wiphy_work(struct work_struct *work);
728 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
729 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
731 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
732 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
734 void ath_start_rfkill_poll(struct ath_softc *sc);
735 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);