2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/leds.h>
23 #include <linux/completion.h>
29 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
30 * should rely on this file or its contents.
35 /* Macro to expand scalars to 64-bit objects */
37 #define ito64(x) (sizeof(x) == 1) ? \
38 (((unsigned long long int)(x)) & (0xff)) : \
40 (((unsigned long long int)(x)) & 0xffff) : \
42 (((unsigned long long int)(x)) & 0xffffffff) : \
43 (unsigned long long int)(x))
45 /* increment with wrap-around */
46 #define INCR(_l, _sz) do { \
48 (_l) &= ((_sz) - 1); \
51 /* decrement with wrap-around */
52 #define DECR(_l, _sz) do { \
54 (_l) &= ((_sz) - 1); \
57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
59 #define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
70 /*************************/
71 /* Descriptor Management */
72 /*************************/
74 #define ATH_TXBUF_RESET(_bf) do { \
75 (_bf)->bf_stale = false; \
76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
82 #define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
87 * enum buffer_type - Buffer type flags
89 * @BUF_HT: Send this buffer using HT capabilities
90 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
91 * @BUF_AGGR: Indicates whether the buffer can be aggregated
92 * (used in aggregation scheduling)
93 * @BUF_RETRY: Indicates whether the buffer is retried
94 * @BUF_XRETRY: To denote excessive retries of the buffer
104 #define bf_nframes bf_state.bfs_nframes
105 #define bf_al bf_state.bfs_al
106 #define bf_frmlen bf_state.bfs_frmlen
107 #define bf_retries bf_state.bfs_retries
108 #define bf_keyix bf_state.bfs_keyix
109 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
110 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
111 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
112 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
113 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
115 #define ATH_TXSTATUS_RING_SIZE 64
119 dma_addr_t dd_desc_paddr;
121 struct ath_buf *dd_bufptr;
124 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
125 struct list_head *head, const char *name,
126 int nbuf, int ndesc, bool is_tx);
127 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
128 struct list_head *head);
134 #define ATH_MAX_ANTENNA 3
135 #define ATH_RXBUF 512
136 #define ATH_TXBUF 512
137 #define ATH_TXBUF_RESERVE 5
138 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
139 #define ATH_TXMAXTRY 13
140 #define ATH_MGT_TXMAXTRY 4
142 #define TID_TO_WME_AC(_tid) \
143 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
144 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
145 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
148 #define ADDBA_EXCHANGE_ATTEMPTS 10
149 #define ATH_AGGR_DELIM_SZ 4
150 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
151 /* number of delimiters for encryption padding */
152 #define ATH_AGGR_ENCRYPTDELIM 10
153 /* minimum h/w qdepth to be sustained to maximize aggregation */
154 #define ATH_AGGR_MIN_QDEPTH 2
155 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
157 #define IEEE80211_SEQ_SEQ_SHIFT 4
158 #define IEEE80211_SEQ_MAX 4096
159 #define IEEE80211_WEP_IVLEN 3
160 #define IEEE80211_WEP_KIDLEN 1
161 #define IEEE80211_WEP_CRCLEN 4
162 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
163 (IEEE80211_WEP_IVLEN + \
164 IEEE80211_WEP_KIDLEN + \
165 IEEE80211_WEP_CRCLEN))
167 /* return whether a bit at index _n in bitmap _bm is set
168 * _sz is the size of the bitmap */
169 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
170 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
172 /* return block-ack bitmap index given sequence and starting sequence */
173 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
175 /* returns delimiter padding required given the packet length */
176 #define ATH_AGGR_GET_NDELIM(_len) \
177 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
178 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
180 #define BAW_WITHIN(_start, _bawsz, _seqno) \
181 ((((_seqno) - (_start)) & 4095) < (_bawsz))
183 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
185 #define ATH_TX_COMPLETE_POLL_INT 1000
187 enum ATH_AGGR_STATUS {
193 #define ATH_TXFIFO_DEPTH 8
197 struct list_head axq_q;
201 bool axq_tx_inprogress;
202 struct list_head axq_acq;
203 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
204 struct list_head txq_fifo_pending;
213 struct list_head list;
214 struct list_head tid_q;
217 struct ath_buf_state {
224 unsigned long bfs_paprd_timestamp;
226 enum ath9k_internal_frame_type bfs_ftype;
230 struct list_head list;
231 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
233 struct ath_buf *bf_next; /* next subframe in the aggregate */
234 struct sk_buff *bf_mpdu; /* enclosing frame structure */
235 void *bf_desc; /* virtual addr of desc */
236 dma_addr_t bf_daddr; /* physical addr of desc */
237 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
241 struct ath_buf_state bf_state;
242 struct ath_wiphy *aphy;
246 struct list_head list;
247 struct list_head buf_q;
249 struct ath_atx_ac *ac;
250 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
255 int baw_head; /* first un-acked tx buffer */
256 int baw_tail; /* next unused tx buffer slot */
263 struct ath_common *common;
264 struct ath_atx_tid tid[WME_NUM_TID];
265 struct ath_atx_ac ac[WME_NUM_AC];
270 #define AGGR_CLEANUP BIT(1)
271 #define AGGR_ADDBA_COMPLETE BIT(2)
272 #define AGGR_ADDBA_PROGRESS BIT(3)
274 struct ath_tx_control {
277 enum ath9k_internal_frame_type frame_type;
281 #define ATH_TX_ERROR 0x01
282 #define ATH_TX_XRETRY 0x02
283 #define ATH_TX_BAR 0x04
288 spinlock_t txbuflock;
289 struct list_head txbuf;
290 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
291 struct ath_descdma txdma;
292 struct ath_txq *txq_map[WME_NUM_AC];
296 struct sk_buff_head rx_fifo;
297 struct sk_buff_head rx_buffers;
305 unsigned int rxfilter;
306 spinlock_t rxbuflock;
307 struct list_head rxbuf;
308 struct ath_descdma rxdma;
309 struct ath_buf *rx_bufptr;
310 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
313 int ath_startrecv(struct ath_softc *sc);
314 bool ath_stoprecv(struct ath_softc *sc);
315 void ath_flushrecv(struct ath_softc *sc);
316 u32 ath_calcrxfilter(struct ath_softc *sc);
317 int ath_rx_init(struct ath_softc *sc, int nbufs);
318 void ath_rx_cleanup(struct ath_softc *sc);
319 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
320 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
321 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
322 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
323 void ath_draintxq(struct ath_softc *sc,
324 struct ath_txq *txq, bool retry_tx);
325 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
326 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
327 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
328 int ath_tx_init(struct ath_softc *sc, int nbufs);
329 void ath_tx_cleanup(struct ath_softc *sc);
330 int ath_txq_update(struct ath_softc *sc, int qnum,
331 struct ath9k_tx_queue_info *q);
332 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
333 struct ath_tx_control *txctl);
334 void ath_tx_tasklet(struct ath_softc *sc);
335 void ath_tx_edma_tasklet(struct ath_softc *sc);
336 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
337 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
339 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
340 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
348 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
349 enum nl80211_iftype av_opmode;
350 struct ath_buf *av_bcbuf;
351 struct ath_tx_control av_btxctl;
352 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
355 /*******************/
356 /* Beacon Handling */
357 /*******************/
360 * Regardless of the number of beacons we stagger, (i.e. regardless of the
361 * number of BSSIDs) if a given beacon does not go out even after waiting this
362 * number of beacon intervals, the game's up.
364 #define BSTUCK_THRESH (9 * ATH_BCBUF)
366 #define ATH_DEFAULT_BINTVAL 100 /* TU */
367 #define ATH_DEFAULT_BMISS_LIMIT 10
368 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
370 struct ath_beacon_config {
380 OK, /* no change needed */
381 UPDATE, /* update pending */
382 COMMIT /* beacon sent, commit change */
383 } updateslot; /* slot time update fsm */
389 struct ieee80211_vif *bslot[ATH_BCBUF];
390 struct ath_wiphy *bslot_aphy[ATH_BCBUF];
393 struct ath9k_tx_queue_info beacon_qi;
394 struct ath_descdma bdma;
395 struct ath_txq *cabq;
396 struct list_head bbuf;
399 void ath_beacon_tasklet(unsigned long data);
400 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
401 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
402 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
403 int ath_beaconq_config(struct ath_softc *sc);
409 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
410 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
411 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
412 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
413 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
414 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
415 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
417 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
419 void ath_hw_check(struct work_struct *work);
420 void ath_paprd_calibrate(struct work_struct *work);
421 void ath_ani_calibrate(unsigned long data);
428 bool hw_timer_enabled;
429 spinlock_t btcoex_lock;
430 struct timer_list period_timer; /* Timer for BT period */
432 unsigned long bt_priority_time;
433 int bt_stomp_type; /* Types of BT stomping */
434 u32 btcoex_no_stomp; /* in usec */
435 u32 btcoex_period; /* in usec */
436 u32 btscan_no_stomp; /* in usec */
437 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
440 int ath_init_btcoex_timer(struct ath_softc *sc);
441 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
442 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
444 /********************/
446 /********************/
448 #define ATH_LED_PIN_DEF 1
449 #define ATH_LED_PIN_9287 8
450 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
451 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
461 struct ath_softc *sc;
462 struct led_classdev led_cdev;
463 enum ath_led_type led_type;
468 void ath_init_leds(struct ath_softc *sc);
469 void ath_deinit_leds(struct ath_softc *sc);
471 /* Antenna diversity/combining */
472 #define ATH_ANT_RX_CURRENT_SHIFT 4
473 #define ATH_ANT_RX_MAIN_SHIFT 2
474 #define ATH_ANT_RX_MASK 0x3
476 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
477 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
478 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
479 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
480 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
481 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
482 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
484 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
485 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
486 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
487 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
488 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
490 enum ath9k_ant_div_comb_lna_conf {
491 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
492 ATH_ANT_DIV_COMB_LNA2,
493 ATH_ANT_DIV_COMB_LNA1,
494 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
497 struct ath_ant_comb {
516 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
517 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
522 unsigned long scan_start_time;
525 /********************/
526 /* Main driver core */
527 /********************/
530 * Default cache line size, in bytes.
531 * Used when PCI device not fully initialized by bootrom/BIOS
533 #define DEFAULT_CACHELINE 32
534 #define ATH_REGCLASSIDS_MAX 10
535 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
536 #define ATH_MAX_SW_RETRIES 10
537 #define ATH_CHAN_MAX 255
538 #define IEEE80211_WEP_NKID 4 /* number of key ids */
540 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
541 #define ATH_RATE_DUMMY_MARKER 0
543 #define SC_OP_INVALID BIT(0)
544 #define SC_OP_BEACONS BIT(1)
545 #define SC_OP_RXAGGR BIT(2)
546 #define SC_OP_TXAGGR BIT(3)
547 #define SC_OP_OFFCHANNEL BIT(4)
548 #define SC_OP_PREAMBLE_SHORT BIT(5)
549 #define SC_OP_PROTECT_ENABLE BIT(6)
550 #define SC_OP_RXFLUSH BIT(7)
551 #define SC_OP_LED_ASSOCIATED BIT(8)
552 #define SC_OP_LED_ON BIT(9)
553 #define SC_OP_TSF_RESET BIT(11)
554 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
555 #define SC_OP_BT_SCAN BIT(13)
556 #define SC_OP_ANI_RUN BIT(14)
558 /* Powersave flags */
559 #define PS_WAIT_FOR_BEACON BIT(0)
560 #define PS_WAIT_FOR_CAB BIT(1)
561 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
562 #define PS_WAIT_FOR_TX_ACK BIT(3)
563 #define PS_BEACON_SYNC BIT(4)
566 struct ath_rate_table;
569 struct ieee80211_hw *hw;
572 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
573 struct ath_wiphy *pri_wiphy;
574 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
575 * have NULL entries */
576 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
579 struct ath_wiphy *next_wiphy;
580 struct work_struct chan_work;
581 int wiphy_select_failures;
582 unsigned long wiphy_select_first_fail;
583 struct delayed_work wiphy_work;
584 unsigned long wiphy_scheduler_int;
585 int wiphy_scheduler_index;
586 struct survey_info *cur_survey;
587 struct survey_info survey[ATH9K_NUM_CHANNELS];
589 struct tasklet_struct intr_tq;
590 struct tasklet_struct bcon_tasklet;
591 struct ath_hw *sc_ah;
594 spinlock_t sc_serial_rw;
595 spinlock_t sc_pm_lock;
596 spinlock_t sc_pcu_lock;
598 struct work_struct paprd_work;
599 struct work_struct hw_check_work;
600 struct completion paprd_complete;
603 u32 sc_flags; /* SC_OP_* */
604 u16 ps_flags; /* PS_* */
610 unsigned long ps_usecount;
612 struct ath_config config;
615 struct ath_beacon beacon;
616 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
618 struct ath_led radio_led;
619 struct ath_led assoc_led;
620 struct ath_led tx_led;
621 struct ath_led rx_led;
622 struct delayed_work ath_led_blink_work;
624 int led_off_duration;
630 #ifdef CONFIG_ATH9K_DEBUGFS
631 struct ath9k_debug debug;
633 struct ath_beacon_config cur_beacon_conf;
634 struct delayed_work tx_complete_work;
635 struct ath_btcoex btcoex;
637 struct ath_descdma txsdma;
639 struct ath_ant_comb ant_comb;
643 struct ath_softc *sc; /* shared for all virtual wiphys */
644 struct ieee80211_hw *hw;
645 struct ath9k_hw_cal_data caldata;
646 enum ath_wiphy_state {
659 void ath9k_tasklet(unsigned long data);
660 int ath_reset(struct ath_softc *sc, bool retry_tx);
661 int ath_cabq_update(struct ath_softc *);
663 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
665 common->bus_ops->read_cachesize(common, csz);
668 extern struct ieee80211_ops ath9k_ops;
669 extern int modparam_nohwcrypt;
670 extern int led_blink;
672 irqreturn_t ath_isr(int irq, void *dev);
673 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
674 const struct ath_bus_ops *bus_ops);
675 void ath9k_deinit_device(struct ath_softc *sc);
676 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
677 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
678 struct ath9k_channel *ichan);
679 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
680 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
681 struct ath9k_channel *hchan);
683 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
684 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
685 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
688 int ath_pci_init(void);
689 void ath_pci_exit(void);
691 static inline int ath_pci_init(void) { return 0; };
692 static inline void ath_pci_exit(void) {};
695 #ifdef CONFIG_ATHEROS_AR71XX
696 int ath_ahb_init(void);
697 void ath_ahb_exit(void);
699 static inline int ath_ahb_init(void) { return 0; };
700 static inline void ath_ahb_exit(void) {};
703 void ath9k_ps_wakeup(struct ath_softc *sc);
704 void ath9k_ps_restore(struct ath_softc *sc);
706 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
707 int ath9k_wiphy_add(struct ath_softc *sc);
708 int ath9k_wiphy_del(struct ath_wiphy *aphy);
709 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
710 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
711 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
712 int ath9k_wiphy_select(struct ath_wiphy *aphy);
713 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
714 void ath9k_wiphy_chan_work(struct work_struct *work);
715 bool ath9k_wiphy_started(struct ath_softc *sc);
716 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
717 struct ath_wiphy *selected);
718 bool ath9k_wiphy_scanning(struct ath_softc *sc);
719 void ath9k_wiphy_work(struct work_struct *work);
720 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
721 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
723 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
724 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
726 void ath_start_rfkill_poll(struct ath_softc *sc);
727 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);