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[mv-sheeva.git] / drivers / net / wireless / ath / ath9k / btcoex.c
1 /*
2  * Copyright (c) 2009-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18
19 enum ath_bt_mode {
20         ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
21         ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
22         ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
23         ATH_BT_COEX_MODE_DISALBED,      /* coexistence disabled */
24 };
25
26 struct ath_btcoex_config {
27         u8 bt_time_extend;
28         bool bt_txstate_extend;
29         bool bt_txframe_extend;
30         enum ath_bt_mode bt_mode; /* coexistence mode */
31         bool bt_quiet_collision;
32         bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
33         u8 bt_priority_time;
34         u8 bt_first_slot_time;
35         bool bt_hold_rx_clear;
36 };
37
38
39 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
40 {
41         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
42         const struct ath_btcoex_config ath_bt_config = {
43                 .bt_time_extend = 0,
44                 .bt_txstate_extend = true,
45                 .bt_txframe_extend = true,
46                 .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
47                 .bt_quiet_collision = true,
48                 .bt_rxclear_polarity = true,
49                 .bt_priority_time = 2,
50                 .bt_first_slot_time = 5,
51                 .bt_hold_rx_clear = true,
52         };
53         u32 i;
54         bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
55
56         if (AR_SREV_9300_20_OR_LATER(ah))
57                 rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
58
59         btcoex_hw->bt_coex_mode =
60                 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
61                 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
62                 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
63                 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
64                 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
65                 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
66                 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
67                 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
68                 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
69                 SM(qnum, AR_BT_QCU_THRESH);
70
71         btcoex_hw->bt_coex_mode2 =
72                 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
73                 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
74                 AR_BT_DISABLE_BT_ANT;
75
76         for (i = 0; i < 32; i++)
77                 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
78 }
79 EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
80
81 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
82 {
83         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
84
85         /* connect bt_active to baseband */
86         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
87                     (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
88                      AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
89
90         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
91                     AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
92
93         /* Set input mux for bt_active to gpio pin */
94         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
95                       AR_GPIO_INPUT_MUX1_BT_ACTIVE,
96                       btcoex_hw->btactive_gpio);
97
98         /* Configure the desired gpio port for input */
99         ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
100 }
101 EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
102
103 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
104 {
105         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
106
107         /* btcoex 3-wire */
108         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
109                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
110                          AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
111
112         /* Set input mux for bt_prority_async and
113          *                  bt_active_async to GPIO pins */
114         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
115                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
116                         btcoex_hw->btactive_gpio);
117
118         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
119                         AR_GPIO_INPUT_MUX1_BT_PRIORITY,
120                         btcoex_hw->btpriority_gpio);
121
122         /* Configure the desired GPIO ports for input */
123
124         ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
125         ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
126 }
127 EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
128
129 static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
130 {
131         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
132
133         /* Configure the desired GPIO port for TX_FRAME output */
134         ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
135                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
136 }
137
138 void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
139                                 u32 bt_weight,
140                                 u32 wlan_weight)
141 {
142         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
143
144         btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
145                                      SM(wlan_weight, AR_BTCOEX_WL_WGHT);
146 }
147 EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
148
149
150 static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
151 {
152         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
153         u32  val;
154
155         /*
156          * Program coex mode and weight registers to
157          * enable coex 3-wire
158          */
159         REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
160         REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
161
162
163         if (AR_SREV_9300_20_OR_LATER(ah)) {
164                 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ah->bt_coex_wlan_weight[0]);
165                 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ah->bt_coex_wlan_weight[1]);
166                 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ah->bt_coex_bt_weight[0]);
167                 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ah->bt_coex_bt_weight[1]);
168                 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ah->bt_coex_bt_weight[2]);
169                 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ah->bt_coex_bt_weight[3]);
170
171         } else
172                 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
173
174
175
176         if (AR_SREV_9271(ah)) {
177                 val = REG_READ(ah, 0x50040);
178                 val &= 0xFFFFFEFF;
179                 REG_WRITE(ah, 0x50040, val);
180         }
181
182         REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
183         REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
184
185         ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
186                             AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
187 }
188
189 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
190 {
191         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
192
193         switch (btcoex_hw->scheme) {
194         case ATH_BTCOEX_CFG_NONE:
195                 break;
196         case ATH_BTCOEX_CFG_2WIRE:
197                 ath9k_hw_btcoex_enable_2wire(ah);
198                 break;
199         case ATH_BTCOEX_CFG_3WIRE:
200                 ath9k_hw_btcoex_enable_3wire(ah);
201                 break;
202         }
203
204         REG_RMW(ah, AR_GPIO_PDPU,
205                 (0x2 << (btcoex_hw->btactive_gpio * 2)),
206                 (0x3 << (btcoex_hw->btactive_gpio * 2)));
207
208         ah->btcoex_hw.enabled = true;
209 }
210 EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
211
212 void ath9k_hw_btcoex_disable(struct ath_hw *ah)
213 {
214         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
215
216         ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
217
218         ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
219                         AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
220
221         if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
222                 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
223                 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
224
225                 if (AR_SREV_9300_20_OR_LATER(ah)) {
226                         REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
227                         REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
228                         REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
229                         REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
230                         REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
231                         REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
232                 } else
233                         REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
234
235         }
236
237         ah->btcoex_hw.enabled = false;
238 }
239 EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
240
241 static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
242                          enum ath_stomp_type stomp_type)
243 {
244         ah->bt_coex_bt_weight[0] = AR9300_BT_WGHT;
245         ah->bt_coex_bt_weight[1] = AR9300_BT_WGHT;
246         ah->bt_coex_bt_weight[2] = AR9300_BT_WGHT;
247         ah->bt_coex_bt_weight[3] = AR9300_BT_WGHT;
248
249
250         switch (stomp_type) {
251         case ATH_BTCOEX_STOMP_ALL:
252                 ah->bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
253                 ah->bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
254                 break;
255         case ATH_BTCOEX_STOMP_LOW:
256                 ah->bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
257                 ah->bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
258                 break;
259         case ATH_BTCOEX_STOMP_NONE:
260                 ah->bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
261                 ah->bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
262                 break;
263
264         default:
265                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
266                                 "Invalid Stomptype\n");
267                 break;
268         }
269
270         ath9k_hw_btcoex_enable(ah);
271 }
272
273 /*
274  * Configures appropriate weight based on stomp type.
275  */
276 void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
277                               enum ath_stomp_type stomp_type)
278 {
279         if (AR_SREV_9300_20_OR_LATER(ah)) {
280                 ar9003_btcoex_bt_stomp(ah, stomp_type);
281                 return;
282         }
283
284         switch (stomp_type) {
285         case ATH_BTCOEX_STOMP_ALL:
286                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
287                                 AR_STOMP_ALL_WLAN_WGHT);
288                 break;
289         case ATH_BTCOEX_STOMP_LOW:
290                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
291                                 AR_STOMP_LOW_WLAN_WGHT);
292                 break;
293         case ATH_BTCOEX_STOMP_NONE:
294                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
295                                 AR_STOMP_NONE_WLAN_WGHT);
296                 break;
297         default:
298                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
299                                 "Invalid Stomptype\n");
300                 break;
301         }
302
303         ath9k_hw_btcoex_enable(ah);
304 }
305 EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);