2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /* We can tune this as we go by monitoring really low values */
20 #define ATH9K_NF_TOO_LOW -60
22 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
23 * is incorrect and we should use the static NF value. Later we can try to
24 * find out why they are reporting these values */
26 static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
28 if (nf > ATH9K_NF_TOO_LOW) {
29 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
30 "noise floor value detected (%d) is "
31 "lower than what we think is a "
32 "reasonable value (%d)\n",
33 nf, ATH9K_NF_TOO_LOW);
39 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
42 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
45 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
46 sort[i] = nfCalBuffer[i];
48 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
49 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
50 if (sort[j] > sort[j - 1]) {
52 sort[j] = sort[j - 1];
57 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
62 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
67 for (i = 0; i < NUM_NF_READINGS; i++) {
68 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
70 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
73 if (h[i].invalidNFcount > 0) {
74 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
75 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
76 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
78 h[i].invalidNFcount--;
79 h[i].privNF = nfarray[i];
83 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
89 static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS])
92 struct ath_common *common = ath9k_hw_common(ah);
95 if (AR_SREV_9280_10_OR_LATER(ah))
96 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
98 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
101 nf = 0 - ((nf ^ 0x1ff) + 1);
102 ath_print(common, ATH_DBG_CALIBRATE,
103 "NF calibrated [ctl] [chain 0] is %d\n", nf);
106 if (!AR_SREV_9285(ah)) {
107 if (AR_SREV_9280_10_OR_LATER(ah))
108 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
109 AR9280_PHY_CH1_MINCCA_PWR);
111 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
112 AR_PHY_CH1_MINCCA_PWR);
115 nf = 0 - ((nf ^ 0x1ff) + 1);
116 ath_print(common, ATH_DBG_CALIBRATE,
117 "NF calibrated [ctl] [chain 1] is %d\n", nf);
120 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
121 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
122 AR_PHY_CH2_MINCCA_PWR);
124 nf = 0 - ((nf ^ 0x1ff) + 1);
125 ath_print(common, ATH_DBG_CALIBRATE,
126 "NF calibrated [ctl] [chain 2] is %d\n", nf);
131 if (AR_SREV_9280_10_OR_LATER(ah))
132 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
133 AR9280_PHY_EXT_MINCCA_PWR);
135 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
136 AR_PHY_EXT_MINCCA_PWR);
139 nf = 0 - ((nf ^ 0x1ff) + 1);
140 ath_print(common, ATH_DBG_CALIBRATE,
141 "NF calibrated [ext] [chain 0] is %d\n", nf);
144 if (!AR_SREV_9285(ah)) {
145 if (AR_SREV_9280_10_OR_LATER(ah))
146 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
147 AR9280_PHY_CH1_EXT_MINCCA_PWR);
149 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
150 AR_PHY_CH1_EXT_MINCCA_PWR);
153 nf = 0 - ((nf ^ 0x1ff) + 1);
154 ath_print(common, ATH_DBG_CALIBRATE,
155 "NF calibrated [ext] [chain 1] is %d\n", nf);
158 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
159 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
160 AR_PHY_CH2_EXT_MINCCA_PWR);
162 nf = 0 - ((nf ^ 0x1ff) + 1);
163 ath_print(common, ATH_DBG_CALIBRATE,
164 "NF calibrated [ext] [chain 2] is %d\n", nf);
170 static bool getNoiseFloorThresh(struct ath_hw *ah,
171 enum ieee80211_band band,
175 case IEEE80211_BAND_5GHZ:
176 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
178 case IEEE80211_BAND_2GHZ:
179 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
189 static void ath9k_hw_setup_calibration(struct ath_hw *ah,
190 struct ath9k_cal_list *currCal)
192 struct ath_common *common = ath9k_hw_common(ah);
194 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
195 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
196 currCal->calData->calCountMax);
198 switch (currCal->calData->calType) {
199 case IQ_MISMATCH_CAL:
200 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
201 ath_print(common, ATH_DBG_CALIBRATE,
202 "starting IQ Mismatch Calibration\n");
205 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
206 ath_print(common, ATH_DBG_CALIBRATE,
207 "starting ADC Gain Calibration\n");
210 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
211 ath_print(common, ATH_DBG_CALIBRATE,
212 "starting ADC DC Calibration\n");
214 case ADC_DC_INIT_CAL:
215 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
216 ath_print(common, ATH_DBG_CALIBRATE,
217 "starting Init ADC DC Calibration\n");
221 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
222 AR_PHY_TIMING_CTRL4_DO_CAL);
225 static void ath9k_hw_reset_calibration(struct ath_hw *ah,
226 struct ath9k_cal_list *currCal)
230 ath9k_hw_setup_calibration(ah, currCal);
232 currCal->calState = CAL_RUNNING;
234 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
235 ah->meas0.sign[i] = 0;
236 ah->meas1.sign[i] = 0;
237 ah->meas2.sign[i] = 0;
238 ah->meas3.sign[i] = 0;
244 static bool ath9k_hw_per_calibration(struct ath_hw *ah,
245 struct ath9k_channel *ichan,
247 struct ath9k_cal_list *currCal)
249 bool iscaldone = false;
251 if (currCal->calState == CAL_RUNNING) {
252 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
253 AR_PHY_TIMING_CTRL4_DO_CAL)) {
255 currCal->calData->calCollect(ah);
258 if (ah->cal_samples >= currCal->calData->calNumSamples) {
259 int i, numChains = 0;
260 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
261 if (rxchainmask & (1 << i))
265 currCal->calData->calPostProc(ah, numChains);
266 ichan->CalValid |= currCal->calData->calType;
267 currCal->calState = CAL_DONE;
270 ath9k_hw_setup_calibration(ah, currCal);
273 } else if (!(ichan->CalValid & currCal->calData->calType)) {
274 ath9k_hw_reset_calibration(ah, currCal);
280 /* Assumes you are talking about the currently configured channel */
281 static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
282 enum ath9k_cal_types calType)
284 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
286 switch (calType & ah->supp_cals) {
287 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
291 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
299 static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
303 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
304 ah->totalPowerMeasI[i] +=
305 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
306 ah->totalPowerMeasQ[i] +=
307 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
308 ah->totalIqCorrMeas[i] +=
309 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
310 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
311 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
312 ah->cal_samples, i, ah->totalPowerMeasI[i],
313 ah->totalPowerMeasQ[i],
314 ah->totalIqCorrMeas[i]);
318 static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
322 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
323 ah->totalAdcIOddPhase[i] +=
324 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
325 ah->totalAdcIEvenPhase[i] +=
326 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
327 ah->totalAdcQOddPhase[i] +=
328 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
329 ah->totalAdcQEvenPhase[i] +=
330 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
332 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
333 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
334 "oddq=0x%08x; evenq=0x%08x;\n",
336 ah->totalAdcIOddPhase[i],
337 ah->totalAdcIEvenPhase[i],
338 ah->totalAdcQOddPhase[i],
339 ah->totalAdcQEvenPhase[i]);
343 static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
347 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
348 ah->totalAdcDcOffsetIOddPhase[i] +=
349 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
350 ah->totalAdcDcOffsetIEvenPhase[i] +=
351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
352 ah->totalAdcDcOffsetQOddPhase[i] +=
353 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
354 ah->totalAdcDcOffsetQEvenPhase[i] +=
355 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
357 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
358 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
359 "oddq=0x%08x; evenq=0x%08x;\n",
361 ah->totalAdcDcOffsetIOddPhase[i],
362 ah->totalAdcDcOffsetIEvenPhase[i],
363 ah->totalAdcDcOffsetQOddPhase[i],
364 ah->totalAdcDcOffsetQEvenPhase[i]);
368 static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
370 struct ath_common *common = ath9k_hw_common(ah);
371 u32 powerMeasQ, powerMeasI, iqCorrMeas;
372 u32 qCoffDenom, iCoffDenom;
373 int32_t qCoff, iCoff;
376 for (i = 0; i < numChains; i++) {
377 powerMeasI = ah->totalPowerMeasI[i];
378 powerMeasQ = ah->totalPowerMeasQ[i];
379 iqCorrMeas = ah->totalIqCorrMeas[i];
381 ath_print(common, ATH_DBG_CALIBRATE,
382 "Starting IQ Cal and Correction for Chain %d\n",
385 ath_print(common, ATH_DBG_CALIBRATE,
386 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
387 i, ah->totalIqCorrMeas[i]);
391 if (iqCorrMeas > 0x80000000) {
392 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
396 ath_print(common, ATH_DBG_CALIBRATE,
397 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
398 ath_print(common, ATH_DBG_CALIBRATE,
399 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
400 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
403 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
404 qCoffDenom = powerMeasQ / 64;
406 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
408 iCoff = iqCorrMeas / iCoffDenom;
409 qCoff = powerMeasI / qCoffDenom - 64;
410 ath_print(common, ATH_DBG_CALIBRATE,
411 "Chn %d iCoff = 0x%08x\n", i, iCoff);
412 ath_print(common, ATH_DBG_CALIBRATE,
413 "Chn %d qCoff = 0x%08x\n", i, qCoff);
415 iCoff = iCoff & 0x3f;
416 ath_print(common, ATH_DBG_CALIBRATE,
417 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
418 if (iqCorrNeg == 0x0)
419 iCoff = 0x40 - iCoff;
423 else if (qCoff <= -16)
426 ath_print(common, ATH_DBG_CALIBRATE,
427 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
430 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
431 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
433 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
434 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
436 ath_print(common, ATH_DBG_CALIBRATE,
437 "IQ Cal and Correction done for Chain %d\n",
442 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
443 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
446 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
448 struct ath_common *common = ath9k_hw_common(ah);
449 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
450 u32 qGainMismatch, iGainMismatch, val, i;
452 for (i = 0; i < numChains; i++) {
453 iOddMeasOffset = ah->totalAdcIOddPhase[i];
454 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
455 qOddMeasOffset = ah->totalAdcQOddPhase[i];
456 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
458 ath_print(common, ATH_DBG_CALIBRATE,
459 "Starting ADC Gain Cal for Chain %d\n", i);
461 ath_print(common, ATH_DBG_CALIBRATE,
462 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
464 ath_print(common, ATH_DBG_CALIBRATE,
465 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
467 ath_print(common, ATH_DBG_CALIBRATE,
468 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
470 ath_print(common, ATH_DBG_CALIBRATE,
471 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
474 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
476 ((iEvenMeasOffset * 32) /
477 iOddMeasOffset) & 0x3f;
479 ((qOddMeasOffset * 32) /
480 qEvenMeasOffset) & 0x3f;
482 ath_print(common, ATH_DBG_CALIBRATE,
483 "Chn %d gain_mismatch_i = 0x%08x\n", i,
485 ath_print(common, ATH_DBG_CALIBRATE,
486 "Chn %d gain_mismatch_q = 0x%08x\n", i,
489 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
491 val |= (qGainMismatch) | (iGainMismatch << 6);
492 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
494 ath_print(common, ATH_DBG_CALIBRATE,
495 "ADC Gain Cal done for Chain %d\n", i);
499 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
500 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
501 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
504 static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
506 struct ath_common *common = ath9k_hw_common(ah);
507 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
508 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
509 const struct ath9k_percal_data *calData =
510 ah->cal_list_curr->calData;
512 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
514 for (i = 0; i < numChains; i++) {
515 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
516 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
517 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
518 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
520 ath_print(common, ATH_DBG_CALIBRATE,
521 "Starting ADC DC Offset Cal for Chain %d\n", i);
523 ath_print(common, ATH_DBG_CALIBRATE,
524 "Chn %d pwr_meas_odd_i = %d\n", i,
526 ath_print(common, ATH_DBG_CALIBRATE,
527 "Chn %d pwr_meas_even_i = %d\n", i,
529 ath_print(common, ATH_DBG_CALIBRATE,
530 "Chn %d pwr_meas_odd_q = %d\n", i,
532 ath_print(common, ATH_DBG_CALIBRATE,
533 "Chn %d pwr_meas_even_q = %d\n", i,
536 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
538 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
541 ath_print(common, ATH_DBG_CALIBRATE,
542 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
544 ath_print(common, ATH_DBG_CALIBRATE,
545 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
548 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
550 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
551 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
553 ath_print(common, ATH_DBG_CALIBRATE,
554 "ADC DC Offset Cal done for Chain %d\n", i);
557 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
558 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
559 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
562 /* This is done for the currently configured channel */
563 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
565 struct ath_common *common = ath9k_hw_common(ah);
566 struct ieee80211_conf *conf = &common->hw->conf;
567 struct ath9k_cal_list *currCal = ah->cal_list_curr;
572 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
578 if (currCal->calState != CAL_DONE) {
579 ath_print(common, ATH_DBG_CALIBRATE,
580 "Calibration state incorrect, %d\n",
585 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
588 ath_print(common, ATH_DBG_CALIBRATE,
589 "Resetting Cal %d state for channel %u\n",
590 currCal->calData->calType, conf->channel->center_freq);
592 ah->curchan->CalValid &= ~currCal->calData->calType;
593 currCal->calState = CAL_WAITING;
597 EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
599 void ath9k_hw_start_nfcal(struct ath_hw *ah)
601 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
602 AR_PHY_AGC_CONTROL_ENABLE_NF);
603 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
604 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
605 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
608 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
610 struct ath9k_nfcal_hist *h;
613 const u32 ar5416_cca_regs[6] = {
621 u8 chainmask, rx_chain_status;
623 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
624 if (AR_SREV_9285(ah))
626 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
627 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
632 if (rx_chain_status & 0x4)
634 else if (rx_chain_status & 0x2)
642 for (i = 0; i < NUM_NF_READINGS; i++) {
643 if (chainmask & (1 << i)) {
644 val = REG_READ(ah, ar5416_cca_regs[i]);
646 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
647 REG_WRITE(ah, ar5416_cca_regs[i], val);
651 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
652 AR_PHY_AGC_CONTROL_ENABLE_NF);
653 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
654 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
655 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
657 for (j = 0; j < 5; j++) {
658 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
659 AR_PHY_AGC_CONTROL_NF) == 0)
664 for (i = 0; i < NUM_NF_READINGS; i++) {
665 if (chainmask & (1 << i)) {
666 val = REG_READ(ah, ar5416_cca_regs[i]);
668 val |= (((u32) (-50) << 1) & 0x1ff);
669 REG_WRITE(ah, ar5416_cca_regs[i], val);
674 int16_t ath9k_hw_getnf(struct ath_hw *ah,
675 struct ath9k_channel *chan)
677 struct ath_common *common = ath9k_hw_common(ah);
678 int16_t nf, nfThresh;
679 int16_t nfarray[NUM_NF_READINGS] = { 0 };
680 struct ath9k_nfcal_hist *h;
681 struct ieee80211_channel *c = chan->chan;
683 chan->channelFlags &= (~CHANNEL_CW_INT);
684 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
685 ath_print(common, ATH_DBG_CALIBRATE,
686 "NF did not complete in calibration window\n");
688 chan->rawNoiseFloor = nf;
689 return chan->rawNoiseFloor;
691 ath9k_hw_do_getnf(ah, nfarray);
693 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
695 ath_print(common, ATH_DBG_CALIBRATE,
696 "noise floor failed detected; "
697 "detected %d, threshold %d\n",
699 chan->channelFlags |= CHANNEL_CW_INT;
705 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
706 chan->rawNoiseFloor = h[0].privNF;
708 return chan->rawNoiseFloor;
711 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
716 if (AR_SREV_9280(ah))
717 noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
718 else if (AR_SREV_9285(ah))
719 noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
720 else if (AR_SREV_9287(ah))
721 noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
723 noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
725 for (i = 0; i < NUM_NF_READINGS; i++) {
726 ah->nfCalHist[i].currIndex = 0;
727 ah->nfCalHist[i].privNF = noise_floor;
728 ah->nfCalHist[i].invalidNFcount =
729 AR_PHY_CCA_FILTERWINDOW_LENGTH;
730 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
731 ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
736 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
740 if (chan->rawNoiseFloor == 0)
743 nf = chan->rawNoiseFloor;
745 if (!ath9k_hw_nf_in_range(ah, nf))
746 nf = ATH_DEFAULT_NOISE_FLOOR;
750 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
752 static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
755 int32_t delta, currPDADC, slope;
757 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
758 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
760 if (ah->initPDADC == 0 || currPDADC == 0) {
762 * Zero value indicates that no frames have been transmitted yet,
763 * can't do temperature compensation until frames are transmitted.
767 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
769 if (slope == 0) { /* to avoid divide by zero case */
772 delta = ((currPDADC - ah->initPDADC)*4) / slope;
774 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
775 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
776 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
777 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
781 static void ath9k_olc_temp_compensation(struct ath_hw *ah)
784 int delta, currPDADC, regval;
786 if (OLC_FOR_AR9287_10_LATER) {
787 ath9k_olc_temp_compensation_9287(ah);
789 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
790 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
792 if (ah->initPDADC == 0 || currPDADC == 0) {
795 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
796 delta = (currPDADC - ah->initPDADC + 4) / 8;
798 delta = (currPDADC - ah->initPDADC + 5) / 10;
800 if (delta != ah->PDADCdelta) {
801 ah->PDADCdelta = delta;
802 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
803 regval = ah->originalGain[i] - delta;
808 AR_PHY_TX_GAIN_TBL1 + i * 4,
809 AR_PHY_TX_GAIN, regval);
816 static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
820 u32 regList [][2] = {
831 for (i = 0; i < ARRAY_SIZE(regList); i++)
832 regList[i][1] = REG_READ(ah, regList[i][0]);
834 regVal = REG_READ(ah, 0x7834);
836 REG_WRITE(ah, 0x7834, regVal);
837 regVal = REG_READ(ah, 0x9808);
838 regVal |= (0x1 << 27);
839 REG_WRITE(ah, 0x9808, regVal);
841 /* 786c,b23,1, pwddac=1 */
842 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
843 /* 7854, b5,1, pdrxtxbb=1 */
844 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
845 /* 7854, b7,1, pdv2i=1 */
846 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
847 /* 7854, b8,1, pddacinterface=1 */
848 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
849 /* 7824,b12,0, offcal=0 */
850 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
851 /* 7838, b1,0, pwddb=0 */
852 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
853 /* 7820,b11,0, enpacal=0 */
854 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
855 /* 7820,b25,1, pdpadrv1=0 */
856 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
857 /* 7820,b24,0, pdpadrv2=0 */
858 REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
859 /* 7820,b23,0, pdpaout=0 */
860 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
861 /* 783c,b14-16,7, padrvgn2tab_0=7 */
862 REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
864 * 7838,b29-31,0, padrvgn1tab_0=0
865 * does not matter since we turn it off
867 REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
869 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
872 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
873 * txon=1,paon=1,oscon=1,synthon_force=1
875 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
880 for (i = 6; i >= 0; i--) {
881 regVal = REG_READ(ah, 0x7834);
882 regVal |= (1 << (20 + i));
883 REG_WRITE(ah, 0x7834, regVal);
885 //regVal = REG_READ(ah, 0x7834);
886 regVal &= (~(0x1 << (20 + i)));
887 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
889 REG_WRITE(ah, 0x7834, regVal);
892 /* Empirical offset correction */
894 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0x20);
897 regVal = REG_READ(ah, 0x7834);
899 REG_WRITE(ah, 0x7834, regVal);
900 regVal = REG_READ(ah, 0x9808);
901 regVal &= (~(0x1 << 27));
902 REG_WRITE(ah, 0x9808, regVal);
904 for (i = 0; i < ARRAY_SIZE(regList); i++)
905 REG_WRITE(ah, regList[i][0], regList[i][1]);
908 static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
910 struct ath_common *common = ath9k_hw_common(ah);
912 int i, offset, offs_6_1, offs_0;
913 u32 ccomp_org, reg_field;
924 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
926 /* PA CAL is not needed for high power solution */
927 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
928 AR5416_EEP_TXGAIN_HIGH_POWER)
931 if (AR_SREV_9285_11(ah)) {
932 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
936 for (i = 0; i < ARRAY_SIZE(regList); i++)
937 regList[i][1] = REG_READ(ah, regList[i][0]);
939 regVal = REG_READ(ah, 0x7834);
941 REG_WRITE(ah, 0x7834, regVal);
942 regVal = REG_READ(ah, 0x9808);
943 regVal |= (0x1 << 27);
944 REG_WRITE(ah, 0x9808, regVal);
946 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
947 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
948 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
949 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
950 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
951 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
952 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
953 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
954 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
955 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
956 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
957 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
958 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
959 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
961 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
963 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
964 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
966 for (i = 6; i > 0; i--) {
967 regVal = REG_READ(ah, 0x7834);
968 regVal |= (1 << (19 + i));
969 REG_WRITE(ah, 0x7834, regVal);
971 regVal = REG_READ(ah, 0x7834);
972 regVal &= (~(0x1 << (19 + i)));
973 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
974 regVal |= (reg_field << (19 + i));
975 REG_WRITE(ah, 0x7834, regVal);
978 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
980 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
981 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
982 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
983 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
985 offset = (offs_6_1<<1) | offs_0;
987 offs_6_1 = offset>>1;
990 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
991 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
992 ah->pacal_info.max_skipcount =
993 2 * ah->pacal_info.max_skipcount;
994 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
996 ah->pacal_info.max_skipcount = 1;
997 ah->pacal_info.skipcount = 0;
998 ah->pacal_info.prev_offset = offset;
1001 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
1002 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
1004 regVal = REG_READ(ah, 0x7834);
1006 REG_WRITE(ah, 0x7834, regVal);
1007 regVal = REG_READ(ah, 0x9808);
1008 regVal &= (~(0x1 << 27));
1009 REG_WRITE(ah, 0x9808, regVal);
1011 for (i = 0; i < ARRAY_SIZE(regList); i++)
1012 REG_WRITE(ah, regList[i][0], regList[i][1]);
1014 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
1016 if (AR_SREV_9285_11(ah))
1017 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1021 bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1022 u8 rxchainmask, bool longcal)
1024 bool iscaldone = true;
1025 struct ath9k_cal_list *currCal = ah->cal_list_curr;
1028 (currCal->calState == CAL_RUNNING ||
1029 currCal->calState == CAL_WAITING)) {
1030 iscaldone = ath9k_hw_per_calibration(ah, chan,
1031 rxchainmask, currCal);
1033 ah->cal_list_curr = currCal = currCal->calNext;
1035 if (currCal->calState == CAL_WAITING) {
1037 ath9k_hw_reset_calibration(ah, currCal);
1042 /* Do NF cal only at longer intervals */
1044 /* Do periodic PAOffset Cal */
1045 if (AR_SREV_9271(ah))
1046 ath9k_hw_9271_pa_cal(ah);
1047 else if (AR_SREV_9285_11_OR_LATER(ah)) {
1048 if (!ah->pacal_info.skipcount)
1049 ath9k_hw_9285_pa_cal(ah, false);
1051 ah->pacal_info.skipcount--;
1054 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
1055 ath9k_olc_temp_compensation(ah);
1057 /* Get the value from the previous NF cal and update history buffer */
1058 ath9k_hw_getnf(ah, chan);
1061 * Load the NF from history buffer of the current channel.
1062 * NF is slow time-variant, so it is OK to use a historical value.
1064 ath9k_hw_loadnf(ah, ah->curchan);
1066 ath9k_hw_start_nfcal(ah);
1071 EXPORT_SYMBOL(ath9k_hw_calibrate);
1073 static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1075 struct ath_common *common = ath9k_hw_common(ah);
1077 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1078 if (IS_CHAN_HT20(chan)) {
1079 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1080 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1081 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1082 AR_PHY_AGC_CONTROL_FLTR_CAL);
1083 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1084 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1085 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1086 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1087 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1088 "calibration failed to complete in "
1092 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1093 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1094 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1096 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1097 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1098 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1099 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1100 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1101 0, AH_WAIT_TIMEOUT)) {
1102 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1103 "failed to complete in 1ms; noisy ??\n");
1107 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1108 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1109 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1114 bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1116 struct ath_common *common = ath9k_hw_common(ah);
1118 if (AR_SREV_9285_12_OR_LATER(ah)) {
1119 if (!ar9285_clc(ah, chan))
1122 if (AR_SREV_9280_10_OR_LATER(ah)) {
1123 if (!AR_SREV_9287_10_OR_LATER(ah))
1124 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1125 AR_PHY_ADC_CTL_OFF_PWDADC);
1126 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1127 AR_PHY_AGC_CONTROL_FLTR_CAL);
1130 /* Calibrate the AGC */
1131 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1132 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1133 AR_PHY_AGC_CONTROL_CAL);
1135 /* Poll for offset calibration complete */
1136 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1137 0, AH_WAIT_TIMEOUT)) {
1138 ath_print(common, ATH_DBG_CALIBRATE,
1139 "offset calibration failed to "
1140 "complete in 1ms; noisy environment?\n");
1144 if (AR_SREV_9280_10_OR_LATER(ah)) {
1145 if (!AR_SREV_9287_10_OR_LATER(ah))
1146 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1147 AR_PHY_ADC_CTL_OFF_PWDADC);
1148 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1149 AR_PHY_AGC_CONTROL_FLTR_CAL);
1153 /* Do PA Calibration */
1154 if (AR_SREV_9285_11_OR_LATER(ah))
1155 ath9k_hw_9285_pa_cal(ah, true);
1157 /* Do NF Calibration after DC offset and other calibrations */
1158 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1159 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
1161 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1163 /* Enable IQ, ADC Gain and ADC DC offset CALs */
1164 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
1165 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1166 INIT_CAL(&ah->adcgain_caldata);
1167 INSERT_CAL(ah, &ah->adcgain_caldata);
1168 ath_print(common, ATH_DBG_CALIBRATE,
1169 "enabling ADC Gain Calibration.\n");
1171 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1172 INIT_CAL(&ah->adcdc_caldata);
1173 INSERT_CAL(ah, &ah->adcdc_caldata);
1174 ath_print(common, ATH_DBG_CALIBRATE,
1175 "enabling ADC DC Calibration.\n");
1177 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1178 INIT_CAL(&ah->iq_caldata);
1179 INSERT_CAL(ah, &ah->iq_caldata);
1180 ath_print(common, ATH_DBG_CALIBRATE,
1181 "enabling IQ Calibration.\n");
1184 ah->cal_list_curr = ah->cal_list;
1186 if (ah->cal_list_curr)
1187 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1195 const struct ath9k_percal_data iq_cal_multi_sample = {
1199 ath9k_hw_iqcal_collect,
1200 ath9k_hw_iqcalibrate
1202 const struct ath9k_percal_data iq_cal_single_sample = {
1206 ath9k_hw_iqcal_collect,
1207 ath9k_hw_iqcalibrate
1209 const struct ath9k_percal_data adc_gain_cal_multi_sample = {
1213 ath9k_hw_adc_gaincal_collect,
1214 ath9k_hw_adc_gaincal_calibrate
1216 const struct ath9k_percal_data adc_gain_cal_single_sample = {
1220 ath9k_hw_adc_gaincal_collect,
1221 ath9k_hw_adc_gaincal_calibrate
1223 const struct ath9k_percal_data adc_dc_cal_multi_sample = {
1227 ath9k_hw_adc_dccal_collect,
1228 ath9k_hw_adc_dccal_calibrate
1230 const struct ath9k_percal_data adc_dc_cal_single_sample = {
1234 ath9k_hw_adc_dccal_collect,
1235 ath9k_hw_adc_dccal_calibrate
1237 const struct ath9k_percal_data adc_init_dc_cal = {
1241 ath9k_hw_adc_dccal_collect,
1242 ath9k_hw_adc_dccal_calibrate