2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define AR_EEPROM_MODAL_SPURS 5
23 #include <net/cfg80211.h>
24 #include "ar9003_eeprom.h"
27 #define AR5416_EEPROM_MAGIC 0x5aa5
29 #define AR5416_EEPROM_MAGIC 0xa55a
32 #define CTRY_DEBUG 0x1ff
33 #define CTRY_DEFAULT 0
35 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
36 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
37 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
38 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
39 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
40 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
41 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
42 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
43 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
45 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
46 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
47 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
48 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
49 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
50 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
53 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
55 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
56 #define AR5416_EEPROM_S 2
57 #define AR5416_EEPROM_OFFSET 0x2000
58 #define AR5416_EEPROM_MAX 0xae0
60 #define AR5416_EEPROM_START_ADDR \
61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
63 #define SD_NO_CTL 0xE0
65 #define CTL_MODE_M 0xf
74 #define EXT_ADDITIVE (0x8000)
75 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
76 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
77 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
79 #define SUB_NUM_CTL_MODES_AT_5G_40 2
80 #define SUB_NUM_CTL_MODES_AT_2G_40 3
82 #define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */
83 #define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */
86 * For AR9285 and later chipsets, the following bits are not being programmed
87 * in EEPROM and so need to be enabled always.
91 * Bit 2: en_fcc_dfs_ht40
93 * Bit 4: en_jap_dfs_ht40
95 #define AR9285_RDEXT_DEFAULT 0x1F
97 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
100 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
102 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
103 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
104 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
105 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
106 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
108 #define EEP_RFSILENT_ENABLED 0x0001
109 #define EEP_RFSILENT_ENABLED_S 0
110 #define EEP_RFSILENT_POLARITY 0x0002
111 #define EEP_RFSILENT_POLARITY_S 1
112 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
113 #define EEP_RFSILENT_GPIO_SEL_S 2
115 #define AR5416_OPFLAGS_11A 0x01
116 #define AR5416_OPFLAGS_11G 0x02
117 #define AR5416_OPFLAGS_N_5G_HT40 0x04
118 #define AR5416_OPFLAGS_N_2G_HT40 0x08
119 #define AR5416_OPFLAGS_N_5G_HT20 0x10
120 #define AR5416_OPFLAGS_N_2G_HT20 0x20
122 #define AR5416_EEP_NO_BACK_VER 0x1
123 #define AR5416_EEP_VER 0xE
124 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
125 #define AR5416_EEP_MINOR_VER_2 0x2
126 #define AR5416_EEP_MINOR_VER_3 0x3
127 #define AR5416_EEP_MINOR_VER_7 0x7
128 #define AR5416_EEP_MINOR_VER_9 0x9
129 #define AR5416_EEP_MINOR_VER_16 0x10
130 #define AR5416_EEP_MINOR_VER_17 0x11
131 #define AR5416_EEP_MINOR_VER_19 0x13
132 #define AR5416_EEP_MINOR_VER_20 0x14
133 #define AR5416_EEP_MINOR_VER_21 0x15
134 #define AR5416_EEP_MINOR_VER_22 0x16
136 #define AR5416_NUM_5G_CAL_PIERS 8
137 #define AR5416_NUM_2G_CAL_PIERS 4
138 #define AR5416_NUM_5G_20_TARGET_POWERS 8
139 #define AR5416_NUM_5G_40_TARGET_POWERS 8
140 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
141 #define AR5416_NUM_2G_20_TARGET_POWERS 4
142 #define AR5416_NUM_2G_40_TARGET_POWERS 4
143 #define AR5416_NUM_CTLS 24
144 #define AR5416_NUM_BAND_EDGES 8
145 #define AR5416_NUM_PD_GAINS 4
146 #define AR5416_PD_GAINS_IN_MASK 4
147 #define AR5416_PD_GAIN_ICEPTS 5
148 #define AR5416_NUM_PDADC_VALUES 128
149 #define AR5416_BCHAN_UNUSED 0xFF
150 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
151 #define AR5416_MAX_CHAINS 3
152 #define AR9300_MAX_CHAINS 3
153 #define AR5416_PWR_TABLE_OFFSET_DB -5
155 /* Rx gain type values */
156 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
157 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
158 #define AR5416_EEP_RXGAIN_ORIG 2
160 /* Tx gain type values */
161 #define AR5416_EEP_TXGAIN_ORIGINAL 0
162 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
164 /* Endianness of EEPROM content */
165 #define AR5416_EEPMISC_BIG_ENDIAN 0x01
167 #define AR5416_EEP4K_START_LOC 64
168 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
169 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
170 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
171 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
172 #define AR5416_EEP4K_NUM_CTLS 12
173 #define AR5416_EEP4K_NUM_BAND_EDGES 4
174 #define AR5416_EEP4K_NUM_PD_GAINS 2
175 #define AR5416_EEP4K_MAX_CHAINS 1
177 #define AR9280_TX_GAIN_TABLE_SIZE 22
179 #define AR9287_EEP_VER 0xE
180 #define AR9287_EEP_VER_MINOR_MASK 0xFFF
181 #define AR9287_EEP_MINOR_VER_1 0x1
182 #define AR9287_EEP_MINOR_VER_2 0x2
183 #define AR9287_EEP_MINOR_VER_3 0x3
184 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
185 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
186 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
188 #define AR9287_EEP_START_LOC 128
189 #define AR9287_HTC_EEP_START_LOC 256
190 #define AR9287_NUM_2G_CAL_PIERS 3
191 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
192 #define AR9287_NUM_2G_20_TARGET_POWERS 3
193 #define AR9287_NUM_2G_40_TARGET_POWERS 3
194 #define AR9287_NUM_CTLS 12
195 #define AR9287_NUM_BAND_EDGES 4
196 #define AR9287_PD_GAIN_ICEPTS 1
197 #define AR9287_EEPMISC_WOW 0x02
198 #define AR9287_MAX_CHAINS 2
199 #define AR9287_ANT_16S 32
201 #define AR9287_DATA_SZ 32
203 #define AR9287_PWR_TABLE_OFFSET_DB -5
205 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
207 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
208 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
210 #define LNA_CTL_BUF_MODE BIT(0)
211 #define LNA_CTL_ISEL_LO BIT(1)
212 #define LNA_CTL_ISEL_HI BIT(2)
213 #define LNA_CTL_BUF_IN BIT(3)
214 #define LNA_CTL_FEM_BAND BIT(4)
215 #define LNA_CTL_LOCAL_BIAS BIT(5)
216 #define LNA_CTL_FORCE_XPA BIT(6)
217 #define LNA_CTL_USE_ANT1 BIT(7)
245 EEP_TEMPSENSE_SLOPE_PAL_ON,
246 EEP_PWR_TABLE_OFFSET,
250 EEP_CHAIN_MASK_REDUCE,
256 rate6mb, rate9mb, rate12mb, rate18mb,
257 rate24mb, rate36mb, rate48mb, rate54mb,
258 rate1l, rate2l, rate2s, rate5_5l,
259 rate5_5s, rate11l, rate11s, rateXr,
260 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
261 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
262 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
263 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
264 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
268 enum ath9k_hal_freq_band {
269 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
270 ATH9K_HAL_FREQ_BAND_2GHZ = 1
273 struct base_eep_header {
284 u16 blueToothOptions;
303 struct base_eep_header_4k {
314 u16 blueToothOptions;
328 struct modal_eep_header {
329 u32 antCtrlChain[AR5416_MAX_CHAINS];
331 u8 antennaGainCh[AR5416_MAX_CHAINS];
333 u8 txRxAttenCh[AR5416_MAX_CHAINS];
334 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
337 u8 xlnaGainCh[AR5416_MAX_CHAINS];
342 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
345 u8 iqCalICh[AR5416_MAX_CHAINS];
346 u8 iqCalQCh[AR5416_MAX_CHAINS];
351 u8 pwrDecreaseFor2Chain;
352 u8 pwrDecreaseFor3Chain;
353 u8 txFrameToDataStart;
355 u8 ht40PowerIncForPdadc;
356 u8 bswAtten[AR5416_MAX_CHAINS];
357 u8 bswMargin[AR5416_MAX_CHAINS];
359 u8 xatten2Db[AR5416_MAX_CHAINS];
360 u8 xatten2Margin[AR5416_MAX_CHAINS];
365 u16 xpaBiasLvlFreq[3];
368 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
371 struct calDataPerFreqOpLoop {
378 struct modal_eep_4k_header {
379 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
381 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
383 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
384 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
387 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
392 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
395 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
396 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
398 #ifdef __BIG_ENDIAN_BITFIELD
406 u8 txFrameToDataStart;
408 u8 ht40PowerIncForPdadc;
409 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
410 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
412 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
413 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
414 #ifdef __BIG_ENDIAN_BITFIELD
420 #ifdef __BIG_ENDIAN_BITFIELD
422 u8 antdiv_ctl1:4, ob_4:4;
424 u8 antdiv_ctl2:4, db1_4:4;
426 u8 reserved:4, db2_4:4;
429 u8 ob_4:4, antdiv_ctl1:4;
431 u8 db1_4:4, antdiv_ctl2:4;
433 u8 db2_4:4, reserved:4;
437 u8 bb_scale_smrt_antenna;
438 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
440 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
443 struct base_eep_ar9287_header {
454 u16 blueToothOptions;
459 int8_t pwrTableOffset;
460 int8_t tempSensSlope;
461 int8_t tempSensSlopePalOn;
465 struct modal_eep_ar9287_header {
466 u32 antCtrlChain[AR9287_MAX_CHAINS];
468 int8_t antennaGainCh[AR9287_MAX_CHAINS];
470 u8 txRxAttenCh[AR9287_MAX_CHAINS];
471 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
472 int8_t adcDesiredSize;
477 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
480 int8_t iqCalICh[AR9287_MAX_CHAINS];
481 int8_t iqCalQCh[AR9287_MAX_CHAINS];
484 u8 txFrameToDataStart;
486 u8 ht40PowerIncForPdadc;
487 u8 bswAtten[AR9287_MAX_CHAINS];
488 u8 bswMargin[AR9287_MAX_CHAINS];
498 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
501 struct cal_data_per_freq {
502 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
503 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
506 struct cal_data_per_freq_4k {
507 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
508 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
511 struct cal_target_power_leg {
516 struct cal_target_power_ht {
521 struct cal_ctl_edges {
526 struct cal_data_op_loop_ar9287 {
533 struct cal_data_per_freq_ar9287 {
534 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
535 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
538 union cal_data_per_freq_ar9287_u {
539 struct cal_data_op_loop_ar9287 calDataOpen;
540 struct cal_data_per_freq_ar9287 calDataClose;
543 struct cal_ctl_data_ar9287 {
545 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
548 struct cal_ctl_data {
550 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
553 struct cal_ctl_data_4k {
555 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
558 struct ar5416_eeprom_def {
559 struct base_eep_header baseEepHeader;
561 struct modal_eep_header modalHeader[2];
562 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
563 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
564 struct cal_data_per_freq
565 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
566 struct cal_data_per_freq
567 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
568 struct cal_target_power_leg
569 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
570 struct cal_target_power_ht
571 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
572 struct cal_target_power_ht
573 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
574 struct cal_target_power_leg
575 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
576 struct cal_target_power_leg
577 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
578 struct cal_target_power_ht
579 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
580 struct cal_target_power_ht
581 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
582 u8 ctlIndex[AR5416_NUM_CTLS];
583 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
587 struct ar5416_eeprom_4k {
588 struct base_eep_header_4k baseEepHeader;
590 struct modal_eep_4k_header modalHeader;
591 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
592 struct cal_data_per_freq_4k
593 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
594 struct cal_target_power_leg
595 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
596 struct cal_target_power_leg
597 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
598 struct cal_target_power_ht
599 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
600 struct cal_target_power_ht
601 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
602 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
603 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
607 struct ar9287_eeprom {
608 struct base_eep_ar9287_header baseEepHeader;
609 u8 custData[AR9287_DATA_SZ];
610 struct modal_eep_ar9287_header modalHeader;
611 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
612 union cal_data_per_freq_ar9287_u
613 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
614 struct cal_target_power_leg
615 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
616 struct cal_target_power_leg
617 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
618 struct cal_target_power_ht
619 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
620 struct cal_target_power_ht
621 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
622 u8 ctlIndex[AR9287_NUM_CTLS];
623 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
627 enum reg_ext_bitmap {
628 REG_EXT_FCC_MIDBAND = 0,
629 REG_EXT_JAPAN_MIDBAND = 1,
630 REG_EXT_FCC_DFS_HT40 = 2,
631 REG_EXT_JAPAN_NONDFS_HT40 = 3,
632 REG_EXT_JAPAN_DFS_HT40 = 4
635 struct ath9k_country_entry {
645 int (*check_eeprom)(struct ath_hw *hw);
646 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
647 bool (*fill_eeprom)(struct ath_hw *hw);
648 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
650 int (*get_eeprom_ver)(struct ath_hw *hw);
651 int (*get_eeprom_rev)(struct ath_hw *hw);
652 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
653 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
654 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
655 u16 cfgCtl, u8 twiceAntennaReduction,
656 u8 powerLimit, bool test);
657 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
658 u8 (*get_eepmisc)(struct ath_hw *ah);
661 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
662 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
664 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
666 int16_t targetRight);
667 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
668 u16 *indexL, u16 *indexR);
669 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data);
670 int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size);
671 bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size);
672 bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev);
673 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
674 int eep_start_loc, int size);
675 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
676 u8 *pVpdList, u16 numIntercepts,
678 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
679 struct ath9k_channel *chan,
680 struct cal_target_power_leg *powInfo,
682 struct cal_target_power_leg *pNewPower,
683 u16 numRates, bool isExtTarget);
684 void ath9k_hw_get_target_powers(struct ath_hw *ah,
685 struct ath9k_channel *chan,
686 struct cal_target_power_ht *powInfo,
688 struct cal_target_power_ht *pNewPower,
689 u16 numRates, bool isHt40Target);
690 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
691 bool is2GHz, int num_band_edges);
692 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
693 u8 antenna_reduction);
694 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
695 int ath9k_hw_eeprom_init(struct ath_hw *ah);
697 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
698 struct ath9k_channel *chan,
700 u8 *bChans, u16 availPiers,
702 u16 *pPdGainBoundaries, u8 *pPDADCValues,
705 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
707 if (fbin == AR5416_BCHAN_UNUSED)
710 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
713 #define ar5416_get_ntxchains(_txchainmask) \
714 (((_txchainmask >> 2) & 1) + \
715 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
717 extern const struct eeprom_ops eep_def_ops;
718 extern const struct eeprom_ops eep_4k_ops;
719 extern const struct eeprom_ops eep_ar9287_ops;
720 extern const struct eeprom_ops eep_ar9287_ops;
721 extern const struct eeprom_ops eep_ar9300_ops;
723 #endif /* EEPROM_H */