drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  21 {
  22         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  23 }
  24
  25 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  26 {
  27         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  28 }
  29
  30 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  31 {
  32 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  33         struct ath_common *common = ath9k_hw_common(ah);
  34         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  35         int addr, eep_start_loc = 0;
  36
  37         eep_start_loc = 64;
  38
  39         if (!ath9k_hw_use_flash(ah)) {
  40                 ath_print(common, ATH_DBG_EEPROM,
  41                           "Reading from EEPROM, not flash\n");
  42         }
  43
  44         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  45                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  46                         ath_print(common, ATH_DBG_EEPROM,
  47                                   "Unable to read eeprom region\n");
  48                         return false;
  49                 }
  50                 eep_data++;
  51         }
  52
  53         return true;
  54 #undef SIZE_EEPROM_4K
  55 }
  56
  57 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  58 {
  59 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  60         struct ath_common *common = ath9k_hw_common(ah);
  61         struct ar5416_eeprom_4k *eep =
  62                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  63         u16 *eepdata, temp, magic, magic2;
  64         u32 sum = 0, el;
  65         bool need_swap = false;
  66         int i, addr;
  67
  68
  69         if (!ath9k_hw_use_flash(ah)) {
  70                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  71                                          &magic)) {
  72                         ath_print(common, ATH_DBG_FATAL,
  73                                   "Reading Magic # failed\n");
  74                         return false;
  75                 }
  76
  77                 ath_print(common, ATH_DBG_EEPROM,
  78                           "Read Magic = 0x%04X\n", magic);
  79
  80                 if (magic != AR5416_EEPROM_MAGIC) {
  81                         magic2 = swab16(magic);
  82
  83                         if (magic2 == AR5416_EEPROM_MAGIC) {
  84                                 need_swap = true;
  85                                 eepdata = (u16 *) (&ah->eeprom);
  86
  87                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
  88                                         temp = swab16(*eepdata);
  89                                         *eepdata = temp;
  90                                         eepdata++;
  91                                 }
  92                         } else {
  93                                 ath_print(common, ATH_DBG_FATAL,
  94                                           "Invalid EEPROM Magic. "
  95                                           "endianness mismatch.\n");
  96                                 return -EINVAL;
  97                         }
  98                 }
  99         }
 100
 101         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 102                   need_swap ? "True" : "False");
 103
 104         if (need_swap)
 105                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 106         else
 107                 el = ah->eeprom.map4k.baseEepHeader.length;
 108
 109         if (el > sizeof(struct ar5416_eeprom_4k))
 110                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 111         else
 112                 el = el / sizeof(u16);
 113
 114         eepdata = (u16 *)(&ah->eeprom);
 115
 116         for (i = 0; i < el; i++)
 117                 sum ^= *eepdata++;
 118
 119         if (need_swap) {
 120                 u32 integer;
 121                 u16 word;
 122
 123                 ath_print(common, ATH_DBG_EEPROM,
 124                           "EEPROM Endianness is not native.. Changing\n");
 125
 126                 word = swab16(eep->baseEepHeader.length);
 127                 eep->baseEepHeader.length = word;
 128
 129                 word = swab16(eep->baseEepHeader.checksum);
 130                 eep->baseEepHeader.checksum = word;
 131
 132                 word = swab16(eep->baseEepHeader.version);
 133                 eep->baseEepHeader.version = word;
 134
 135                 word = swab16(eep->baseEepHeader.regDmn[0]);
 136                 eep->baseEepHeader.regDmn[0] = word;
 137
 138                 word = swab16(eep->baseEepHeader.regDmn[1]);
 139                 eep->baseEepHeader.regDmn[1] = word;
 140
 141                 word = swab16(eep->baseEepHeader.rfSilent);
 142                 eep->baseEepHeader.rfSilent = word;
 143
 144                 word = swab16(eep->baseEepHeader.blueToothOptions);
 145                 eep->baseEepHeader.blueToothOptions = word;
 146
 147                 word = swab16(eep->baseEepHeader.deviceCap);
 148                 eep->baseEepHeader.deviceCap = word;
 149
 150                 integer = swab32(eep->modalHeader.antCtrlCommon);
 151                 eep->modalHeader.antCtrlCommon = integer;
 152
 153                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 154                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 155                         eep->modalHeader.antCtrlChain[i] = integer;
 156                 }
 157
 158                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 159                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 160                         eep->modalHeader.spurChans[i].spurChan = word;
 161                 }
 162         }
 163
 164         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 165             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 166                 ath_print(common, ATH_DBG_FATAL,
 167                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 168                           sum, ah->eep_ops->get_eeprom_ver(ah));
 169                 return -EINVAL;
 170         }
 171
 172         return 0;
 173 #undef EEPROM_4K_SIZE
 174 }
 175
 176 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 177                                   enum eeprom_param param)
 178 {
 179         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 180         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 181         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 182         u16 ver_minor;
 183
 184         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 185
 186         switch (param) {
 187         case EEP_NFTHRESH_2:
 188                 return pModal->noiseFloorThreshCh[0];
 189         case EEP_MAC_LSW:
 190                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 191         case EEP_MAC_MID:
 192                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 193         case EEP_MAC_MSW:
 194                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 195         case EEP_REG_0:
 196                 return pBase->regDmn[0];
 197         case EEP_REG_1:
 198                 return pBase->regDmn[1];
 199         case EEP_OP_CAP:
 200                 return pBase->deviceCap;
 201         case EEP_OP_MODE:
 202                 return pBase->opCapFlags;
 203         case EEP_RF_SILENT:
 204                 return pBase->rfSilent;
 205         case EEP_OB_2:
 206                 return pModal->ob_0;
 207         case EEP_DB_2:
 208                 return pModal->db1_1;
 209         case EEP_MINOR_REV:
 210                 return ver_minor;
 211         case EEP_TX_MASK:
 212                 return pBase->txMask;
 213         case EEP_RX_MASK:
 214                 return pBase->rxMask;
 215         case EEP_FRAC_N_5G:
 216                 return 0;
 217         case EEP_PWR_TABLE_OFFSET:
 218                 return AR5416_PWR_TABLE_OFFSET_DB;
 219         case EEP_MODAL_VER:
 220                 return pModal->version;
 221         case EEP_ANT_DIV_CTL1:
 222                 return pModal->antdiv_ctl1;
 223         case EEP_TXGAIN_TYPE:
 224                 if (ver_minor >= AR5416_EEP_MINOR_VER_19)
 225                         return pBase->txGainType;
 226                 else
 227                         return AR5416_EEP_TXGAIN_ORIGINAL;
 228         default:
 229                 return 0;
 230         }
 231 }
 232
 233 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
 234                                 struct ath9k_channel *chan,
 235                                 struct cal_data_per_freq_4k *pRawDataSet,
 236                                 u8 *bChans, u16 availPiers,
 237                                 u16 tPdGainOverlap,
 238                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 239                                 u16 numXpdGains)
 240 {
 241 #define TMP_VAL_VPD_TABLE \
 242         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
 243         int i, j, k;
 244         int16_t ss;
 245         u16 idxL = 0, idxR = 0, numPiers;
 246         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
 247                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 248         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
 249                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 250         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
 251                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 252
 253         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 254         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 255         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 256         int16_t vpdStep;
 257         int16_t tmpVal;
 258         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 259         bool match;
 260         int16_t minDelta = 0;
 261         struct chan_centers centers;
 262 #define PD_GAIN_BOUNDARY_DEFAULT 58;
 263
 264         memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
 265         ath9k_hw_get_channel_centers(ah, chan, &centers);
 266
 267         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 268                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 269                         break;
 270         }
 271
 272         match = ath9k_hw_get_lower_upper_index(
 273                                         (u8)FREQ2FBIN(centers.synth_center,
 274                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
 275                                         &idxL, &idxR);
 276
 277         if (match) {
 278                 for (i = 0; i < numXpdGains; i++) {
 279                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 280                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 281                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 282                                         pRawDataSet[idxL].pwrPdg[i],
 283                                         pRawDataSet[idxL].vpdPdg[i],
 284                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
 285                                         vpdTableI[i]);
 286                 }
 287         } else {
 288                 for (i = 0; i < numXpdGains; i++) {
 289                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 290                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 291                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 292                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 293
 294                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 295
 296                         maxPwrT4[i] =
 297                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
 298                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
 299
 300
 301                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 302                                                 pPwrL, pVpdL,
 303                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 304                                                 vpdTableL[i]);
 305                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 306                                                 pPwrR, pVpdR,
 307                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 308                                                 vpdTableR[i]);
 309
 310                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 311                                 vpdTableI[i][j] =
 312                                         (u8)(ath9k_hw_interpolate((u16)
 313                                              FREQ2FBIN(centers.
 314                                                        synth_center,
 315                                                        IS_CHAN_2GHZ
 316                                                        (chan)),
 317                                              bChans[idxL], bChans[idxR],
 318                                              vpdTableL[i][j], vpdTableR[i][j]));
 319                         }
 320                 }
 321         }
 322
 323         k = 0;
 324
 325         for (i = 0; i < numXpdGains; i++) {
 326                 if (i == (numXpdGains - 1))
 327                         pPdGainBoundaries[i] =
 328                                 (u16)(maxPwrT4[i] / 2);
 329                 else
 330                         pPdGainBoundaries[i] =
 331                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 332
 333                 pPdGainBoundaries[i] =
 334                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 335
 336                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 337                         minDelta = pPdGainBoundaries[0] - 23;
 338                         pPdGainBoundaries[0] = 23;
 339                 } else {
 340                         minDelta = 0;
 341                 }
 342
 343                 if (i == 0) {
 344                         if (AR_SREV_9280_20_OR_LATER(ah))
 345                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 346                         else
 347                                 ss = 0;
 348                 } else {
 349                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 350                                         (minPwrT4[i] / 2)) -
 351                                        tPdGainOverlap + 1 + minDelta);
 352                 }
 353                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 354                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 355
 356                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 357                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 358                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 359                         ss++;
 360                 }
 361
 362                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 363                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 364                                 (minPwrT4[i] / 2));
 365                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 366                         tgtIndex : sizeCurrVpdTable;
 367
 368                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
 369                         pPDADCValues[k++] = vpdTableI[i][ss++];
 370
 371                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 372                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 373                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 374
 375                 if (tgtIndex >= maxIndex) {
 376                         while ((ss <= tgtIndex) &&
 377                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 378                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
 379                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 380                                                          255 : tmpVal);
 381                                 ss++;
 382                         }
 383                 }
 384         }
 385
 386         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
 387                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
 388                 i++;
 389         }
 390
 391         while (k < AR5416_NUM_PDADC_VALUES) {
 392                 pPDADCValues[k] = pPDADCValues[k - 1];
 393                 k++;
 394         }
 395
 396         return;
 397 #undef TMP_VAL_VPD_TABLE
 398 }
 399
 400 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 401                                   struct ath9k_channel *chan,
 402                                   int16_t *pTxPowerIndexOffset)
 403 {
 404         struct ath_common *common = ath9k_hw_common(ah);
 405         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 406         struct cal_data_per_freq_4k *pRawDataset;
 407         u8 *pCalBChans = NULL;
 408         u16 pdGainOverlap_t2;
 409         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 410         u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
 411         u16 numPiers, i, j;
 412         u16 numXpdGain, xpdMask;
 413         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 414         u32 reg32, regOffset, regChainOffset;
 415
 416         xpdMask = pEepData->modalHeader.xpdGain;
 417
 418         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 419             AR5416_EEP_MINOR_VER_2) {
 420                 pdGainOverlap_t2 =
 421                         pEepData->modalHeader.pdGainOverlap;
 422         } else {
 423                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 424                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 425         }
 426
 427         pCalBChans = pEepData->calFreqPier2G;
 428         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 429
 430         numXpdGain = 0;
 431
 432         for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
 433                 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
 434                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 435                                 break;
 436                         xpdGainValues[numXpdGain] =
 437                                 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
 438                         numXpdGain++;
 439                 }
 440         }
 441
 442         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 443                       (numXpdGain - 1) & 0x3);
 444         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 445                       xpdGainValues[0]);
 446         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 447                       xpdGainValues[1]);
 448         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 449
 450         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 451                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 452                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 453                     (i != 0)) {
 454                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 455                 } else
 456                         regChainOffset = i * 0x1000;
 457
 458                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 459                         pRawDataset = pEepData->calPierData2G[i];
 460
 461                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
 462                                             pRawDataset, pCalBChans,
 463                                             numPiers, pdGainOverlap_t2,
 464                                             gainBoundaries,
 465                                             pdadcValues, numXpdGain);
 466
 467                         ENABLE_REGWRITE_BUFFER(ah);
 468
 469                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 470                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 471                                           SM(pdGainOverlap_t2,
 472                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 473                                           | SM(gainBoundaries[0],
 474                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 475                                           | SM(gainBoundaries[1],
 476                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 477                                           | SM(gainBoundaries[2],
 478                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 479                                           | SM(gainBoundaries[3],
 480                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 481                         }
 482
 483                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 484                         for (j = 0; j < 32; j++) {
 485                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 486                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 487                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 488                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 489                                 REG_WRITE(ah, regOffset, reg32);
 490
 491                                 ath_print(common, ATH_DBG_EEPROM,
 492                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
 493                                           i, regChainOffset, regOffset,
 494                                           reg32);
 495                                 ath_print(common, ATH_DBG_EEPROM,
 496                                           "PDADC: Chain %d | "
 497                                           "PDADC %3d Value %3d | "
 498                                           "PDADC %3d Value %3d | "
 499                                           "PDADC %3d Value %3d | "
 500                                           "PDADC %3d Value %3d |\n",
 501                                           i, 4 * j, pdadcValues[4 * j],
 502                                           4 * j + 1, pdadcValues[4 * j + 1],
 503                                           4 * j + 2, pdadcValues[4 * j + 2],
 504                                           4 * j + 3,
 505                                           pdadcValues[4 * j + 3]);
 506
 507                                 regOffset += 4;
 508                         }
 509
 510                         REGWRITE_BUFFER_FLUSH(ah);
 511                 }
 512         }
 513
 514         *pTxPowerIndexOffset = 0;
 515 }
 516
 517 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 518                                                  struct ath9k_channel *chan,
 519                                                  int16_t *ratesArray,
 520                                                  u16 cfgCtl,
 521                                                  u16 AntennaReduction,
 522                                                  u16 twiceMaxRegulatoryPower,
 523                                                  u16 powerLimit)
 524 {
 525 #define CMP_TEST_GRP \
 526         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 527          pEepData->ctlIndex[i])                                         \
 528         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 529             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 530
 531         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 532         int i;
 533         int16_t twiceLargestAntenna;
 534         u16 twiceMinEdgePower;
 535         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 536         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 537         u16 numCtlModes, *pCtlMode, ctlMode, freq;
 538         struct chan_centers centers;
 539         struct cal_ctl_data_4k *rep;
 540         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 541         static const u16 tpScaleReductionTable[5] =
 542                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 543         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 544                 0, { 0, 0, 0, 0}
 545         };
 546         struct cal_target_power_leg targetPowerOfdmExt = {
 547                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 548                 0, { 0, 0, 0, 0 }
 549         };
 550         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 551                 0, {0, 0, 0, 0}
 552         };
 553         u16 ctlModesFor11g[] =
 554                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 555                   CTL_2GHT40
 556                 };
 557
 558         ath9k_hw_get_channel_centers(ah, chan, &centers);
 559
 560         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 561         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 562                                            twiceLargestAntenna, 0);
 563
 564         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 565         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 566                 maxRegAllowedPower -=
 567                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 568         }
 569
 570         scaledPower = min(powerLimit, maxRegAllowedPower);
 571         scaledPower = max((u16)0, scaledPower);
 572
 573         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 574         pCtlMode = ctlModesFor11g;
 575
 576         ath9k_hw_get_legacy_target_powers(ah, chan,
 577                         pEepData->calTargetPowerCck,
 578                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 579                         &targetPowerCck, 4, false);
 580         ath9k_hw_get_legacy_target_powers(ah, chan,
 581                         pEepData->calTargetPower2G,
 582                         AR5416_NUM_2G_20_TARGET_POWERS,
 583                         &targetPowerOfdm, 4, false);
 584         ath9k_hw_get_target_powers(ah, chan,
 585                         pEepData->calTargetPower2GHT20,
 586                         AR5416_NUM_2G_20_TARGET_POWERS,
 587                         &targetPowerHt20, 8, false);
 588
 589         if (IS_CHAN_HT40(chan)) {
 590                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 591                 ath9k_hw_get_target_powers(ah, chan,
 592                                 pEepData->calTargetPower2GHT40,
 593                                 AR5416_NUM_2G_40_TARGET_POWERS,
 594                                 &targetPowerHt40, 8, true);
 595                 ath9k_hw_get_legacy_target_powers(ah, chan,
 596                                 pEepData->calTargetPowerCck,
 597                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 598                                 &targetPowerCckExt, 4, true);
 599                 ath9k_hw_get_legacy_target_powers(ah, chan,
 600                                 pEepData->calTargetPower2G,
 601                                 AR5416_NUM_2G_20_TARGET_POWERS,
 602                                 &targetPowerOfdmExt, 4, true);
 603         }
 604
 605         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 606                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 607                         (pCtlMode[ctlMode] == CTL_2GHT40);
 608
 609                 if (isHt40CtlMode)
 610                         freq = centers.synth_center;
 611                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 612                         freq = centers.ext_center;
 613                 else
 614                         freq = centers.ctl_center;
 615
 616                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 617                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 618                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 619
 620                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 621                              pEepData->ctlIndex[i]; i++) {
 622
 623                         if (CMP_TEST_GRP) {
 624                                 rep = &(pEepData->ctlData[i]);
 625
 626                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 627                                         freq,
 628                                         rep->ctlEdges[
 629                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 630                                         IS_CHAN_2GHZ(chan),
 631                                         AR5416_EEP4K_NUM_BAND_EDGES);
 632
 633                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 634                                         twiceMaxEdgePower =
 635                                                 min(twiceMaxEdgePower,
 636                                                     twiceMinEdgePower);
 637                                 } else {
 638                                         twiceMaxEdgePower = twiceMinEdgePower;
 639                                         break;
 640                                 }
 641                         }
 642                 }
 643
 644                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 645
 646                 switch (pCtlMode[ctlMode]) {
 647                 case CTL_11B:
 648                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 649                                 targetPowerCck.tPow2x[i] =
 650                                         min((u16)targetPowerCck.tPow2x[i],
 651                                             minCtlPower);
 652                         }
 653                         break;
 654                 case CTL_11G:
 655                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 656                                 targetPowerOfdm.tPow2x[i] =
 657                                         min((u16)targetPowerOfdm.tPow2x[i],
 658                                             minCtlPower);
 659                         }
 660                         break;
 661                 case CTL_2GHT20:
 662                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 663                                 targetPowerHt20.tPow2x[i] =
 664                                         min((u16)targetPowerHt20.tPow2x[i],
 665                                             minCtlPower);
 666                         }
 667                         break;
 668                 case CTL_11B_EXT:
 669                         targetPowerCckExt.tPow2x[0] =
 670                                 min((u16)targetPowerCckExt.tPow2x[0],
 671                                     minCtlPower);
 672                         break;
 673                 case CTL_11G_EXT:
 674                         targetPowerOfdmExt.tPow2x[0] =
 675                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 676                                     minCtlPower);
 677                         break;
 678                 case CTL_2GHT40:
 679                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 680                                 targetPowerHt40.tPow2x[i] =
 681                                         min((u16)targetPowerHt40.tPow2x[i],
 682                                             minCtlPower);
 683                         }
 684                         break;
 685                 default:
 686                         break;
 687                 }
 688         }
 689
 690         ratesArray[rate6mb] =
 691         ratesArray[rate9mb] =
 692         ratesArray[rate12mb] =
 693         ratesArray[rate18mb] =
 694         ratesArray[rate24mb] =
 695         targetPowerOfdm.tPow2x[0];
 696
 697         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 698         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 699         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 700         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 701
 702         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 703                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 704
 705         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 706         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 707         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 708         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 709
 710         if (IS_CHAN_HT40(chan)) {
 711                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 712                         ratesArray[rateHt40_0 + i] =
 713                                 targetPowerHt40.tPow2x[i];
 714                 }
 715                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 716                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 717                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 718                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 719         }
 720
 721 #undef CMP_TEST_GRP
 722 }
 723
 724 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 725                                     struct ath9k_channel *chan,
 726                                     u16 cfgCtl,
 727                                     u8 twiceAntennaReduction,
 728                                     u8 twiceMaxRegulatoryPower,
 729                                     u8 powerLimit)
 730 {
 731         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 732         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 733         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 734         int16_t ratesArray[Ar5416RateSize];
 735         int16_t txPowerIndexOffset = 0;
 736         u8 ht40PowerIncForPdadc = 2;
 737         int i;
 738
 739         memset(ratesArray, 0, sizeof(ratesArray));
 740
 741         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 742             AR5416_EEP_MINOR_VER_2) {
 743                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 744         }
 745
 746         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 747                                              &ratesArray[0], cfgCtl,
 748                                              twiceAntennaReduction,
 749                                              twiceMaxRegulatoryPower,
 750                                              powerLimit);
 751
 752         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 753
 754         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 755                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
 756                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
 757                         ratesArray[i] = AR5416_MAX_RATE_POWER;
 758         }
 759
 760
 761         /* Update regulatory */
 762
 763         i = rate6mb;
 764         if (IS_CHAN_HT40(chan))
 765                 i = rateHt40_0;
 766         else if (IS_CHAN_HT20(chan))
 767                 i = rateHt20_0;
 768
 769         regulatory->max_power_level = ratesArray[i];
 770
 771         if (AR_SREV_9280_20_OR_LATER(ah)) {
 772                 for (i = 0; i < Ar5416RateSize; i++)
 773                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 774         }
 775
 776         ENABLE_REGWRITE_BUFFER(ah);
 777
 778         /* OFDM power per rate */
 779         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 780                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 781                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 782                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 783                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 784         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 785                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 786                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 787                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 788                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 789
 790         /* CCK power per rate */
 791         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 792                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 793                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 794                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 795                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 796         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 797                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 798                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 799                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 800                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 801
 802         /* HT20 power per rate */
 803         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 804                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 805                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 806                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 807                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 808         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 809                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 810                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 811                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 812                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 813
 814         /* HT40 power per rate */
 815         if (IS_CHAN_HT40(chan)) {
 816                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 817                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 818                                        ht40PowerIncForPdadc, 24)
 819                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 820                                          ht40PowerIncForPdadc, 16)
 821                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 822                                          ht40PowerIncForPdadc, 8)
 823                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 824                                          ht40PowerIncForPdadc, 0));
 825                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 826                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 827                                        ht40PowerIncForPdadc, 24)
 828                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 829                                          ht40PowerIncForPdadc, 16)
 830                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 831                                          ht40PowerIncForPdadc, 8)
 832                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 833                                          ht40PowerIncForPdadc, 0));
 834                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 835                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 836                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 837                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 838                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 839         }
 840
 841         REGWRITE_BUFFER_FLUSH(ah);
 842 }
 843
 844 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
 845                                   struct ath9k_channel *chan)
 846 {
 847         struct modal_eep_4k_header *pModal;
 848         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 849         u8 biaslevel;
 850
 851         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 852                 return;
 853
 854         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 855                 return;
 856
 857         pModal = &eep->modalHeader;
 858
 859         if (pModal->xpaBiasLvl != 0xff) {
 860                 biaslevel = pModal->xpaBiasLvl;
 861                 INI_RA(&ah->iniAddac, 7, 1) =
 862                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
 863         }
 864 }
 865
 866 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 867                                  struct modal_eep_4k_header *pModal,
 868                                  struct ar5416_eeprom_4k *eep,
 869                                  u8 txRxAttenLocal)
 870 {
 871         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 872                   pModal->antCtrlChain[0]);
 873
 874         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 875                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 876                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 877                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 878                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 879                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 880
 881         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 882             AR5416_EEP_MINOR_VER_3) {
 883                 txRxAttenLocal = pModal->txRxAttenCh[0];
 884
 885                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 886                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 887                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 888                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 889                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 890                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 891                               pModal->xatten2Margin[0]);
 892                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 893                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 894
 895                 /* Set the block 1 value to block 0 value */
 896                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 897                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 898                               pModal->bswMargin[0]);
 899                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 900                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 901                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 902                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 903                               pModal->xatten2Margin[0]);
 904                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 905                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 906                               pModal->xatten2Db[0]);
 907         }
 908
 909         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 910                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 911         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 912                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 913
 914         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 915                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 916         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 917                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 918 }
 919
 920 /*
 921  * Read EEPROM header info and program the device for correct operation
 922  * given the channel value.
 923  */
 924 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 925                                          struct ath9k_channel *chan)
 926 {
 927         struct modal_eep_4k_header *pModal;
 928         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 929         u8 txRxAttenLocal;
 930         u8 ob[5], db1[5], db2[5];
 931         u8 ant_div_control1, ant_div_control2;
 932         u32 regVal;
 933
 934         pModal = &eep->modalHeader;
 935         txRxAttenLocal = 23;
 936
 937         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 938                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 939
 940         /* Single chain for 4K EEPROM*/
 941         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 942
 943         /* Initialize Ant Diversity settings from EEPROM */
 944         if (pModal->version >= 3) {
 945                 ant_div_control1 = pModal->antdiv_ctl1;
 946                 ant_div_control2 = pModal->antdiv_ctl2;
 947
 948                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 949                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 950
 951                 regVal |= SM(ant_div_control1,
 952                              AR_PHY_9285_ANT_DIV_CTL);
 953                 regVal |= SM(ant_div_control2,
 954                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 955                 regVal |= SM((ant_div_control2 >> 2),
 956                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 957                 regVal |= SM((ant_div_control1 >> 1),
 958                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 959                 regVal |= SM((ant_div_control1 >> 2),
 960                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 961
 962
 963                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 964                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 965                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 966                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 967                 regVal |= SM((ant_div_control1 >> 3),
 968                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 969
 970                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 971                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 972         }
 973
 974         if (pModal->version >= 2) {
 975                 ob[0] = pModal->ob_0;
 976                 ob[1] = pModal->ob_1;
 977                 ob[2] = pModal->ob_2;
 978                 ob[3] = pModal->ob_3;
 979                 ob[4] = pModal->ob_4;
 980
 981                 db1[0] = pModal->db1_0;
 982                 db1[1] = pModal->db1_1;
 983                 db1[2] = pModal->db1_2;
 984                 db1[3] = pModal->db1_3;
 985                 db1[4] = pModal->db1_4;
 986
 987                 db2[0] = pModal->db2_0;
 988                 db2[1] = pModal->db2_1;
 989                 db2[2] = pModal->db2_2;
 990                 db2[3] = pModal->db2_3;
 991                 db2[4] = pModal->db2_4;
 992         } else if (pModal->version == 1) {
 993                 ob[0] = pModal->ob_0;
 994                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 995                 db1[0] = pModal->db1_0;
 996                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 997                 db2[0] = pModal->db2_0;
 998                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 999         } else {
1000                 int i;
1001
1002                 for (i = 0; i < 5; i++) {
1003                         ob[i] = pModal->ob_0;
1004                         db1[i] = pModal->db1_0;
1005                         db2[i] = pModal->db1_0;
1006                 }
1007         }
1008
1009         if (AR_SREV_9271(ah)) {
1010                 ath9k_hw_analog_shift_rmw(ah,
1011                                           AR9285_AN_RF2G3,
1012                                           AR9271_AN_RF2G3_OB_cck,
1013                                           AR9271_AN_RF2G3_OB_cck_S,
1014                                           ob[0]);
1015                 ath9k_hw_analog_shift_rmw(ah,
1016                                           AR9285_AN_RF2G3,
1017                                           AR9271_AN_RF2G3_OB_psk,
1018                                           AR9271_AN_RF2G3_OB_psk_S,
1019                                           ob[1]);
1020                 ath9k_hw_analog_shift_rmw(ah,
1021                                           AR9285_AN_RF2G3,
1022                                           AR9271_AN_RF2G3_OB_qam,
1023                                           AR9271_AN_RF2G3_OB_qam_S,
1024                                           ob[2]);
1025                 ath9k_hw_analog_shift_rmw(ah,
1026                                           AR9285_AN_RF2G3,
1027                                           AR9271_AN_RF2G3_DB_1,
1028                                           AR9271_AN_RF2G3_DB_1_S,
1029                                           db1[0]);
1030                 ath9k_hw_analog_shift_rmw(ah,
1031                                           AR9285_AN_RF2G4,
1032                                           AR9271_AN_RF2G4_DB_2,
1033                                           AR9271_AN_RF2G4_DB_2_S,
1034                                           db2[0]);
1035         } else {
1036                 ath9k_hw_analog_shift_rmw(ah,
1037                                           AR9285_AN_RF2G3,
1038                                           AR9285_AN_RF2G3_OB_0,
1039                                           AR9285_AN_RF2G3_OB_0_S,
1040                                           ob[0]);
1041                 ath9k_hw_analog_shift_rmw(ah,
1042                                           AR9285_AN_RF2G3,
1043                                           AR9285_AN_RF2G3_OB_1,
1044                                           AR9285_AN_RF2G3_OB_1_S,
1045                                           ob[1]);
1046                 ath9k_hw_analog_shift_rmw(ah,
1047                                           AR9285_AN_RF2G3,
1048                                           AR9285_AN_RF2G3_OB_2,
1049                                           AR9285_AN_RF2G3_OB_2_S,
1050                                           ob[2]);
1051                 ath9k_hw_analog_shift_rmw(ah,
1052                                           AR9285_AN_RF2G3,
1053                                           AR9285_AN_RF2G3_OB_3,
1054                                           AR9285_AN_RF2G3_OB_3_S,
1055                                           ob[3]);
1056                 ath9k_hw_analog_shift_rmw(ah,
1057                                           AR9285_AN_RF2G3,
1058                                           AR9285_AN_RF2G3_OB_4,
1059                                           AR9285_AN_RF2G3_OB_4_S,
1060                                           ob[4]);
1061
1062                 ath9k_hw_analog_shift_rmw(ah,
1063                                           AR9285_AN_RF2G3,
1064                                           AR9285_AN_RF2G3_DB1_0,
1065                                           AR9285_AN_RF2G3_DB1_0_S,
1066                                           db1[0]);
1067                 ath9k_hw_analog_shift_rmw(ah,
1068                                           AR9285_AN_RF2G3,
1069                                           AR9285_AN_RF2G3_DB1_1,
1070                                           AR9285_AN_RF2G3_DB1_1_S,
1071                                           db1[1]);
1072                 ath9k_hw_analog_shift_rmw(ah,
1073                                           AR9285_AN_RF2G3,
1074                                           AR9285_AN_RF2G3_DB1_2,
1075                                           AR9285_AN_RF2G3_DB1_2_S,
1076                                           db1[2]);
1077                 ath9k_hw_analog_shift_rmw(ah,
1078                                           AR9285_AN_RF2G4,
1079                                           AR9285_AN_RF2G4_DB1_3,
1080                                           AR9285_AN_RF2G4_DB1_3_S,
1081                                           db1[3]);
1082                 ath9k_hw_analog_shift_rmw(ah,
1083                                           AR9285_AN_RF2G4,
1084                                           AR9285_AN_RF2G4_DB1_4,
1085                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1086
1087                 ath9k_hw_analog_shift_rmw(ah,
1088                                           AR9285_AN_RF2G4,
1089                                           AR9285_AN_RF2G4_DB2_0,
1090                                           AR9285_AN_RF2G4_DB2_0_S,
1091                                           db2[0]);
1092                 ath9k_hw_analog_shift_rmw(ah,
1093                                           AR9285_AN_RF2G4,
1094                                           AR9285_AN_RF2G4_DB2_1,
1095                                           AR9285_AN_RF2G4_DB2_1_S,
1096                                           db2[1]);
1097                 ath9k_hw_analog_shift_rmw(ah,
1098                                           AR9285_AN_RF2G4,
1099                                           AR9285_AN_RF2G4_DB2_2,
1100                                           AR9285_AN_RF2G4_DB2_2_S,
1101                                           db2[2]);
1102                 ath9k_hw_analog_shift_rmw(ah,
1103                                           AR9285_AN_RF2G4,
1104                                           AR9285_AN_RF2G4_DB2_3,
1105                                           AR9285_AN_RF2G4_DB2_3_S,
1106                                           db2[3]);
1107                 ath9k_hw_analog_shift_rmw(ah,
1108                                           AR9285_AN_RF2G4,
1109                                           AR9285_AN_RF2G4_DB2_4,
1110                                           AR9285_AN_RF2G4_DB2_4_S,
1111                                           db2[4]);
1112         }
1113
1114
1115         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1116                       pModal->switchSettling);
1117         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1118                       pModal->adcDesiredSize);
1119
1120         REG_WRITE(ah, AR_PHY_RF_CTL4,
1121                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1122                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1123                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1124                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1125
1126         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1127                       pModal->txEndToRxOn);
1128
1129         if (AR_SREV_9271_10(ah))
1130                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1131                               pModal->txEndToRxOn);
1132         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1133                       pModal->thresh62);
1134         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1135                       pModal->thresh62);
1136
1137         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1138                                                 AR5416_EEP_MINOR_VER_2) {
1139                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1140                               pModal->txFrameToDataStart);
1141                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1142                               pModal->txFrameToPaOn);
1143         }
1144
1145         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1146                                                 AR5416_EEP_MINOR_VER_3) {
1147                 if (IS_CHAN_HT40(chan))
1148                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1149                                       AR_PHY_SETTLING_SWITCH,
1150                                       pModal->swSettleHt40);
1151         }
1152 }
1153
1154 static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1155                                               struct ath9k_channel *chan)
1156 {
1157         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1158         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1159
1160         return pModal->antCtrlCommon;
1161 }
1162
1163 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1164                                          enum ath9k_hal_freq_band freq_band)
1165 {
1166         return 1;
1167 }
1168
1169 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1170 {
1171 #define EEP_MAP4K_SPURCHAN \
1172         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1173         struct ath_common *common = ath9k_hw_common(ah);
1174
1175         u16 spur_val = AR_NO_SPUR;
1176
1177         ath_print(common, ATH_DBG_ANI,
1178                   "Getting spur idx %d is2Ghz. %d val %x\n",
1179                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1180
1181         switch (ah->config.spurmode) {
1182         case SPUR_DISABLE:
1183                 break;
1184         case SPUR_ENABLE_IOCTL:
1185                 spur_val = ah->config.spurchans[i][is2GHz];
1186                 ath_print(common, ATH_DBG_ANI,
1187                           "Getting spur val from new loc. %d\n", spur_val);
1188                 break;
1189         case SPUR_ENABLE_EEPROM:
1190                 spur_val = EEP_MAP4K_SPURCHAN;
1191                 break;
1192         }
1193
1194         return spur_val;
1195
1196 #undef EEP_MAP4K_SPURCHAN
1197 }
1198
1199 const struct eeprom_ops eep_4k_ops = {
1200         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1201         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1202         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1203         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1204         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1205         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1206         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1207         .set_board_values       = ath9k_hw_4k_set_board_values,
1208         .set_addac              = ath9k_hw_4k_set_addac,
1209         .set_txpower            = ath9k_hw_4k_set_txpower,
1210         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1211 };