drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9002_phy.h"
  20
  21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  22 {
  23         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  24 }
  25
  26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  27 {
  28         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  29 }
  30
  31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  32
  33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  34 {
  35         struct ath_common *common = ath9k_hw_common(ah);
  36         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  37         int addr, eep_start_loc = 64;
  38
  39         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  40                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  41                         ath_dbg(common, ATH_DBG_EEPROM,
  42                                 "Unable to read eeprom region\n");
  43                         return false;
  44                 }
  45                 eep_data++;
  46         }
  47
  48         return true;
  49 }
  50
  51 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
  52 {
  53         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  54
  55         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
  56
  57         return true;
  58 }
  59
  60 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  61 {
  62         struct ath_common *common = ath9k_hw_common(ah);
  63
  64         if (!ath9k_hw_use_flash(ah)) {
  65                 ath_dbg(common, ATH_DBG_EEPROM,
  66                         "Reading from EEPROM, not flash\n");
  67         }
  68
  69         if (common->bus_ops->ath_bus_type == ATH_USB)
  70                 return __ath9k_hw_usb_4k_fill_eeprom(ah);
  71         else
  72                 return __ath9k_hw_4k_fill_eeprom(ah);
  73 }
  74
  75 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
  76 static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
  77                                       struct modal_eep_4k_header *modal_hdr)
  78 {
  79         PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
  80         PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
  81         PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
  82         PR_EEP("Switch Settle", modal_hdr->switchSettling);
  83         PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
  84         PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
  85         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
  86         PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
  87         PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
  88         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
  89         PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
  90         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
  91         PR_EEP("CCA Threshold)", modal_hdr->thresh62);
  92         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
  93         PR_EEP("xpdGain", modal_hdr->xpdGain);
  94         PR_EEP("External PD", modal_hdr->xpd);
  95         PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
  96         PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
  97         PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
  98         PR_EEP("O/D Bias Version", modal_hdr->version);
  99         PR_EEP("CCK OutputBias", modal_hdr->ob_0);
 100         PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
 101         PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
 102         PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
 103         PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
 104         PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
 105         PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
 106         PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
 107         PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
 108         PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
 109         PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
 110         PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
 111         PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
 112         PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
 113         PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
 114         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
 115         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
 116         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
 117         PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
 118         PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
 119         PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
 120         PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
 121         PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
 122         PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
 123         PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
 124         PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
 125         PR_EEP("TX Diversity", modal_hdr->tx_diversity);
 126
 127         return len;
 128 }
 129
 130 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 131                                        u8 *buf, u32 len, u32 size)
 132 {
 133         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 134         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 135
 136         if (!dump_base_hdr) {
 137                 len += snprintf(buf + len, size - len,
 138                                 "%20s :\n", "2GHz modal Header");
 139                 len += ath9k_dump_4k_modal_eeprom(buf, len, size,
 140                                                   &eep->modalHeader);
 141                 goto out;
 142         }
 143
 144         PR_EEP("Major Version", pBase->version >> 12);
 145         PR_EEP("Minor Version", pBase->version & 0xFFF);
 146         PR_EEP("Checksum", pBase->checksum);
 147         PR_EEP("Length", pBase->length);
 148         PR_EEP("RegDomain1", pBase->regDmn[0]);
 149         PR_EEP("RegDomain2", pBase->regDmn[1]);
 150         PR_EEP("TX Mask", pBase->txMask);
 151         PR_EEP("RX Mask", pBase->rxMask);
 152         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
 153         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
 154         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
 155                                         AR5416_OPFLAGS_N_2G_HT20));
 156         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
 157                                         AR5416_OPFLAGS_N_2G_HT40));
 158         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
 159                                         AR5416_OPFLAGS_N_5G_HT20));
 160         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
 161                                         AR5416_OPFLAGS_N_5G_HT40));
 162         PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
 163         PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
 164         PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
 165         PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
 166         PR_EEP("TX Gain type", pBase->txGainType);
 167
 168         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
 169                         pBase->macAddr);
 170
 171 out:
 172         if (len > size)
 173                 len = size;
 174
 175         return len;
 176 }
 177 #else
 178 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 179                                        u8 *buf, u32 len, u32 size)
 180 {
 181         return 0;
 182 }
 183 #endif
 184
 185
 186 #undef SIZE_EEPROM_4K
 187
 188 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 189 {
 190 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 191         struct ath_common *common = ath9k_hw_common(ah);
 192         struct ar5416_eeprom_4k *eep =
 193                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
 194         u16 *eepdata, temp, magic, magic2;
 195         u32 sum = 0, el;
 196         bool need_swap = false;
 197         int i, addr;
 198
 199
 200         if (!ath9k_hw_use_flash(ah)) {
 201                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
 202                                          &magic)) {
 203                         ath_err(common, "Reading Magic # failed\n");
 204                         return false;
 205                 }
 206
 207                 ath_dbg(common, ATH_DBG_EEPROM,
 208                         "Read Magic = 0x%04X\n", magic);
 209
 210                 if (magic != AR5416_EEPROM_MAGIC) {
 211                         magic2 = swab16(magic);
 212
 213                         if (magic2 == AR5416_EEPROM_MAGIC) {
 214                                 need_swap = true;
 215                                 eepdata = (u16 *) (&ah->eeprom);
 216
 217                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 218                                         temp = swab16(*eepdata);
 219                                         *eepdata = temp;
 220                                         eepdata++;
 221                                 }
 222                         } else {
 223                                 ath_err(common,
 224                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 225                                 return -EINVAL;
 226                         }
 227                 }
 228         }
 229
 230         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 231                 need_swap ? "True" : "False");
 232
 233         if (need_swap)
 234                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 235         else
 236                 el = ah->eeprom.map4k.baseEepHeader.length;
 237
 238         if (el > sizeof(struct ar5416_eeprom_4k))
 239                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 240         else
 241                 el = el / sizeof(u16);
 242
 243         eepdata = (u16 *)(&ah->eeprom);
 244
 245         for (i = 0; i < el; i++)
 246                 sum ^= *eepdata++;
 247
 248         if (need_swap) {
 249                 u32 integer;
 250                 u16 word;
 251
 252                 ath_dbg(common, ATH_DBG_EEPROM,
 253                         "EEPROM Endianness is not native.. Changing\n");
 254
 255                 word = swab16(eep->baseEepHeader.length);
 256                 eep->baseEepHeader.length = word;
 257
 258                 word = swab16(eep->baseEepHeader.checksum);
 259                 eep->baseEepHeader.checksum = word;
 260
 261                 word = swab16(eep->baseEepHeader.version);
 262                 eep->baseEepHeader.version = word;
 263
 264                 word = swab16(eep->baseEepHeader.regDmn[0]);
 265                 eep->baseEepHeader.regDmn[0] = word;
 266
 267                 word = swab16(eep->baseEepHeader.regDmn[1]);
 268                 eep->baseEepHeader.regDmn[1] = word;
 269
 270                 word = swab16(eep->baseEepHeader.rfSilent);
 271                 eep->baseEepHeader.rfSilent = word;
 272
 273                 word = swab16(eep->baseEepHeader.blueToothOptions);
 274                 eep->baseEepHeader.blueToothOptions = word;
 275
 276                 word = swab16(eep->baseEepHeader.deviceCap);
 277                 eep->baseEepHeader.deviceCap = word;
 278
 279                 integer = swab32(eep->modalHeader.antCtrlCommon);
 280                 eep->modalHeader.antCtrlCommon = integer;
 281
 282                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 283                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 284                         eep->modalHeader.antCtrlChain[i] = integer;
 285                 }
 286
 287                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 288                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 289                         eep->modalHeader.spurChans[i].spurChan = word;
 290                 }
 291         }
 292
 293         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 294             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 295                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 296                         sum, ah->eep_ops->get_eeprom_ver(ah));
 297                 return -EINVAL;
 298         }
 299
 300         return 0;
 301 #undef EEPROM_4K_SIZE
 302 }
 303
 304 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 305                                   enum eeprom_param param)
 306 {
 307         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 308         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 309         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 310         u16 ver_minor;
 311
 312         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 313
 314         switch (param) {
 315         case EEP_NFTHRESH_2:
 316                 return pModal->noiseFloorThreshCh[0];
 317         case EEP_MAC_LSW:
 318                 return get_unaligned_be16(pBase->macAddr);
 319         case EEP_MAC_MID:
 320                 return get_unaligned_be16(pBase->macAddr + 2);
 321         case EEP_MAC_MSW:
 322                 return get_unaligned_be16(pBase->macAddr + 4);
 323         case EEP_REG_0:
 324                 return pBase->regDmn[0];
 325         case EEP_REG_1:
 326                 return pBase->regDmn[1];
 327         case EEP_OP_CAP:
 328                 return pBase->deviceCap;
 329         case EEP_OP_MODE:
 330                 return pBase->opCapFlags;
 331         case EEP_RF_SILENT:
 332                 return pBase->rfSilent;
 333         case EEP_OB_2:
 334                 return pModal->ob_0;
 335         case EEP_DB_2:
 336                 return pModal->db1_1;
 337         case EEP_MINOR_REV:
 338                 return ver_minor;
 339         case EEP_TX_MASK:
 340                 return pBase->txMask;
 341         case EEP_RX_MASK:
 342                 return pBase->rxMask;
 343         case EEP_FRAC_N_5G:
 344                 return 0;
 345         case EEP_PWR_TABLE_OFFSET:
 346                 return AR5416_PWR_TABLE_OFFSET_DB;
 347         case EEP_MODAL_VER:
 348                 return pModal->version;
 349         case EEP_ANT_DIV_CTL1:
 350                 return pModal->antdiv_ctl1;
 351         case EEP_TXGAIN_TYPE:
 352                 return pBase->txGainType;
 353         case EEP_ANTENNA_GAIN_2G:
 354                 return pModal->antennaGainCh[0];
 355         default:
 356                 return 0;
 357         }
 358 }
 359
 360 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 361                                   struct ath9k_channel *chan)
 362 {
 363         struct ath_common *common = ath9k_hw_common(ah);
 364         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 365         struct cal_data_per_freq_4k *pRawDataset;
 366         u8 *pCalBChans = NULL;
 367         u16 pdGainOverlap_t2;
 368         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 369         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 370         u16 numPiers, i, j;
 371         u16 numXpdGain, xpdMask;
 372         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 373         u32 reg32, regOffset, regChainOffset;
 374
 375         xpdMask = pEepData->modalHeader.xpdGain;
 376
 377         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 378             AR5416_EEP_MINOR_VER_2) {
 379                 pdGainOverlap_t2 =
 380                         pEepData->modalHeader.pdGainOverlap;
 381         } else {
 382                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 383                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 384         }
 385
 386         pCalBChans = pEepData->calFreqPier2G;
 387         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 388
 389         numXpdGain = 0;
 390
 391         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 392                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 393                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 394                                 break;
 395                         xpdGainValues[numXpdGain] =
 396                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 397                         numXpdGain++;
 398                 }
 399         }
 400
 401         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 402                       (numXpdGain - 1) & 0x3);
 403         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 404                       xpdGainValues[0]);
 405         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 406                       xpdGainValues[1]);
 407         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 408
 409         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 410                 regChainOffset = i * 0x1000;
 411
 412                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 413                         pRawDataset = pEepData->calPierData2G[i];
 414
 415                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
 416                                             pRawDataset, pCalBChans,
 417                                             numPiers, pdGainOverlap_t2,
 418                                             gainBoundaries,
 419                                             pdadcValues, numXpdGain);
 420
 421                         ENABLE_REGWRITE_BUFFER(ah);
 422
 423                         REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 424                                   SM(pdGainOverlap_t2,
 425                                      AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 426                                   | SM(gainBoundaries[0],
 427                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 428                                   | SM(gainBoundaries[1],
 429                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 430                                   | SM(gainBoundaries[2],
 431                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 432                                   | SM(gainBoundaries[3],
 433                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 434
 435                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 436                         for (j = 0; j < 32; j++) {
 437                                 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
 438                                 REG_WRITE(ah, regOffset, reg32);
 439
 440                                 ath_dbg(common, ATH_DBG_EEPROM,
 441                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 442                                         i, regChainOffset, regOffset,
 443                                         reg32);
 444                                 ath_dbg(common, ATH_DBG_EEPROM,
 445                                         "PDADC: Chain %d | "
 446                                         "PDADC %3d Value %3d | "
 447                                         "PDADC %3d Value %3d | "
 448                                         "PDADC %3d Value %3d | "
 449                                         "PDADC %3d Value %3d |\n",
 450                                         i, 4 * j, pdadcValues[4 * j],
 451                                         4 * j + 1, pdadcValues[4 * j + 1],
 452                                         4 * j + 2, pdadcValues[4 * j + 2],
 453                                         4 * j + 3, pdadcValues[4 * j + 3]);
 454
 455                                 regOffset += 4;
 456                         }
 457
 458                         REGWRITE_BUFFER_FLUSH(ah);
 459                 }
 460         }
 461 }
 462
 463 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 464                                                  struct ath9k_channel *chan,
 465                                                  int16_t *ratesArray,
 466                                                  u16 cfgCtl,
 467                                                  u16 antenna_reduction,
 468                                                  u16 powerLimit)
 469 {
 470 #define CMP_TEST_GRP \
 471         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 472          pEepData->ctlIndex[i])                                         \
 473         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 474             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 475
 476         int i;
 477         u16 twiceMinEdgePower;
 478         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 479         u16 scaledPower = 0, minCtlPower;
 480         u16 numCtlModes;
 481         const u16 *pCtlMode;
 482         u16 ctlMode, freq;
 483         struct chan_centers centers;
 484         struct cal_ctl_data_4k *rep;
 485         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 486         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 487                 0, { 0, 0, 0, 0}
 488         };
 489         struct cal_target_power_leg targetPowerOfdmExt = {
 490                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 491                 0, { 0, 0, 0, 0 }
 492         };
 493         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 494                 0, {0, 0, 0, 0}
 495         };
 496         static const u16 ctlModesFor11g[] = {
 497                 CTL_11B, CTL_11G, CTL_2GHT20,
 498                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 499         };
 500
 501         ath9k_hw_get_channel_centers(ah, chan, &centers);
 502
 503         scaledPower = powerLimit - antenna_reduction;
 504         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 505         pCtlMode = ctlModesFor11g;
 506
 507         ath9k_hw_get_legacy_target_powers(ah, chan,
 508                         pEepData->calTargetPowerCck,
 509                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 510                         &targetPowerCck, 4, false);
 511         ath9k_hw_get_legacy_target_powers(ah, chan,
 512                         pEepData->calTargetPower2G,
 513                         AR5416_NUM_2G_20_TARGET_POWERS,
 514                         &targetPowerOfdm, 4, false);
 515         ath9k_hw_get_target_powers(ah, chan,
 516                         pEepData->calTargetPower2GHT20,
 517                         AR5416_NUM_2G_20_TARGET_POWERS,
 518                         &targetPowerHt20, 8, false);
 519
 520         if (IS_CHAN_HT40(chan)) {
 521                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 522                 ath9k_hw_get_target_powers(ah, chan,
 523                                 pEepData->calTargetPower2GHT40,
 524                                 AR5416_NUM_2G_40_TARGET_POWERS,
 525                                 &targetPowerHt40, 8, true);
 526                 ath9k_hw_get_legacy_target_powers(ah, chan,
 527                                 pEepData->calTargetPowerCck,
 528                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 529                                 &targetPowerCckExt, 4, true);
 530                 ath9k_hw_get_legacy_target_powers(ah, chan,
 531                                 pEepData->calTargetPower2G,
 532                                 AR5416_NUM_2G_20_TARGET_POWERS,
 533                                 &targetPowerOfdmExt, 4, true);
 534         }
 535
 536         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 537                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 538                         (pCtlMode[ctlMode] == CTL_2GHT40);
 539
 540                 if (isHt40CtlMode)
 541                         freq = centers.synth_center;
 542                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 543                         freq = centers.ext_center;
 544                 else
 545                         freq = centers.ctl_center;
 546
 547                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 548                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 549                         twiceMaxEdgePower = MAX_RATE_POWER;
 550
 551                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 552                              pEepData->ctlIndex[i]; i++) {
 553
 554                         if (CMP_TEST_GRP) {
 555                                 rep = &(pEepData->ctlData[i]);
 556
 557                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 558                                         freq,
 559                                         rep->ctlEdges[
 560                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 561                                         IS_CHAN_2GHZ(chan),
 562                                         AR5416_EEP4K_NUM_BAND_EDGES);
 563
 564                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 565                                         twiceMaxEdgePower =
 566                                                 min(twiceMaxEdgePower,
 567                                                     twiceMinEdgePower);
 568                                 } else {
 569                                         twiceMaxEdgePower = twiceMinEdgePower;
 570                                         break;
 571                                 }
 572                         }
 573                 }
 574
 575                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 576
 577                 switch (pCtlMode[ctlMode]) {
 578                 case CTL_11B:
 579                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 580                                 targetPowerCck.tPow2x[i] =
 581                                         min((u16)targetPowerCck.tPow2x[i],
 582                                             minCtlPower);
 583                         }
 584                         break;
 585                 case CTL_11G:
 586                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 587                                 targetPowerOfdm.tPow2x[i] =
 588                                         min((u16)targetPowerOfdm.tPow2x[i],
 589                                             minCtlPower);
 590                         }
 591                         break;
 592                 case CTL_2GHT20:
 593                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 594                                 targetPowerHt20.tPow2x[i] =
 595                                         min((u16)targetPowerHt20.tPow2x[i],
 596                                             minCtlPower);
 597                         }
 598                         break;
 599                 case CTL_11B_EXT:
 600                         targetPowerCckExt.tPow2x[0] =
 601                                 min((u16)targetPowerCckExt.tPow2x[0],
 602                                     minCtlPower);
 603                         break;
 604                 case CTL_11G_EXT:
 605                         targetPowerOfdmExt.tPow2x[0] =
 606                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 607                                     minCtlPower);
 608                         break;
 609                 case CTL_2GHT40:
 610                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 611                                 targetPowerHt40.tPow2x[i] =
 612                                         min((u16)targetPowerHt40.tPow2x[i],
 613                                             minCtlPower);
 614                         }
 615                         break;
 616                 default:
 617                         break;
 618                 }
 619         }
 620
 621         ratesArray[rate6mb] =
 622         ratesArray[rate9mb] =
 623         ratesArray[rate12mb] =
 624         ratesArray[rate18mb] =
 625         ratesArray[rate24mb] =
 626         targetPowerOfdm.tPow2x[0];
 627
 628         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 629         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 630         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 631         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 632
 633         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 634                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 635
 636         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 637         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 638         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 639         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 640
 641         if (IS_CHAN_HT40(chan)) {
 642                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 643                         ratesArray[rateHt40_0 + i] =
 644                                 targetPowerHt40.tPow2x[i];
 645                 }
 646                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 647                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 648                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 649                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 650         }
 651
 652 #undef CMP_TEST_GRP
 653 }
 654
 655 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 656                                     struct ath9k_channel *chan,
 657                                     u16 cfgCtl,
 658                                     u8 twiceAntennaReduction,
 659                                     u8 powerLimit, bool test)
 660 {
 661         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 662         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 663         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 664         int16_t ratesArray[Ar5416RateSize];
 665         u8 ht40PowerIncForPdadc = 2;
 666         int i;
 667
 668         memset(ratesArray, 0, sizeof(ratesArray));
 669
 670         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 671             AR5416_EEP_MINOR_VER_2) {
 672                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 673         }
 674
 675         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 676                                              &ratesArray[0], cfgCtl,
 677                                              twiceAntennaReduction,
 678                                              powerLimit);
 679
 680         ath9k_hw_set_4k_power_cal_table(ah, chan);
 681
 682         regulatory->max_power_level = 0;
 683         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 684                 if (ratesArray[i] > MAX_RATE_POWER)
 685                         ratesArray[i] = MAX_RATE_POWER;
 686
 687                 if (ratesArray[i] > regulatory->max_power_level)
 688                         regulatory->max_power_level = ratesArray[i];
 689         }
 690
 691         if (test)
 692             return;
 693
 694         for (i = 0; i < Ar5416RateSize; i++)
 695                 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 696
 697         ENABLE_REGWRITE_BUFFER(ah);
 698
 699         /* OFDM power per rate */
 700         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 701                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 702                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 703                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 704                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 705         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 706                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 707                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 708                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 709                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 710
 711         /* CCK power per rate */
 712         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 713                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 714                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 715                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 716                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 717         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 718                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 719                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 720                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 721                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 722
 723         /* HT20 power per rate */
 724         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 725                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 726                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 727                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 728                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 729         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 730                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 731                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 732                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 733                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 734
 735         /* HT40 power per rate */
 736         if (IS_CHAN_HT40(chan)) {
 737                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 738                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 739                                        ht40PowerIncForPdadc, 24)
 740                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 741                                          ht40PowerIncForPdadc, 16)
 742                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 743                                          ht40PowerIncForPdadc, 8)
 744                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 745                                          ht40PowerIncForPdadc, 0));
 746                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 747                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 748                                        ht40PowerIncForPdadc, 24)
 749                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 750                                          ht40PowerIncForPdadc, 16)
 751                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 752                                          ht40PowerIncForPdadc, 8)
 753                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 754                                          ht40PowerIncForPdadc, 0));
 755                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 756                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 757                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 758                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 759                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 760         }
 761
 762         REGWRITE_BUFFER_FLUSH(ah);
 763 }
 764
 765 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 766                                  struct modal_eep_4k_header *pModal,
 767                                  struct ar5416_eeprom_4k *eep,
 768                                  u8 txRxAttenLocal)
 769 {
 770         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 771                   pModal->antCtrlChain[0]);
 772
 773         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 774                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 775                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 776                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 777                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 778                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 779
 780         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 781             AR5416_EEP_MINOR_VER_3) {
 782                 txRxAttenLocal = pModal->txRxAttenCh[0];
 783
 784                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 785                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 786                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 787                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 788                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 789                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 790                               pModal->xatten2Margin[0]);
 791                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 792                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 793
 794                 /* Set the block 1 value to block 0 value */
 795                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 796                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 797                               pModal->bswMargin[0]);
 798                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 799                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 800                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 801                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 802                               pModal->xatten2Margin[0]);
 803                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 804                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 805                               pModal->xatten2Db[0]);
 806         }
 807
 808         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 809                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 810         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 811                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 812
 813         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 814                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 815         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 816                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 817 }
 818
 819 /*
 820  * Read EEPROM header info and program the device for correct operation
 821  * given the channel value.
 822  */
 823 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 824                                          struct ath9k_channel *chan)
 825 {
 826         struct modal_eep_4k_header *pModal;
 827         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 828         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 829         u8 txRxAttenLocal;
 830         u8 ob[5], db1[5], db2[5];
 831         u8 ant_div_control1, ant_div_control2;
 832         u8 bb_desired_scale;
 833         u32 regVal;
 834
 835         pModal = &eep->modalHeader;
 836         txRxAttenLocal = 23;
 837
 838         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 839
 840         /* Single chain for 4K EEPROM*/
 841         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 842
 843         /* Initialize Ant Diversity settings from EEPROM */
 844         if (pModal->version >= 3) {
 845                 ant_div_control1 = pModal->antdiv_ctl1;
 846                 ant_div_control2 = pModal->antdiv_ctl2;
 847
 848                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 849                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 850
 851                 regVal |= SM(ant_div_control1,
 852                              AR_PHY_9285_ANT_DIV_CTL);
 853                 regVal |= SM(ant_div_control2,
 854                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 855                 regVal |= SM((ant_div_control2 >> 2),
 856                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 857                 regVal |= SM((ant_div_control1 >> 1),
 858                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 859                 regVal |= SM((ant_div_control1 >> 2),
 860                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 861
 862
 863                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 864                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 865                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 866                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 867                 regVal |= SM((ant_div_control1 >> 3),
 868                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 869
 870                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 871                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 872         }
 873
 874         if (pModal->version >= 2) {
 875                 ob[0] = pModal->ob_0;
 876                 ob[1] = pModal->ob_1;
 877                 ob[2] = pModal->ob_2;
 878                 ob[3] = pModal->ob_3;
 879                 ob[4] = pModal->ob_4;
 880
 881                 db1[0] = pModal->db1_0;
 882                 db1[1] = pModal->db1_1;
 883                 db1[2] = pModal->db1_2;
 884                 db1[3] = pModal->db1_3;
 885                 db1[4] = pModal->db1_4;
 886
 887                 db2[0] = pModal->db2_0;
 888                 db2[1] = pModal->db2_1;
 889                 db2[2] = pModal->db2_2;
 890                 db2[3] = pModal->db2_3;
 891                 db2[4] = pModal->db2_4;
 892         } else if (pModal->version == 1) {
 893                 ob[0] = pModal->ob_0;
 894                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 895                 db1[0] = pModal->db1_0;
 896                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 897                 db2[0] = pModal->db2_0;
 898                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 899         } else {
 900                 int i;
 901
 902                 for (i = 0; i < 5; i++) {
 903                         ob[i] = pModal->ob_0;
 904                         db1[i] = pModal->db1_0;
 905                         db2[i] = pModal->db1_0;
 906                 }
 907         }
 908
 909         if (AR_SREV_9271(ah)) {
 910                 ath9k_hw_analog_shift_rmw(ah,
 911                                           AR9285_AN_RF2G3,
 912                                           AR9271_AN_RF2G3_OB_cck,
 913                                           AR9271_AN_RF2G3_OB_cck_S,
 914                                           ob[0]);
 915                 ath9k_hw_analog_shift_rmw(ah,
 916                                           AR9285_AN_RF2G3,
 917                                           AR9271_AN_RF2G3_OB_psk,
 918                                           AR9271_AN_RF2G3_OB_psk_S,
 919                                           ob[1]);
 920                 ath9k_hw_analog_shift_rmw(ah,
 921                                           AR9285_AN_RF2G3,
 922                                           AR9271_AN_RF2G3_OB_qam,
 923                                           AR9271_AN_RF2G3_OB_qam_S,
 924                                           ob[2]);
 925                 ath9k_hw_analog_shift_rmw(ah,
 926                                           AR9285_AN_RF2G3,
 927                                           AR9271_AN_RF2G3_DB_1,
 928                                           AR9271_AN_RF2G3_DB_1_S,
 929                                           db1[0]);
 930                 ath9k_hw_analog_shift_rmw(ah,
 931                                           AR9285_AN_RF2G4,
 932                                           AR9271_AN_RF2G4_DB_2,
 933                                           AR9271_AN_RF2G4_DB_2_S,
 934                                           db2[0]);
 935         } else {
 936                 ath9k_hw_analog_shift_rmw(ah,
 937                                           AR9285_AN_RF2G3,
 938                                           AR9285_AN_RF2G3_OB_0,
 939                                           AR9285_AN_RF2G3_OB_0_S,
 940                                           ob[0]);
 941                 ath9k_hw_analog_shift_rmw(ah,
 942                                           AR9285_AN_RF2G3,
 943                                           AR9285_AN_RF2G3_OB_1,
 944                                           AR9285_AN_RF2G3_OB_1_S,
 945                                           ob[1]);
 946                 ath9k_hw_analog_shift_rmw(ah,
 947                                           AR9285_AN_RF2G3,
 948                                           AR9285_AN_RF2G3_OB_2,
 949                                           AR9285_AN_RF2G3_OB_2_S,
 950                                           ob[2]);
 951                 ath9k_hw_analog_shift_rmw(ah,
 952                                           AR9285_AN_RF2G3,
 953                                           AR9285_AN_RF2G3_OB_3,
 954                                           AR9285_AN_RF2G3_OB_3_S,
 955                                           ob[3]);
 956                 ath9k_hw_analog_shift_rmw(ah,
 957                                           AR9285_AN_RF2G3,
 958                                           AR9285_AN_RF2G3_OB_4,
 959                                           AR9285_AN_RF2G3_OB_4_S,
 960                                           ob[4]);
 961
 962                 ath9k_hw_analog_shift_rmw(ah,
 963                                           AR9285_AN_RF2G3,
 964                                           AR9285_AN_RF2G3_DB1_0,
 965                                           AR9285_AN_RF2G3_DB1_0_S,
 966                                           db1[0]);
 967                 ath9k_hw_analog_shift_rmw(ah,
 968                                           AR9285_AN_RF2G3,
 969                                           AR9285_AN_RF2G3_DB1_1,
 970                                           AR9285_AN_RF2G3_DB1_1_S,
 971                                           db1[1]);
 972                 ath9k_hw_analog_shift_rmw(ah,
 973                                           AR9285_AN_RF2G3,
 974                                           AR9285_AN_RF2G3_DB1_2,
 975                                           AR9285_AN_RF2G3_DB1_2_S,
 976                                           db1[2]);
 977                 ath9k_hw_analog_shift_rmw(ah,
 978                                           AR9285_AN_RF2G4,
 979                                           AR9285_AN_RF2G4_DB1_3,
 980                                           AR9285_AN_RF2G4_DB1_3_S,
 981                                           db1[3]);
 982                 ath9k_hw_analog_shift_rmw(ah,
 983                                           AR9285_AN_RF2G4,
 984                                           AR9285_AN_RF2G4_DB1_4,
 985                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
 986
 987                 ath9k_hw_analog_shift_rmw(ah,
 988                                           AR9285_AN_RF2G4,
 989                                           AR9285_AN_RF2G4_DB2_0,
 990                                           AR9285_AN_RF2G4_DB2_0_S,
 991                                           db2[0]);
 992                 ath9k_hw_analog_shift_rmw(ah,
 993                                           AR9285_AN_RF2G4,
 994                                           AR9285_AN_RF2G4_DB2_1,
 995                                           AR9285_AN_RF2G4_DB2_1_S,
 996                                           db2[1]);
 997                 ath9k_hw_analog_shift_rmw(ah,
 998                                           AR9285_AN_RF2G4,
 999                                           AR9285_AN_RF2G4_DB2_2,
1000                                           AR9285_AN_RF2G4_DB2_2_S,
1001                                           db2[2]);
1002                 ath9k_hw_analog_shift_rmw(ah,
1003                                           AR9285_AN_RF2G4,
1004                                           AR9285_AN_RF2G4_DB2_3,
1005                                           AR9285_AN_RF2G4_DB2_3_S,
1006                                           db2[3]);
1007                 ath9k_hw_analog_shift_rmw(ah,
1008                                           AR9285_AN_RF2G4,
1009                                           AR9285_AN_RF2G4_DB2_4,
1010                                           AR9285_AN_RF2G4_DB2_4_S,
1011                                           db2[4]);
1012         }
1013
1014
1015         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1016                       pModal->switchSettling);
1017         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1018                       pModal->adcDesiredSize);
1019
1020         REG_WRITE(ah, AR_PHY_RF_CTL4,
1021                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1022                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1023                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1024                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1025
1026         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1027                       pModal->txEndToRxOn);
1028
1029         if (AR_SREV_9271_10(ah))
1030                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1031                               pModal->txEndToRxOn);
1032         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1033                       pModal->thresh62);
1034         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1035                       pModal->thresh62);
1036
1037         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1038                                                 AR5416_EEP_MINOR_VER_2) {
1039                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1040                               pModal->txFrameToDataStart);
1041                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1042                               pModal->txFrameToPaOn);
1043         }
1044
1045         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1046                                                 AR5416_EEP_MINOR_VER_3) {
1047                 if (IS_CHAN_HT40(chan))
1048                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1049                                       AR_PHY_SETTLING_SWITCH,
1050                                       pModal->swSettleHt40);
1051         }
1052
1053         bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1054                         EEP_4K_BB_DESIRED_SCALE_MASK);
1055         if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1056                 u32 pwrctrl, mask, clr;
1057
1058                 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1059                 pwrctrl = mask * bb_desired_scale;
1060                 clr = mask * 0x1f;
1061                 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1062                 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1063                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1064
1065                 mask = BIT(0)|BIT(5)|BIT(15);
1066                 pwrctrl = mask * bb_desired_scale;
1067                 clr = mask * 0x1f;
1068                 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1069
1070                 mask = BIT(0)|BIT(5);
1071                 pwrctrl = mask * bb_desired_scale;
1072                 clr = mask * 0x1f;
1073                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1074                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1075         }
1076 }
1077
1078 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1079 {
1080 #define EEP_MAP4K_SPURCHAN \
1081         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1082         struct ath_common *common = ath9k_hw_common(ah);
1083
1084         u16 spur_val = AR_NO_SPUR;
1085
1086         ath_dbg(common, ATH_DBG_ANI,
1087                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1088                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1089
1090         switch (ah->config.spurmode) {
1091         case SPUR_DISABLE:
1092                 break;
1093         case SPUR_ENABLE_IOCTL:
1094                 spur_val = ah->config.spurchans[i][is2GHz];
1095                 ath_dbg(common, ATH_DBG_ANI,
1096                         "Getting spur val from new loc. %d\n", spur_val);
1097                 break;
1098         case SPUR_ENABLE_EEPROM:
1099                 spur_val = EEP_MAP4K_SPURCHAN;
1100                 break;
1101         }
1102
1103         return spur_val;
1104
1105 #undef EEP_MAP4K_SPURCHAN
1106 }
1107
1108 const struct eeprom_ops eep_4k_ops = {
1109         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1110         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1111         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1112         .dump_eeprom            = ath9k_hw_4k_dump_eeprom,
1113         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1114         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1115         .set_board_values       = ath9k_hw_4k_set_board_values,
1116         .set_txpower            = ath9k_hw_4k_set_txpower,
1117         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1118 };