2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "ar9002_phy.h"
21 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
23 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
25 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
28 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
30 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
33 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
35 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
37 int addr, eep_start_loc = AR9287_EEP_START_LOC;
38 eep_data = (u16 *)eep;
40 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
41 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data))
49 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
51 u16 *eep_data = (u16 *)&ah->eeprom.map9287;
53 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
54 AR9287_HTC_EEP_START_LOC,
59 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
61 struct ath_common *common = ath9k_hw_common(ah);
63 if (!ath9k_hw_use_flash(ah)) {
64 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
67 if (common->bus_ops->ath_bus_type == ATH_USB)
68 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
70 return __ath9k_hw_ar9287_fill_eeprom(ah);
73 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
74 static u32 ar9287_dump_modal_eeprom(char *buf, u32 len, u32 size,
75 struct modal_eep_ar9287_header *modal_hdr)
77 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
78 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
79 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
80 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
81 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
82 PR_EEP("Switch Settle", modal_hdr->switchSettling);
83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
84 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
85 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
86 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
87 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
91 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
93 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
94 PR_EEP("xpdGain", modal_hdr->xpdGain);
95 PR_EEP("External PD", modal_hdr->xpd);
96 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
97 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
98 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
99 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
100 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
101 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
102 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
103 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
104 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
105 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
106 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
107 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
108 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
109 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
110 PR_EEP("AR92x7 Version", modal_hdr->version);
111 PR_EEP("DriverBias1", modal_hdr->db1);
112 PR_EEP("DriverBias2", modal_hdr->db1);
113 PR_EEP("CCK OutputBias", modal_hdr->ob_cck);
114 PR_EEP("PSK OutputBias", modal_hdr->ob_psk);
115 PR_EEP("QAM OutputBias", modal_hdr->ob_qam);
116 PR_EEP("PAL_OFF OutputBias", modal_hdr->ob_pal_off);
121 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
122 u8 *buf, u32 len, u32 size)
124 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
125 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
127 if (!dump_base_hdr) {
128 len += scnprintf(buf + len, size - len,
129 "%20s :\n", "2GHz modal Header");
130 len = ar9287_dump_modal_eeprom(buf, len, size,
135 PR_EEP("Major Version", pBase->version >> 12);
136 PR_EEP("Minor Version", pBase->version & 0xFFF);
137 PR_EEP("Checksum", pBase->checksum);
138 PR_EEP("Length", pBase->length);
139 PR_EEP("RegDomain1", pBase->regDmn[0]);
140 PR_EEP("RegDomain2", pBase->regDmn[1]);
141 PR_EEP("TX Mask", pBase->txMask);
142 PR_EEP("RX Mask", pBase->rxMask);
143 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
144 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
145 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
146 AR5416_OPFLAGS_N_2G_HT20));
147 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
148 AR5416_OPFLAGS_N_2G_HT40));
149 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
150 AR5416_OPFLAGS_N_5G_HT20));
151 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
152 AR5416_OPFLAGS_N_5G_HT40));
153 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
154 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
155 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
156 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
157 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
158 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
160 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
170 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
171 u8 *buf, u32 len, u32 size)
178 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
184 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
186 err = ath9k_hw_nvram_swap_data(ah, &need_swap, SIZE_EEPROM_AR9287);
191 el = swab16(eep->baseEepHeader.length);
193 el = eep->baseEepHeader.length;
195 el = min(el / sizeof(u16), SIZE_EEPROM_AR9287);
196 if (!ath9k_hw_nvram_validate_checksum(ah, el))
200 word = swab16(eep->baseEepHeader.length);
201 eep->baseEepHeader.length = word;
203 word = swab16(eep->baseEepHeader.checksum);
204 eep->baseEepHeader.checksum = word;
206 word = swab16(eep->baseEepHeader.version);
207 eep->baseEepHeader.version = word;
209 word = swab16(eep->baseEepHeader.regDmn[0]);
210 eep->baseEepHeader.regDmn[0] = word;
212 word = swab16(eep->baseEepHeader.regDmn[1]);
213 eep->baseEepHeader.regDmn[1] = word;
215 word = swab16(eep->baseEepHeader.rfSilent);
216 eep->baseEepHeader.rfSilent = word;
218 word = swab16(eep->baseEepHeader.blueToothOptions);
219 eep->baseEepHeader.blueToothOptions = word;
221 word = swab16(eep->baseEepHeader.deviceCap);
222 eep->baseEepHeader.deviceCap = word;
224 integer = swab32(eep->modalHeader.antCtrlCommon);
225 eep->modalHeader.antCtrlCommon = integer;
227 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
228 integer = swab32(eep->modalHeader.antCtrlChain[i]);
229 eep->modalHeader.antCtrlChain[i] = integer;
232 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
233 word = swab16(eep->modalHeader.spurChans[i].spurChan);
234 eep->modalHeader.spurChans[i].spurChan = word;
238 if (!ath9k_hw_nvram_check_version(ah, AR9287_EEP_VER,
239 AR5416_EEP_NO_BACK_VER))
245 #undef SIZE_EEPROM_AR9287
247 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
248 enum eeprom_param param)
250 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
251 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
252 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
255 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
259 return pModal->noiseFloorThreshCh[0];
261 return get_unaligned_be16(pBase->macAddr);
263 return get_unaligned_be16(pBase->macAddr + 2);
265 return get_unaligned_be16(pBase->macAddr + 4);
267 return pBase->regDmn[0];
269 return pBase->deviceCap;
271 return pBase->opCapFlags;
273 return pBase->rfSilent;
277 return pBase->txMask;
279 return pBase->rxMask;
281 return pBase->deviceType;
283 return pBase->openLoopPwrCntl;
284 case EEP_TEMPSENSE_SLOPE:
285 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
286 return pBase->tempSensSlope;
289 case EEP_TEMPSENSE_SLOPE_PAL_ON:
290 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
291 return pBase->tempSensSlopePalOn;
294 case EEP_ANTENNA_GAIN_2G:
295 return max_t(u8, pModal->antennaGainCh[0],
296 pModal->antennaGainCh[1]);
302 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
303 struct ath9k_channel *chan,
304 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
305 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
307 u16 idxL = 0, idxR = 0, numPiers;
309 struct chan_centers centers;
311 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
313 for (numPiers = 0; numPiers < availPiers; numPiers++) {
314 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
318 match = ath9k_hw_get_lower_upper_index(
319 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
320 pCalChans, numPiers, &idxL, &idxR);
323 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
325 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
326 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
331 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
332 int32_t txPower, u16 chain)
337 /* Enable OLPC for chain 0 */
339 tmpVal = REG_READ(ah, 0xa270);
340 tmpVal = tmpVal & 0xFCFFFFFF;
341 tmpVal = tmpVal | (0x3 << 24);
342 REG_WRITE(ah, 0xa270, tmpVal);
344 /* Enable OLPC for chain 1 */
346 tmpVal = REG_READ(ah, 0xb270);
347 tmpVal = tmpVal & 0xFCFFFFFF;
348 tmpVal = tmpVal | (0x3 << 24);
349 REG_WRITE(ah, 0xb270, tmpVal);
351 /* Write the OLPC ref power for chain 0 */
354 tmpVal = REG_READ(ah, 0xa398);
355 tmpVal = tmpVal & 0xff00ffff;
357 tmpVal = tmpVal | (a << 16);
358 REG_WRITE(ah, 0xa398, tmpVal);
361 /* Write the OLPC ref power for chain 1 */
364 tmpVal = REG_READ(ah, 0xb398);
365 tmpVal = tmpVal & 0xff00ffff;
367 tmpVal = tmpVal | (a << 16);
368 REG_WRITE(ah, 0xb398, tmpVal);
372 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
373 struct ath9k_channel *chan)
375 struct cal_data_per_freq_ar9287 *pRawDataset;
376 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
377 u8 *pCalBChans = NULL;
378 u16 pdGainOverlap_t2;
379 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
380 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
381 u16 numPiers = 0, i, j;
382 u16 numXpdGain, xpdMask;
383 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
384 u32 reg32, regOffset, regChainOffset, regval;
386 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
388 xpdMask = pEepData->modalHeader.xpdGain;
390 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
391 AR9287_EEP_MINOR_VER_2)
392 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
394 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
395 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
397 if (IS_CHAN_2GHZ(chan)) {
398 pCalBChans = pEepData->calFreqPier2G;
399 numPiers = AR9287_NUM_2G_CAL_PIERS;
400 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
401 pRawDatasetOpenLoop =
402 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
403 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
409 /* Calculate the value of xpdgains from the xpdGain Mask */
410 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
411 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
412 if (numXpdGain >= AR5416_NUM_PD_GAINS)
414 xpdGainValues[numXpdGain] =
415 (u16)(AR5416_PD_GAINS_IN_MASK-i);
420 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
421 (numXpdGain - 1) & 0x3);
422 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
424 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
426 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
429 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
430 regChainOffset = i * 0x1000;
432 if (pEepData->baseEepHeader.txMask & (1 << i)) {
433 pRawDatasetOpenLoop =
434 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
436 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
438 ar9287_eeprom_get_tx_gain_index(ah, chan,
440 pCalBChans, numPiers,
442 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
445 (struct cal_data_per_freq_ar9287 *)
446 pEepData->calPierData2G[i];
448 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
450 pCalBChans, numPiers,
457 ENABLE_REGWRITE_BUFFER(ah);
460 if (!ath9k_hw_ar9287_get_eeprom(ah,
463 regval = SM(pdGainOverlap_t2,
464 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
465 | SM(gainBoundaries[0],
466 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
467 | SM(gainBoundaries[1],
468 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
469 | SM(gainBoundaries[2],
470 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
471 | SM(gainBoundaries[3],
472 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
475 AR_PHY_TPCRG5 + regChainOffset,
480 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
481 pEepData->baseEepHeader.pwrTableOffset) {
482 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
483 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
486 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
487 pdadcValues[j] = pdadcValues[j+diff];
489 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
490 j < AR5416_NUM_PDADC_VALUES; j++)
492 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
495 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
496 regOffset = AR_PHY_BASE +
497 (672 << 2) + regChainOffset;
499 for (j = 0; j < 32; j++) {
500 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
502 REG_WRITE(ah, regOffset, reg32);
506 REGWRITE_BUFFER_FLUSH(ah);
511 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
512 struct ath9k_channel *chan,
515 u16 antenna_reduction,
519 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
520 pEepData->ctlIndex[i])
523 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
524 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
526 u16 twiceMaxEdgePower;
528 struct cal_ctl_data_ar9287 *rep;
529 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
530 targetPowerCck = {0, {0, 0, 0, 0} };
531 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
532 targetPowerCckExt = {0, {0, 0, 0, 0} };
533 struct cal_target_power_ht targetPowerHt20,
534 targetPowerHt40 = {0, {0, 0, 0, 0} };
535 u16 scaledPower = 0, minCtlPower;
536 static const u16 ctlModesFor11g[] = {
537 CTL_11B, CTL_11G, CTL_2GHT20,
538 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
541 const u16 *pCtlMode = NULL;
543 struct chan_centers centers;
545 u16 twiceMinEdgePower;
546 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
547 tx_chainmask = ah->txchainmask;
549 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
550 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
554 * Get TX power from EEPROM.
556 if (IS_CHAN_2GHZ(chan)) {
557 /* CTL_11B, CTL_11G, CTL_2GHT20 */
559 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
561 pCtlMode = ctlModesFor11g;
563 ath9k_hw_get_legacy_target_powers(ah, chan,
564 pEepData->calTargetPowerCck,
565 AR9287_NUM_2G_CCK_TARGET_POWERS,
566 &targetPowerCck, 4, false);
567 ath9k_hw_get_legacy_target_powers(ah, chan,
568 pEepData->calTargetPower2G,
569 AR9287_NUM_2G_20_TARGET_POWERS,
570 &targetPowerOfdm, 4, false);
571 ath9k_hw_get_target_powers(ah, chan,
572 pEepData->calTargetPower2GHT20,
573 AR9287_NUM_2G_20_TARGET_POWERS,
574 &targetPowerHt20, 8, false);
576 if (IS_CHAN_HT40(chan)) {
578 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
579 ath9k_hw_get_target_powers(ah, chan,
580 pEepData->calTargetPower2GHT40,
581 AR9287_NUM_2G_40_TARGET_POWERS,
582 &targetPowerHt40, 8, true);
583 ath9k_hw_get_legacy_target_powers(ah, chan,
584 pEepData->calTargetPowerCck,
585 AR9287_NUM_2G_CCK_TARGET_POWERS,
586 &targetPowerCckExt, 4, true);
587 ath9k_hw_get_legacy_target_powers(ah, chan,
588 pEepData->calTargetPower2G,
589 AR9287_NUM_2G_20_TARGET_POWERS,
590 &targetPowerOfdmExt, 4, true);
594 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
596 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
599 freq = centers.synth_center;
600 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
601 freq = centers.ext_center;
603 freq = centers.ctl_center;
605 twiceMaxEdgePower = MAX_RATE_POWER;
606 /* Walk through the CTL indices stored in EEPROM */
607 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
608 struct cal_ctl_edges *pRdEdgesPower;
611 * Compare test group from regulatory channel list
612 * with test mode from pCtlMode list
614 if (CMP_CTL || CMP_NO_CTL) {
615 rep = &(pEepData->ctlData[i]);
617 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
619 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
622 AR5416_NUM_BAND_EDGES);
624 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
625 twiceMaxEdgePower = min(twiceMaxEdgePower,
628 twiceMaxEdgePower = twiceMinEdgePower;
634 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
636 /* Apply ctl mode to correct target power set */
637 switch (pCtlMode[ctlMode]) {
639 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
640 targetPowerCck.tPow2x[i] =
641 (u8)min((u16)targetPowerCck.tPow2x[i],
647 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
648 targetPowerOfdm.tPow2x[i] =
649 (u8)min((u16)targetPowerOfdm.tPow2x[i],
655 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
656 targetPowerHt20.tPow2x[i] =
657 (u8)min((u16)targetPowerHt20.tPow2x[i],
662 targetPowerCckExt.tPow2x[0] =
663 (u8)min((u16)targetPowerCckExt.tPow2x[0],
668 targetPowerOfdmExt.tPow2x[0] =
669 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
674 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
675 targetPowerHt40.tPow2x[i] =
676 (u8)min((u16)targetPowerHt40.tPow2x[i],
685 /* Now set the rates array */
687 ratesArray[rate6mb] =
688 ratesArray[rate9mb] =
689 ratesArray[rate12mb] =
690 ratesArray[rate18mb] =
691 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
693 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
694 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
695 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
696 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
698 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
699 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
701 if (IS_CHAN_2GHZ(chan)) {
702 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
704 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
705 ratesArray[rate5_5s] =
706 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
707 ratesArray[rate11s] =
708 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
710 if (IS_CHAN_HT40(chan)) {
711 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
712 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
714 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
715 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
716 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
718 if (IS_CHAN_2GHZ(chan))
719 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
726 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
727 struct ath9k_channel *chan, u16 cfgCtl,
728 u8 twiceAntennaReduction,
729 u8 powerLimit, bool test)
731 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
732 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
733 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
734 int16_t ratesArray[Ar5416RateSize];
735 u8 ht40PowerIncForPdadc = 2;
738 memset(ratesArray, 0, sizeof(ratesArray));
740 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
741 AR9287_EEP_MINOR_VER_2)
742 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
744 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
745 &ratesArray[0], cfgCtl,
746 twiceAntennaReduction,
749 ath9k_hw_set_ar9287_power_cal_table(ah, chan);
751 regulatory->max_power_level = 0;
752 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
753 if (ratesArray[i] > MAX_RATE_POWER)
754 ratesArray[i] = MAX_RATE_POWER;
756 if (ratesArray[i] > regulatory->max_power_level)
757 regulatory->max_power_level = ratesArray[i];
760 ath9k_hw_update_regulatory_maxpower(ah);
765 for (i = 0; i < Ar5416RateSize; i++)
766 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
768 ENABLE_REGWRITE_BUFFER(ah);
770 /* OFDM power per rate */
771 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
772 ATH9K_POW_SM(ratesArray[rate18mb], 24)
773 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
774 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
775 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
777 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
778 ATH9K_POW_SM(ratesArray[rate54mb], 24)
779 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
780 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
781 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
783 /* CCK power per rate */
784 if (IS_CHAN_2GHZ(chan)) {
785 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
786 ATH9K_POW_SM(ratesArray[rate2s], 24)
787 | ATH9K_POW_SM(ratesArray[rate2l], 16)
788 | ATH9K_POW_SM(ratesArray[rateXr], 8)
789 | ATH9K_POW_SM(ratesArray[rate1l], 0));
790 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
791 ATH9K_POW_SM(ratesArray[rate11s], 24)
792 | ATH9K_POW_SM(ratesArray[rate11l], 16)
793 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
794 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
797 /* HT20 power per rate */
798 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
799 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
800 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
801 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
802 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
804 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
805 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
806 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
807 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
808 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
810 /* HT40 power per rate */
811 if (IS_CHAN_HT40(chan)) {
812 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
813 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
814 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
815 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
816 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
817 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
819 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
820 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
821 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
822 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
823 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
825 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
826 ATH9K_POW_SM(ratesArray[rateHt40_3] +
827 ht40PowerIncForPdadc, 24)
828 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
829 ht40PowerIncForPdadc, 16)
830 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
831 ht40PowerIncForPdadc, 8)
832 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
833 ht40PowerIncForPdadc, 0));
835 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
836 ATH9K_POW_SM(ratesArray[rateHt40_7] +
837 ht40PowerIncForPdadc, 24)
838 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
839 ht40PowerIncForPdadc, 16)
840 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
841 ht40PowerIncForPdadc, 8)
842 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
843 ht40PowerIncForPdadc, 0));
846 /* Dup/Ext power per rate */
847 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
848 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
849 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
850 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
851 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
854 /* TPC initializations */
855 if (ah->tpc_enabled) {
858 ht40_delta = (IS_CHAN_HT40(chan)) ? ht40PowerIncForPdadc : 0;
859 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
861 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
862 MAX_RATE_POWER | AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
865 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
868 REGWRITE_BUFFER_FLUSH(ah);
871 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
872 struct ath9k_channel *chan)
874 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
875 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
876 u32 regChainOffset, regval;
880 pModal = &eep->modalHeader;
882 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
884 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
885 regChainOffset = i * 0x1000;
887 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
888 pModal->antCtrlChain[i]);
890 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
891 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
892 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
893 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
894 SM(pModal->iqCalICh[i],
895 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
896 SM(pModal->iqCalQCh[i],
897 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
899 txRxAttenLocal = pModal->txRxAttenCh[i];
901 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
902 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
903 pModal->bswMargin[i]);
904 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
905 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
906 pModal->bswAtten[i]);
907 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
908 AR9280_PHY_RXGAIN_TXRX_ATTEN,
910 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
911 AR9280_PHY_RXGAIN_TXRX_MARGIN,
912 pModal->rxTxMarginCh[i]);
916 if (IS_CHAN_HT40(chan))
917 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
918 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
920 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
921 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
923 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
924 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
926 REG_WRITE(ah, AR_PHY_RF_CTL4,
927 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
928 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
929 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
930 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
932 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
933 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
935 REG_RMW_FIELD(ah, AR_PHY_CCA,
936 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
937 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
938 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
940 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
941 regval &= ~(AR9287_AN_RF2G3_DB1 |
942 AR9287_AN_RF2G3_DB2 |
943 AR9287_AN_RF2G3_OB_CCK |
944 AR9287_AN_RF2G3_OB_PSK |
945 AR9287_AN_RF2G3_OB_QAM |
946 AR9287_AN_RF2G3_OB_PAL_OFF);
947 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
948 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
949 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
950 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
951 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
952 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
954 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
956 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
957 regval &= ~(AR9287_AN_RF2G3_DB1 |
958 AR9287_AN_RF2G3_DB2 |
959 AR9287_AN_RF2G3_OB_CCK |
960 AR9287_AN_RF2G3_OB_PSK |
961 AR9287_AN_RF2G3_OB_QAM |
962 AR9287_AN_RF2G3_OB_PAL_OFF);
963 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
964 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
965 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
966 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
967 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
968 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
970 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
972 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
973 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
974 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
975 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
977 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
978 AR9287_AN_TOP2_XPABIAS_LVL,
979 AR9287_AN_TOP2_XPABIAS_LVL_S,
983 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
986 return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan;
989 const struct eeprom_ops eep_ar9287_ops = {
990 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
991 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
992 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
993 .dump_eeprom = ath9k_hw_ar9287_dump_eeprom,
994 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
995 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
996 .set_board_values = ath9k_hw_ar9287_set_board_values,
997 .set_txpower = ath9k_hw_ar9287_set_txpower,
998 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel