2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "ar9002_phy.h"
21 static void ath9k_get_txgain_index(struct ath_hw *ah,
22 struct ath9k_channel *chan,
23 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
24 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
27 u16 idxL = 0, idxR = 0, numPiers;
29 struct chan_centers centers;
31 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
33 for (numPiers = 0; numPiers < availPiers; numPiers++)
34 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
37 match = ath9k_hw_get_lower_upper_index(
38 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
39 calChans, numPiers, &idxL, &idxR);
41 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
42 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
44 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
45 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
46 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
49 while (pcdac > ah->originalGain[i] &&
50 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
67 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
70 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
73 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
75 pPDADCValues[i] = 0x0;
77 pPDADCValues[i] = 0xFF;
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
90 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
94 struct ath_common *common = ath9k_hw_common(ah);
95 u16 *eep_data = (u16 *)&ah->eeprom.def;
96 int addr, ar5416_eep_start_loc = 0x100;
98 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
99 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
101 ath_err(ath9k_hw_common(ah),
102 "Unable to read eeprom region\n");
110 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
112 u16 *eep_data = (u16 *)&ah->eeprom.def;
114 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
115 0x100, SIZE_EEPROM_DEF);
119 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
121 struct ath_common *common = ath9k_hw_common(ah);
123 if (!ath9k_hw_use_flash(ah)) {
124 ath_dbg(common, ATH_DBG_EEPROM,
125 "Reading from EEPROM, not flash\n");
128 if (common->bus_ops->ath_bus_type == ATH_USB)
129 return __ath9k_hw_usb_def_fill_eeprom(ah);
131 return __ath9k_hw_def_fill_eeprom(ah);
134 #undef SIZE_EEPROM_DEF
136 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
137 static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
138 struct modal_eep_header *modal_hdr)
140 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
141 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
142 PR_EEP("Chain2 Ant. Control", modal_hdr->antCtrlChain[2]);
143 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
144 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
145 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
146 PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]);
147 PR_EEP("Switch Settle", modal_hdr->switchSettling);
148 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
149 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
150 PR_EEP("Chain2 TxRxAtten", modal_hdr->txRxAttenCh[2]);
151 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
152 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
153 PR_EEP("Chain2 RxTxMargin", modal_hdr->rxTxMarginCh[2]);
154 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
155 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
156 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
157 PR_EEP("Chain1 xlna Gain", modal_hdr->xlnaGainCh[1]);
158 PR_EEP("Chain2 xlna Gain", modal_hdr->xlnaGainCh[2]);
159 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
160 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
161 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
162 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
163 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
164 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
165 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
166 PR_EEP("xpdGain", modal_hdr->xpdGain);
167 PR_EEP("External PD", modal_hdr->xpd);
168 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
169 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
170 PR_EEP("Chain2 I Coefficient", modal_hdr->iqCalICh[2]);
171 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
172 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
173 PR_EEP("Chain2 Q Coefficient", modal_hdr->iqCalQCh[2]);
174 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
175 PR_EEP("Chain0 OutputBias", modal_hdr->ob);
176 PR_EEP("Chain0 DriverBias", modal_hdr->db);
177 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
178 PR_EEP("2chain pwr decrease", modal_hdr->pwrDecreaseFor2Chain);
179 PR_EEP("3chain pwr decrease", modal_hdr->pwrDecreaseFor3Chain);
180 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
181 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
182 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
183 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
184 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
185 PR_EEP("Chain2 bswAtten", modal_hdr->bswAtten[2]);
186 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
187 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
188 PR_EEP("Chain2 bswMargin", modal_hdr->bswMargin[2]);
189 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
190 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
191 PR_EEP("Chain1 xatten2Db", modal_hdr->xatten2Db[1]);
192 PR_EEP("Chain2 xatten2Db", modal_hdr->xatten2Db[2]);
193 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
194 PR_EEP("Chain1 xatten2Margin", modal_hdr->xatten2Margin[1]);
195 PR_EEP("Chain2 xatten2Margin", modal_hdr->xatten2Margin[2]);
196 PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1);
197 PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1);
198 PR_EEP("LNA Control", modal_hdr->lna_ctl);
199 PR_EEP("XPA Bias Freq0", modal_hdr->xpaBiasLvlFreq[0]);
200 PR_EEP("XPA Bias Freq1", modal_hdr->xpaBiasLvlFreq[1]);
201 PR_EEP("XPA Bias Freq2", modal_hdr->xpaBiasLvlFreq[2]);
206 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
207 u8 *buf, u32 len, u32 size)
209 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
210 struct base_eep_header *pBase = &eep->baseEepHeader;
212 if (!dump_base_hdr) {
213 len += snprintf(buf + len, size - len,
214 "%20s :\n", "2GHz modal Header");
215 len += ath9k_def_dump_modal_eeprom(buf, len, size,
216 &eep->modalHeader[0]);
217 len += snprintf(buf + len, size - len,
218 "%20s :\n", "5GHz modal Header");
219 len += ath9k_def_dump_modal_eeprom(buf, len, size,
220 &eep->modalHeader[1]);
224 PR_EEP("Major Version", pBase->version >> 12);
225 PR_EEP("Minor Version", pBase->version & 0xFFF);
226 PR_EEP("Checksum", pBase->checksum);
227 PR_EEP("Length", pBase->length);
228 PR_EEP("RegDomain1", pBase->regDmn[0]);
229 PR_EEP("RegDomain2", pBase->regDmn[1]);
230 PR_EEP("TX Mask", pBase->txMask);
231 PR_EEP("RX Mask", pBase->rxMask);
232 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
233 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
234 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
235 AR5416_OPFLAGS_N_2G_HT20));
236 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
237 AR5416_OPFLAGS_N_2G_HT40));
238 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
239 AR5416_OPFLAGS_N_5G_HT20));
240 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
241 AR5416_OPFLAGS_N_5G_HT40));
242 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
243 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
244 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
245 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
246 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
248 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
258 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
259 u8 *buf, u32 len, u32 size)
266 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
268 struct ar5416_eeprom_def *eep =
269 (struct ar5416_eeprom_def *) &ah->eeprom.def;
270 struct ath_common *common = ath9k_hw_common(ah);
271 u16 *eepdata, temp, magic, magic2;
273 bool need_swap = false;
276 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
277 ath_err(common, "Reading Magic # failed\n");
281 if (!ath9k_hw_use_flash(ah)) {
282 ath_dbg(common, ATH_DBG_EEPROM,
283 "Read Magic = 0x%04X\n", magic);
285 if (magic != AR5416_EEPROM_MAGIC) {
286 magic2 = swab16(magic);
288 if (magic2 == AR5416_EEPROM_MAGIC) {
289 size = sizeof(struct ar5416_eeprom_def);
291 eepdata = (u16 *) (&ah->eeprom);
293 for (addr = 0; addr < size / sizeof(u16); addr++) {
294 temp = swab16(*eepdata);
300 "Invalid EEPROM Magic. Endianness mismatch.\n");
306 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
307 need_swap ? "True" : "False");
310 el = swab16(ah->eeprom.def.baseEepHeader.length);
312 el = ah->eeprom.def.baseEepHeader.length;
314 if (el > sizeof(struct ar5416_eeprom_def))
315 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
317 el = el / sizeof(u16);
319 eepdata = (u16 *)(&ah->eeprom);
321 for (i = 0; i < el; i++)
328 ath_dbg(common, ATH_DBG_EEPROM,
329 "EEPROM Endianness is not native.. Changing.\n");
331 word = swab16(eep->baseEepHeader.length);
332 eep->baseEepHeader.length = word;
334 word = swab16(eep->baseEepHeader.checksum);
335 eep->baseEepHeader.checksum = word;
337 word = swab16(eep->baseEepHeader.version);
338 eep->baseEepHeader.version = word;
340 word = swab16(eep->baseEepHeader.regDmn[0]);
341 eep->baseEepHeader.regDmn[0] = word;
343 word = swab16(eep->baseEepHeader.regDmn[1]);
344 eep->baseEepHeader.regDmn[1] = word;
346 word = swab16(eep->baseEepHeader.rfSilent);
347 eep->baseEepHeader.rfSilent = word;
349 word = swab16(eep->baseEepHeader.blueToothOptions);
350 eep->baseEepHeader.blueToothOptions = word;
352 word = swab16(eep->baseEepHeader.deviceCap);
353 eep->baseEepHeader.deviceCap = word;
355 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
356 struct modal_eep_header *pModal =
357 &eep->modalHeader[j];
358 integer = swab32(pModal->antCtrlCommon);
359 pModal->antCtrlCommon = integer;
361 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
362 integer = swab32(pModal->antCtrlChain[i]);
363 pModal->antCtrlChain[i] = integer;
365 for (i = 0; i < 3; i++) {
366 word = swab16(pModal->xpaBiasLvlFreq[i]);
367 pModal->xpaBiasLvlFreq[i] = word;
370 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
371 word = swab16(pModal->spurChans[i].spurChan);
372 pModal->spurChans[i].spurChan = word;
377 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
378 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
379 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
380 sum, ah->eep_ops->get_eeprom_ver(ah));
384 /* Enable fixup for AR_AN_TOP2 if necessary */
385 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
386 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
387 (eep->baseEepHeader.pwdclkind == 0))
388 ah->need_an_top2_fixup = 1;
390 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
392 eep->modalHeader[0].xpaBiasLvl = 0;
397 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
398 enum eeprom_param param)
400 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
401 struct modal_eep_header *pModal = eep->modalHeader;
402 struct base_eep_header *pBase = &eep->baseEepHeader;
406 return pModal[0].noiseFloorThreshCh[0];
408 return pModal[1].noiseFloorThreshCh[0];
410 return get_unaligned_be16(pBase->macAddr);
412 return get_unaligned_be16(pBase->macAddr + 2);
414 return get_unaligned_be16(pBase->macAddr + 4);
416 return pBase->regDmn[0];
418 return pBase->regDmn[1];
420 return pBase->deviceCap;
422 return pBase->opCapFlags;
424 return pBase->rfSilent;
434 return AR5416_VER_MASK;
436 return pBase->txMask;
438 return pBase->rxMask;
440 return pBase->fastClk5g;
441 case EEP_RXGAIN_TYPE:
442 return pBase->rxGainType;
443 case EEP_TXGAIN_TYPE:
444 return pBase->txGainType;
446 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
447 return pBase->openLoopPwrCntl ? true : false;
450 case EEP_RC_CHAIN_MASK:
451 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
452 return pBase->rcChainMask;
455 case EEP_DAC_HPWR_5G:
456 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
457 return pBase->dacHiPwrMode_5G;
461 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
462 return pBase->frac_n_5g;
465 case EEP_PWR_TABLE_OFFSET:
466 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
467 return pBase->pwr_table_offset;
469 return AR5416_PWR_TABLE_OFFSET_DB;
475 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
476 struct modal_eep_header *pModal,
477 struct ar5416_eeprom_def *eep,
478 u8 txRxAttenLocal, int regChainOffset, int i)
480 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
481 txRxAttenLocal = pModal->txRxAttenCh[i];
483 if (AR_SREV_9280_20_OR_LATER(ah)) {
484 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
485 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
486 pModal->bswMargin[i]);
487 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
488 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
489 pModal->bswAtten[i]);
490 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
491 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
492 pModal->xatten2Margin[i]);
493 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
494 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
495 pModal->xatten2Db[i]);
497 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
498 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
499 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
500 | SM(pModal-> bswMargin[i],
501 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
502 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
503 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
504 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
505 | SM(pModal->bswAtten[i],
506 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
510 if (AR_SREV_9280_20_OR_LATER(ah)) {
512 AR_PHY_RXGAIN + regChainOffset,
513 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
515 AR_PHY_RXGAIN + regChainOffset,
516 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
519 AR_PHY_RXGAIN + regChainOffset,
520 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
521 ~AR_PHY_RXGAIN_TXRX_ATTEN)
522 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
524 AR_PHY_GAIN_2GHZ + regChainOffset,
525 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
526 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
527 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
531 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
532 struct ath9k_channel *chan)
534 struct modal_eep_header *pModal;
535 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
536 int i, regChainOffset;
539 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
540 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
542 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
544 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
545 if (AR_SREV_9280(ah)) {
550 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
551 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
553 regChainOffset = i * 0x1000;
555 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
556 pModal->antCtrlChain[i]);
558 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
559 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
560 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
561 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
562 SM(pModal->iqCalICh[i],
563 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
564 SM(pModal->iqCalQCh[i],
565 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
567 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
571 if (AR_SREV_9280_20_OR_LATER(ah)) {
572 if (IS_CHAN_2GHZ(chan)) {
573 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
575 AR_AN_RF2G1_CH0_OB_S,
577 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
579 AR_AN_RF2G1_CH0_DB_S,
581 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
583 AR_AN_RF2G1_CH1_OB_S,
585 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
587 AR_AN_RF2G1_CH1_DB_S,
590 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
592 AR_AN_RF5G1_CH0_OB5_S,
594 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
596 AR_AN_RF5G1_CH0_DB5_S,
598 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
600 AR_AN_RF5G1_CH1_OB5_S,
602 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
604 AR_AN_RF5G1_CH1_DB5_S,
607 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
608 AR_AN_TOP2_XPABIAS_LVL,
609 AR_AN_TOP2_XPABIAS_LVL_S,
611 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
612 AR_AN_TOP2_LOCALBIAS,
613 AR_AN_TOP2_LOCALBIAS_S,
615 LNA_CTL_LOCAL_BIAS));
616 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
617 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
620 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
621 pModal->switchSettling);
622 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
623 pModal->adcDesiredSize);
625 if (!AR_SREV_9280_20_OR_LATER(ah))
626 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
627 AR_PHY_DESIRED_SZ_PGA,
628 pModal->pgaDesiredSize);
630 REG_WRITE(ah, AR_PHY_RF_CTL4,
631 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
632 | SM(pModal->txEndToXpaOff,
633 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
634 | SM(pModal->txFrameToXpaOn,
635 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
636 | SM(pModal->txFrameToXpaOn,
637 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
639 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
640 pModal->txEndToRxOn);
642 if (AR_SREV_9280_20_OR_LATER(ah)) {
643 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
645 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
646 AR_PHY_EXT_CCA0_THRESH62,
649 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
651 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
652 AR_PHY_EXT_CCA_THRESH62,
656 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
657 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
658 AR_PHY_TX_END_DATA_START,
659 pModal->txFrameToDataStart);
660 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
661 pModal->txFrameToPaOn);
664 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
665 if (IS_CHAN_HT40(chan))
666 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
667 AR_PHY_SETTLING_SWITCH,
668 pModal->swSettleHt40);
671 if (AR_SREV_9280_20_OR_LATER(ah) &&
672 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
673 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
674 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
678 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
679 if (IS_CHAN_2GHZ(chan))
680 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
681 eep->baseEepHeader.dacLpMode);
682 else if (eep->baseEepHeader.dacHiPwrMode_5G)
683 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
685 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
686 eep->baseEepHeader.dacLpMode);
690 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
691 pModal->miscBits >> 2);
693 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
694 AR_PHY_TX_DESIRED_SCALE_CCK,
695 eep->baseEepHeader.desiredScaleCCK);
699 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
700 struct ath9k_channel *chan)
702 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
703 struct modal_eep_header *pModal;
704 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
707 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
710 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
713 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
715 if (pModal->xpaBiasLvl != 0xff) {
716 biaslevel = pModal->xpaBiasLvl;
718 u16 resetFreqBin, freqBin, freqCount = 0;
719 struct chan_centers centers;
721 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
723 resetFreqBin = FREQ2FBIN(centers.synth_center,
725 freqBin = XPA_LVL_FREQ(0) & 0xff;
726 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
730 while (freqCount < 3) {
731 if (XPA_LVL_FREQ(freqCount) == 0x0)
734 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
735 if (resetFreqBin >= freqBin)
736 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
743 if (IS_CHAN_2GHZ(chan)) {
744 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
745 7, 1) & (~0x18)) | biaslevel << 3;
747 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
748 6, 1) & (~0xc0)) | biaslevel << 6;
753 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
756 u16 pdGainOverlap_t2,
757 int8_t pwr_table_offset,
763 /* Prior to writing the boundaries or the pdadc vs. power table
764 * into the chip registers the default starting point on the pdadc
765 * vs. power table needs to be checked and the curve boundaries
766 * adjusted accordingly
768 if (AR_SREV_9280_20_OR_LATER(ah)) {
771 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
772 /* get the difference in dB */
773 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
774 /* get the number of half dB steps */
776 /* change the original gain boundary settings
777 * by the number of half dB steps
779 for (k = 0; k < numXpdGain; k++)
780 gb[k] = (u16)(gb[k] - *diff);
782 /* Because of a hardware limitation, ensure the gain boundary
783 * is not larger than (63 - overlap)
785 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
787 for (k = 0; k < numXpdGain; k++)
788 gb[k] = (u16)min(gb_limit, gb[k]);
794 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
795 int8_t pwr_table_offset,
799 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
802 /* If this is a board that has a pwrTableOffset that differs from
803 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
804 * pdadc vs pwr table needs to be adjusted prior to writing to the
807 if (AR_SREV_9280_20_OR_LATER(ah)) {
808 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
809 /* shift the table to start at the new offset */
810 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
811 pdadcValues[k] = pdadcValues[k + diff];
814 /* fill the back of the table */
815 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
816 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
823 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
824 struct ath9k_channel *chan)
826 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
827 #define SM_PDGAIN_B(x, y) \
828 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
829 struct ath_common *common = ath9k_hw_common(ah);
830 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
831 struct cal_data_per_freq *pRawDataset;
832 u8 *pCalBChans = NULL;
833 u16 pdGainOverlap_t2;
834 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
835 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
838 u16 numXpdGain, xpdMask;
839 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
840 u32 reg32, regOffset, regChainOffset;
842 int8_t pwr_table_offset;
844 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
845 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
847 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
849 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
850 AR5416_EEP_MINOR_VER_2) {
852 pEepData->modalHeader[modalIdx].pdGainOverlap;
854 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
855 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
858 if (IS_CHAN_2GHZ(chan)) {
859 pCalBChans = pEepData->calFreqPier2G;
860 numPiers = AR5416_NUM_2G_CAL_PIERS;
862 pCalBChans = pEepData->calFreqPier5G;
863 numPiers = AR5416_NUM_5G_CAL_PIERS;
866 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
867 pRawDataset = pEepData->calPierData2G[0];
868 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
869 pRawDataset)->vpdPdg[0][0];
874 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
875 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
876 if (numXpdGain >= AR5416_NUM_PD_GAINS)
878 xpdGainValues[numXpdGain] =
879 (u16)(AR5416_PD_GAINS_IN_MASK - i);
884 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
885 (numXpdGain - 1) & 0x3);
886 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
888 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
890 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
893 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
894 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
896 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
898 regChainOffset = i * 0x1000;
900 if (pEepData->baseEepHeader.txMask & (1 << i)) {
901 if (IS_CHAN_2GHZ(chan))
902 pRawDataset = pEepData->calPierData2G[i];
904 pRawDataset = pEepData->calPierData5G[i];
907 if (OLC_FOR_AR9280_20_LATER) {
911 ath9k_get_txgain_index(ah, chan,
912 (struct calDataPerFreqOpLoop *)pRawDataset,
913 pCalBChans, numPiers, &txPower, &pcdacIdx);
914 ath9k_olc_get_pdadcs(ah, pcdacIdx,
915 txPower/2, pdadcValues);
917 ath9k_hw_get_gain_boundaries_pdadcs(ah,
919 pCalBChans, numPiers,
926 diff = ath9k_change_gain_boundary_setting(ah,
933 ENABLE_REGWRITE_BUFFER(ah);
935 if (OLC_FOR_AR9280_20_LATER) {
937 AR_PHY_TPCRG5 + regChainOffset,
939 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
940 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
941 SM_PD_GAIN(3) | SM_PD_GAIN(4));
944 AR_PHY_TPCRG5 + regChainOffset,
946 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
953 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
956 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
957 for (j = 0; j < 32; j++) {
958 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
959 REG_WRITE(ah, regOffset, reg32);
961 ath_dbg(common, ATH_DBG_EEPROM,
962 "PDADC (%d,%4x): %4.4x %8.8x\n",
963 i, regChainOffset, regOffset,
965 ath_dbg(common, ATH_DBG_EEPROM,
966 "PDADC: Chain %d | PDADC %3d "
967 "Value %3d | PDADC %3d Value %3d | "
968 "PDADC %3d Value %3d | PDADC %3d "
970 i, 4 * j, pdadcValues[4 * j],
971 4 * j + 1, pdadcValues[4 * j + 1],
972 4 * j + 2, pdadcValues[4 * j + 2],
973 4 * j + 3, pdadcValues[4 * j + 3]);
977 REGWRITE_BUFFER_FLUSH(ah);
985 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
986 struct ath9k_channel *chan,
989 u16 AntennaReduction,
990 u16 twiceMaxRegulatoryPower,
993 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
994 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
996 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
997 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
998 u16 twiceMaxEdgePower = MAX_RATE_POWER;
999 static const u16 tpScaleReductionTable[5] =
1000 { 0, 3, 6, 9, MAX_RATE_POWER };
1003 int16_t twiceLargestAntenna;
1004 struct cal_ctl_data *rep;
1005 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1008 struct cal_target_power_leg targetPowerOfdmExt = {
1009 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1012 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1015 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1016 static const u16 ctlModesFor11a[] = {
1017 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1019 static const u16 ctlModesFor11g[] = {
1020 CTL_11B, CTL_11G, CTL_2GHT20,
1021 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1024 const u16 *pCtlMode;
1026 struct chan_centers centers;
1028 u16 twiceMinEdgePower;
1030 tx_chainmask = ah->txchainmask;
1032 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1034 twiceLargestAntenna = max(
1035 pEepData->modalHeader
1036 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1037 pEepData->modalHeader
1038 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1040 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1041 pEepData->modalHeader
1042 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1044 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1045 twiceLargestAntenna, 0);
1047 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1049 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1050 maxRegAllowedPower -=
1051 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1054 scaledPower = min(powerLimit, maxRegAllowedPower);
1056 switch (ar5416_get_ntxchains(tx_chainmask)) {
1060 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
1061 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1066 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
1067 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1073 if (IS_CHAN_2GHZ(chan)) {
1074 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1075 SUB_NUM_CTL_MODES_AT_2G_40;
1076 pCtlMode = ctlModesFor11g;
1078 ath9k_hw_get_legacy_target_powers(ah, chan,
1079 pEepData->calTargetPowerCck,
1080 AR5416_NUM_2G_CCK_TARGET_POWERS,
1081 &targetPowerCck, 4, false);
1082 ath9k_hw_get_legacy_target_powers(ah, chan,
1083 pEepData->calTargetPower2G,
1084 AR5416_NUM_2G_20_TARGET_POWERS,
1085 &targetPowerOfdm, 4, false);
1086 ath9k_hw_get_target_powers(ah, chan,
1087 pEepData->calTargetPower2GHT20,
1088 AR5416_NUM_2G_20_TARGET_POWERS,
1089 &targetPowerHt20, 8, false);
1091 if (IS_CHAN_HT40(chan)) {
1092 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1093 ath9k_hw_get_target_powers(ah, chan,
1094 pEepData->calTargetPower2GHT40,
1095 AR5416_NUM_2G_40_TARGET_POWERS,
1096 &targetPowerHt40, 8, true);
1097 ath9k_hw_get_legacy_target_powers(ah, chan,
1098 pEepData->calTargetPowerCck,
1099 AR5416_NUM_2G_CCK_TARGET_POWERS,
1100 &targetPowerCckExt, 4, true);
1101 ath9k_hw_get_legacy_target_powers(ah, chan,
1102 pEepData->calTargetPower2G,
1103 AR5416_NUM_2G_20_TARGET_POWERS,
1104 &targetPowerOfdmExt, 4, true);
1107 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1108 SUB_NUM_CTL_MODES_AT_5G_40;
1109 pCtlMode = ctlModesFor11a;
1111 ath9k_hw_get_legacy_target_powers(ah, chan,
1112 pEepData->calTargetPower5G,
1113 AR5416_NUM_5G_20_TARGET_POWERS,
1114 &targetPowerOfdm, 4, false);
1115 ath9k_hw_get_target_powers(ah, chan,
1116 pEepData->calTargetPower5GHT20,
1117 AR5416_NUM_5G_20_TARGET_POWERS,
1118 &targetPowerHt20, 8, false);
1120 if (IS_CHAN_HT40(chan)) {
1121 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1122 ath9k_hw_get_target_powers(ah, chan,
1123 pEepData->calTargetPower5GHT40,
1124 AR5416_NUM_5G_40_TARGET_POWERS,
1125 &targetPowerHt40, 8, true);
1126 ath9k_hw_get_legacy_target_powers(ah, chan,
1127 pEepData->calTargetPower5G,
1128 AR5416_NUM_5G_20_TARGET_POWERS,
1129 &targetPowerOfdmExt, 4, true);
1133 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1134 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1135 (pCtlMode[ctlMode] == CTL_2GHT40);
1137 freq = centers.synth_center;
1138 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1139 freq = centers.ext_center;
1141 freq = centers.ctl_center;
1143 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1144 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1145 twiceMaxEdgePower = MAX_RATE_POWER;
1147 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1148 if ((((cfgCtl & ~CTL_MODE_M) |
1149 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1150 pEepData->ctlIndex[i]) ||
1151 (((cfgCtl & ~CTL_MODE_M) |
1152 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1153 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1154 rep = &(pEepData->ctlData[i]);
1156 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1157 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1158 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1160 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1161 twiceMaxEdgePower = min(twiceMaxEdgePower,
1164 twiceMaxEdgePower = twiceMinEdgePower;
1170 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1172 switch (pCtlMode[ctlMode]) {
1174 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1175 targetPowerCck.tPow2x[i] =
1176 min((u16)targetPowerCck.tPow2x[i],
1182 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1183 targetPowerOfdm.tPow2x[i] =
1184 min((u16)targetPowerOfdm.tPow2x[i],
1190 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1191 targetPowerHt20.tPow2x[i] =
1192 min((u16)targetPowerHt20.tPow2x[i],
1197 targetPowerCckExt.tPow2x[0] = min((u16)
1198 targetPowerCckExt.tPow2x[0],
1203 targetPowerOfdmExt.tPow2x[0] = min((u16)
1204 targetPowerOfdmExt.tPow2x[0],
1209 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1210 targetPowerHt40.tPow2x[i] =
1211 min((u16)targetPowerHt40.tPow2x[i],
1220 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1221 ratesArray[rate18mb] = ratesArray[rate24mb] =
1222 targetPowerOfdm.tPow2x[0];
1223 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1224 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1225 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1226 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1228 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1229 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1231 if (IS_CHAN_2GHZ(chan)) {
1232 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1233 ratesArray[rate2s] = ratesArray[rate2l] =
1234 targetPowerCck.tPow2x[1];
1235 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1236 targetPowerCck.tPow2x[2];
1237 ratesArray[rate11s] = ratesArray[rate11l] =
1238 targetPowerCck.tPow2x[3];
1240 if (IS_CHAN_HT40(chan)) {
1241 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1242 ratesArray[rateHt40_0 + i] =
1243 targetPowerHt40.tPow2x[i];
1245 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1246 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1247 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1248 if (IS_CHAN_2GHZ(chan)) {
1249 ratesArray[rateExtCck] =
1250 targetPowerCckExt.tPow2x[0];
1255 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1256 struct ath9k_channel *chan,
1258 u8 twiceAntennaReduction,
1259 u8 twiceMaxRegulatoryPower,
1260 u8 powerLimit, bool test)
1262 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1263 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1264 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1265 struct modal_eep_header *pModal =
1266 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1267 int16_t ratesArray[Ar5416RateSize];
1268 u8 ht40PowerIncForPdadc = 2;
1269 int i, cck_ofdm_delta = 0;
1271 memset(ratesArray, 0, sizeof(ratesArray));
1273 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1274 AR5416_EEP_MINOR_VER_2) {
1275 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1278 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1279 &ratesArray[0], cfgCtl,
1280 twiceAntennaReduction,
1281 twiceMaxRegulatoryPower,
1284 ath9k_hw_set_def_power_cal_table(ah, chan);
1286 regulatory->max_power_level = 0;
1287 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1288 if (ratesArray[i] > MAX_RATE_POWER)
1289 ratesArray[i] = MAX_RATE_POWER;
1290 if (ratesArray[i] > regulatory->max_power_level)
1291 regulatory->max_power_level = ratesArray[i];
1294 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1298 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1301 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1304 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1305 "Invalid chainmask configuration\n");
1312 if (AR_SREV_9280_20_OR_LATER(ah)) {
1313 for (i = 0; i < Ar5416RateSize; i++) {
1314 int8_t pwr_table_offset;
1316 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1317 EEP_PWR_TABLE_OFFSET);
1318 ratesArray[i] -= pwr_table_offset * 2;
1322 ENABLE_REGWRITE_BUFFER(ah);
1324 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1325 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1326 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1327 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1328 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1329 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1330 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1331 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1332 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1333 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1335 if (IS_CHAN_2GHZ(chan)) {
1336 if (OLC_FOR_AR9280_20_LATER) {
1338 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1339 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1340 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1341 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1342 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1343 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1344 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1345 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1346 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1347 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1349 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1350 ATH9K_POW_SM(ratesArray[rate2s], 24)
1351 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1352 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1353 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1354 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1355 ATH9K_POW_SM(ratesArray[rate11s], 24)
1356 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1357 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1358 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1362 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1363 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1364 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1365 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1366 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1367 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1368 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1369 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1370 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1371 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1373 if (IS_CHAN_HT40(chan)) {
1374 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1375 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1376 ht40PowerIncForPdadc, 24)
1377 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1378 ht40PowerIncForPdadc, 16)
1379 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1380 ht40PowerIncForPdadc, 8)
1381 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1382 ht40PowerIncForPdadc, 0));
1383 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1384 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1385 ht40PowerIncForPdadc, 24)
1386 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1387 ht40PowerIncForPdadc, 16)
1388 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1389 ht40PowerIncForPdadc, 8)
1390 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1391 ht40PowerIncForPdadc, 0));
1392 if (OLC_FOR_AR9280_20_LATER) {
1393 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1394 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1395 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1396 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1397 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1399 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1400 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1401 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1402 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1403 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1407 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1408 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1409 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1411 REGWRITE_BUFFER_FLUSH(ah);
1414 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1416 #define EEP_DEF_SPURCHAN \
1417 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1418 struct ath_common *common = ath9k_hw_common(ah);
1420 u16 spur_val = AR_NO_SPUR;
1422 ath_dbg(common, ATH_DBG_ANI,
1423 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1424 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1426 switch (ah->config.spurmode) {
1429 case SPUR_ENABLE_IOCTL:
1430 spur_val = ah->config.spurchans[i][is2GHz];
1431 ath_dbg(common, ATH_DBG_ANI,
1432 "Getting spur val from new loc. %d\n", spur_val);
1434 case SPUR_ENABLE_EEPROM:
1435 spur_val = EEP_DEF_SPURCHAN;
1441 #undef EEP_DEF_SPURCHAN
1444 const struct eeprom_ops eep_def_ops = {
1445 .check_eeprom = ath9k_hw_def_check_eeprom,
1446 .get_eeprom = ath9k_hw_def_get_eeprom,
1447 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1448 .dump_eeprom = ath9k_hw_def_dump_eeprom,
1449 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1450 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1451 .set_board_values = ath9k_hw_def_set_board_values,
1452 .set_addac = ath9k_hw_def_set_addac,
1453 .set_txpower = ath9k_hw_def_set_txpower,
1454 .get_spur_channel = ath9k_hw_def_get_spur_channel