2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102 if (conf_is_ht40(conf))
106 if (IS_CHAN_HALF_RATE(ah->curchan))
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
112 common->clockrate = clockrate;
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
117 struct ath_common *common = ath9k_hw_common(ah);
119 return usecs * common->clockrate;
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 BUG_ON(timeout < AH_TIME_QUANTUM);
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
132 udelay(AH_TIME_QUANTUM);
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
141 EXPORT_SYMBOL(ath9k_hw_wait);
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
154 REGWRITE_BUFFER_FLUSH(ah);
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 u32 frameLen, u16 rateix,
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
289 if (!AR_SREV_9100(ah))
290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
292 ah->hw_version.macRev = val & AR_SREV_REVISION;
294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->is_pciexpress = true;
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
305 if (!AR_SREV_5416(ah))
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
321 static void ath9k_hw_aspm_init(struct ath_hw *ah)
323 struct ath_common *common = ath9k_hw_common(ah);
325 if (common->bus_ops->aspm_init)
326 common->bus_ops->aspm_init(common);
329 /* This should work for all families including legacy */
330 static bool ath9k_hw_chip_test(struct ath_hw *ah)
332 struct ath_common *common = ath9k_hw_common(ah);
333 u32 regAddr[2] = { AR_STA_ID0 };
335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
340 if (!AR_SREV_9300_20_OR_LATER(ah)) {
342 regAddr[1] = AR_PHY_BASE + (8 << 2);
346 for (i = 0; i < loop_max; i++) {
347 u32 addr = regAddr[i];
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
358 addr, wrData, rdData);
362 for (j = 0; j < 4; j++) {
363 wrData = patternData[j];
364 REG_WRITE(ah, addr, wrData);
365 rdData = REG_READ(ah, addr);
366 if (wrData != rdData) {
368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
369 addr, wrData, rdData);
373 REG_WRITE(ah, regAddr[i], regHold[i]);
380 static void ath9k_hw_init_config(struct ath_hw *ah)
384 ah->config.dma_beacon_response_time = 2;
385 ah->config.sw_beacon_response_time = 10;
386 ah->config.additional_swba_backoff = 0;
387 ah->config.ack_6mb = 0x0;
388 ah->config.cwm_ignore_extcca = 0;
389 ah->config.pcie_clock_req = 0;
390 ah->config.pcie_waen = 0;
391 ah->config.analog_shiftreg = 1;
392 ah->config.enable_ani = true;
394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
395 ah->config.spurchans[i][0] = AR_NO_SPUR;
396 ah->config.spurchans[i][1] = AR_NO_SPUR;
399 /* PAPRD needs some more work to be enabled */
400 ah->config.paprd_disable = 1;
402 ah->config.rx_intr_mitigation = true;
403 ah->config.pcieSerDesWrite = true;
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
421 if (num_possible_cpus() > 1)
422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
425 static void ath9k_hw_init_defaults(struct ath_hw *ah)
427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
429 regulatory->country_code = CTRY_DEFAULT;
430 regulatory->power_limit = MAX_RATE_POWER;
431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
433 ah->hw_version.magic = AR5416_MAGIC;
434 ah->hw_version.subvendorid = 0;
437 ah->sta_id1_defaults =
438 AR_STA_ID1_CRPT_MIC_ENABLE |
439 AR_STA_ID1_MCAST_KSRCH;
440 if (AR_SREV_9100(ah))
441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
442 ah->enable_32kHz_clock = DONT_USE_32KHZ;
444 ah->globaltxtimeout = (u32) -1;
445 ah->power_mode = ATH9K_PM_UNDEFINED;
448 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
450 struct ath_common *common = ath9k_hw_common(ah);
454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
457 for (i = 0; i < 3; i++) {
458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
460 common->macaddr[2 * i] = eeval >> 8;
461 common->macaddr[2 * i + 1] = eeval & 0xff;
463 if (sum == 0 || sum == 0xffff * 3)
464 return -EADDRNOTAVAIL;
469 static int ath9k_hw_post_init(struct ath_hw *ah)
471 struct ath_common *common = ath9k_hw_common(ah);
474 if (common->bus_ops->ath_bus_type != ATH_USB) {
475 if (!ath9k_hw_chip_test(ah))
479 if (!AR_SREV_9300_20_OR_LATER(ah)) {
480 ecode = ar9002_hw_rf_claim(ah);
485 ecode = ath9k_hw_eeprom_init(ah);
489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
490 "Eeprom VER: %d, REV: %d\n",
491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
494 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
496 ath_err(ath9k_hw_common(ah),
497 "Failed allocating banks for external radio\n");
498 ath9k_hw_rf_free_ext_banks(ah);
502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
503 ath9k_hw_ani_setup(ah);
504 ath9k_hw_ani_init(ah);
510 static void ath9k_hw_attach_ops(struct ath_hw *ah)
512 if (AR_SREV_9300_20_OR_LATER(ah))
513 ar9003_hw_attach_ops(ah);
515 ar9002_hw_attach_ops(ah);
518 /* Called for all hardware families */
519 static int __ath9k_hw_init(struct ath_hw *ah)
521 struct ath_common *common = ath9k_hw_common(ah);
524 ath9k_hw_read_revisions(ah);
527 * Read back AR_WA into a permanent copy and set bits 14 and 17.
528 * We need to do this to avoid RMW of this register. We cannot
529 * read the reg when chip is asleep.
531 ah->WARegVal = REG_READ(ah, AR_WA);
532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
533 AR_WA_ASPM_TIMER_BASED_DISABLE);
535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
536 ath_err(common, "Couldn't reset chip\n");
540 ath9k_hw_init_defaults(ah);
541 ath9k_hw_init_config(ah);
543 ath9k_hw_attach_ops(ah);
545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
546 ath_err(common, "Couldn't wakeup chip\n");
550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
553 !ah->is_pciexpress)) {
554 ah->config.serialize_regmode =
557 ah->config.serialize_regmode =
562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
563 ah->config.serialize_regmode);
565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
570 switch (ah->hw_version.macVersion) {
571 case AR_SREV_VERSION_5416_PCI:
572 case AR_SREV_VERSION_5416_PCIE:
573 case AR_SREV_VERSION_9160:
574 case AR_SREV_VERSION_9100:
575 case AR_SREV_VERSION_9280:
576 case AR_SREV_VERSION_9285:
577 case AR_SREV_VERSION_9287:
578 case AR_SREV_VERSION_9271:
579 case AR_SREV_VERSION_9300:
580 case AR_SREV_VERSION_9330:
581 case AR_SREV_VERSION_9485:
582 case AR_SREV_VERSION_9340:
586 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
587 ah->hw_version.macVersion, ah->hw_version.macRev);
591 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
593 ah->is_pciexpress = false;
595 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
596 ath9k_hw_init_cal_settings(ah);
598 ah->ani_function = ATH9K_ANI_ALL;
599 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
601 if (!AR_SREV_9300_20_OR_LATER(ah))
602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
604 ath9k_hw_init_mode_regs(ah);
606 if (!ah->is_pciexpress)
607 ath9k_hw_disablepcie(ah);
609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ar9002_hw_cck_chan14_spread(ah);
612 r = ath9k_hw_post_init(ah);
616 ath9k_hw_init_mode_gain_regs(ah);
617 r = ath9k_hw_fill_cap_info(ah);
621 if (ah->is_pciexpress)
622 ath9k_hw_aspm_init(ah);
624 r = ath9k_hw_init_macaddr(ah);
626 ath_err(common, "Failed to initialize MAC address\n");
630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
631 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
633 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
635 if (AR_SREV_9330(ah))
636 ah->bb_watchdog_timeout_ms = 85;
638 ah->bb_watchdog_timeout_ms = 25;
640 common->state = ATH_HW_INITIALIZED;
645 int ath9k_hw_init(struct ath_hw *ah)
648 struct ath_common *common = ath9k_hw_common(ah);
650 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
651 switch (ah->hw_version.devid) {
652 case AR5416_DEVID_PCI:
653 case AR5416_DEVID_PCIE:
654 case AR5416_AR9100_DEVID:
655 case AR9160_DEVID_PCI:
656 case AR9280_DEVID_PCI:
657 case AR9280_DEVID_PCIE:
658 case AR9285_DEVID_PCIE:
659 case AR9287_DEVID_PCI:
660 case AR9287_DEVID_PCIE:
661 case AR2427_DEVID_PCIE:
662 case AR9300_DEVID_PCIE:
663 case AR9300_DEVID_AR9485_PCIE:
664 case AR9300_DEVID_AR9330:
665 case AR9300_DEVID_AR9340:
666 case AR9300_DEVID_AR9580:
669 if (common->bus_ops->ath_bus_type == ATH_USB)
671 ath_err(common, "Hardware device ID 0x%04x not supported\n",
672 ah->hw_version.devid);
676 ret = __ath9k_hw_init(ah);
679 "Unable to initialize hardware; initialization status: %d\n",
686 EXPORT_SYMBOL(ath9k_hw_init);
688 static void ath9k_hw_init_qos(struct ath_hw *ah)
690 ENABLE_REGWRITE_BUFFER(ah);
692 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
693 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
695 REG_WRITE(ah, AR_QOS_NO_ACK,
696 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
697 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
698 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
700 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
701 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
702 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
703 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
704 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
706 REGWRITE_BUFFER_FLUSH(ah);
709 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
711 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
713 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
715 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
718 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
720 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
722 static void ath9k_hw_init_pll(struct ath_hw *ah,
723 struct ath9k_channel *chan)
727 if (AR_SREV_9485(ah)) {
729 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
731 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_DPLL2_KD, 0x40);
734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
735 AR_CH0_DPLL2_KI, 0x4);
737 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
738 AR_CH0_BB_DPLL1_REFDIV, 0x5);
739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
740 AR_CH0_BB_DPLL1_NINI, 0x58);
741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
742 AR_CH0_BB_DPLL1_NFRAC, 0x0);
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
745 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
747 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
749 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
751 /* program BB PLL phase_shift to 0x6 */
752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
753 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
756 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
758 } else if (AR_SREV_9330(ah)) {
759 u32 ddr_dpll2, pll_control2, kd;
761 if (ah->is_clk_25mhz) {
762 ddr_dpll2 = 0x18e82f01;
763 pll_control2 = 0xe04a3d;
766 ddr_dpll2 = 0x19e82f01;
767 pll_control2 = 0x886666;
771 /* program DDR PLL ki and kd value */
772 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
774 /* program DDR PLL phase_shift */
775 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
776 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
778 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
781 /* program refdiv, nint, frac to RTC register */
782 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
784 /* program BB PLL kd and ki value */
785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
788 /* program BB PLL phase_shift */
789 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
790 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
791 } else if (AR_SREV_9340(ah)) {
792 u32 regval, pll2_divint, pll2_divfrac, refdiv;
794 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
797 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
800 if (ah->is_clk_25mhz) {
802 pll2_divfrac = 0x1eb85;
810 regval = REG_READ(ah, AR_PHY_PLL_MODE);
811 regval |= (0x1 << 16);
812 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
815 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
816 (pll2_divint << 18) | pll2_divfrac);
819 regval = REG_READ(ah, AR_PHY_PLL_MODE);
820 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
821 (0x4 << 26) | (0x18 << 19);
822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
823 REG_WRITE(ah, AR_PHY_PLL_MODE,
824 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
828 pll = ath9k_hw_compute_pll_control(ah, chan);
830 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
832 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
835 /* Switch the core clock for ar9271 to 117Mhz */
836 if (AR_SREV_9271(ah)) {
838 REG_WRITE(ah, 0x50040, 0x304);
841 udelay(RTC_PLL_SETTLE_DELAY);
843 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
845 if (AR_SREV_9340(ah)) {
846 if (ah->is_clk_25mhz) {
847 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
848 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
849 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
851 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
852 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
853 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
859 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
860 enum nl80211_iftype opmode)
862 u32 sync_default = AR_INTR_SYNC_DEFAULT;
863 u32 imr_reg = AR_IMR_TXERR |
869 if (AR_SREV_9340(ah))
870 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
872 if (AR_SREV_9300_20_OR_LATER(ah)) {
873 imr_reg |= AR_IMR_RXOK_HP;
874 if (ah->config.rx_intr_mitigation)
875 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
877 imr_reg |= AR_IMR_RXOK_LP;
880 if (ah->config.rx_intr_mitigation)
881 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
883 imr_reg |= AR_IMR_RXOK;
886 if (ah->config.tx_intr_mitigation)
887 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
889 imr_reg |= AR_IMR_TXOK;
891 if (opmode == NL80211_IFTYPE_AP)
892 imr_reg |= AR_IMR_MIB;
894 ENABLE_REGWRITE_BUFFER(ah);
896 REG_WRITE(ah, AR_IMR, imr_reg);
897 ah->imrs2_reg |= AR_IMR_S2_GTT;
898 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
900 if (!AR_SREV_9100(ah)) {
901 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
902 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
903 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
906 REGWRITE_BUFFER_FLUSH(ah);
908 if (AR_SREV_9300_20_OR_LATER(ah)) {
909 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
910 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
911 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
912 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
916 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
918 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
919 val = min(val, (u32) 0xFFFF);
920 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
923 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
925 u32 val = ath9k_hw_mac_to_clks(ah, us);
926 val = min(val, (u32) 0xFFFF);
927 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
930 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
932 u32 val = ath9k_hw_mac_to_clks(ah, us);
933 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
934 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
937 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
939 u32 val = ath9k_hw_mac_to_clks(ah, us);
940 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
941 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
944 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
947 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
948 "bad global tx timeout %u\n", tu);
949 ah->globaltxtimeout = (u32) -1;
952 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
953 ah->globaltxtimeout = tu;
958 void ath9k_hw_init_global_settings(struct ath_hw *ah)
960 struct ath_common *common = ath9k_hw_common(ah);
961 struct ieee80211_conf *conf = &common->hw->conf;
962 const struct ath9k_channel *chan = ah->curchan;
966 int rx_lat = 0, tx_lat = 0, eifs = 0;
969 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
975 if (ah->misc_mode != 0)
976 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
981 if (IS_CHAN_HALF_RATE(chan)) {
985 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
990 } else if (IS_CHAN_QUARTER_RATE(chan)) {
994 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1000 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/common->clockrate;
1001 reg = REG_READ(ah, AR_USEC);
1002 rx_lat = MS(reg, AR_USEC_RX_LAT);
1003 tx_lat = MS(reg, AR_USEC_TX_LAT);
1005 slottime = ah->slottime;
1006 if (IS_CHAN_5GHZ(chan))
1012 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1013 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1016 * Workaround for early ACK timeouts, add an offset to match the
1017 * initval's 64us ack timeout value.
1018 * This was initially only meant to work around an issue with delayed
1019 * BA frames in some implementations, but it has been found to fix ACK
1020 * timeout issues in other cases as well.
1022 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1023 acktimeout += 64 - sifstime - ah->slottime;
1025 ath9k_hw_set_sifs_time(ah, sifstime);
1026 ath9k_hw_setslottime(ah, slottime);
1027 ath9k_hw_set_ack_timeout(ah, acktimeout);
1028 ath9k_hw_set_cts_timeout(ah, acktimeout);
1029 if (ah->globaltxtimeout != (u32) -1)
1030 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1032 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1033 REG_RMW(ah, AR_USEC,
1034 (common->clockrate - 1) |
1035 SM(rx_lat, AR_USEC_RX_LAT) |
1036 SM(tx_lat, AR_USEC_TX_LAT),
1037 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1040 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1042 void ath9k_hw_deinit(struct ath_hw *ah)
1044 struct ath_common *common = ath9k_hw_common(ah);
1046 if (common->state < ATH_HW_INITIALIZED)
1049 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1052 ath9k_hw_rf_free_ext_banks(ah);
1054 EXPORT_SYMBOL(ath9k_hw_deinit);
1060 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1062 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1064 if (IS_CHAN_B(chan))
1066 else if (IS_CHAN_G(chan))
1074 /****************************************/
1075 /* Reset and Channel Switching Routines */
1076 /****************************************/
1078 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1080 struct ath_common *common = ath9k_hw_common(ah);
1082 ENABLE_REGWRITE_BUFFER(ah);
1085 * set AHB_MODE not to do cacheline prefetches
1087 if (!AR_SREV_9300_20_OR_LATER(ah))
1088 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1091 * let mac dma reads be in 128 byte chunks
1093 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1095 REGWRITE_BUFFER_FLUSH(ah);
1098 * Restore TX Trigger Level to its pre-reset value.
1099 * The initial value depends on whether aggregation is enabled, and is
1100 * adjusted whenever underruns are detected.
1102 if (!AR_SREV_9300_20_OR_LATER(ah))
1103 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1105 ENABLE_REGWRITE_BUFFER(ah);
1108 * let mac dma writes be in 128 byte chunks
1110 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1113 * Setup receive FIFO threshold to hold off TX activities
1115 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1117 if (AR_SREV_9300_20_OR_LATER(ah)) {
1118 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1119 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1121 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1122 ah->caps.rx_status_len);
1126 * reduce the number of usable entries in PCU TXBUF to avoid
1127 * wrap around issues.
1129 if (AR_SREV_9285(ah)) {
1130 /* For AR9285 the number of Fifos are reduced to half.
1131 * So set the usable tx buf size also to half to
1132 * avoid data/delimiter underruns
1134 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1135 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1136 } else if (!AR_SREV_9271(ah)) {
1137 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1138 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1141 REGWRITE_BUFFER_FLUSH(ah);
1143 if (AR_SREV_9300_20_OR_LATER(ah))
1144 ath9k_hw_reset_txstatus_ring(ah);
1147 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1149 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1150 u32 set = AR_STA_ID1_KSRCH_MODE;
1153 case NL80211_IFTYPE_ADHOC:
1154 case NL80211_IFTYPE_MESH_POINT:
1155 set |= AR_STA_ID1_ADHOC;
1156 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1158 case NL80211_IFTYPE_AP:
1159 set |= AR_STA_ID1_STA_AP;
1161 case NL80211_IFTYPE_STATION:
1162 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1165 if (!ah->is_monitoring)
1169 REG_RMW(ah, AR_STA_ID1, set, mask);
1172 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1173 u32 *coef_mantissa, u32 *coef_exponent)
1175 u32 coef_exp, coef_man;
1177 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1178 if ((coef_scaled >> coef_exp) & 0x1)
1181 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1183 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1185 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1186 *coef_exponent = coef_exp - 16;
1189 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1194 if (AR_SREV_9100(ah)) {
1195 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1196 AR_RTC_DERIVED_CLK_PERIOD, 1);
1197 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1200 ENABLE_REGWRITE_BUFFER(ah);
1202 if (AR_SREV_9300_20_OR_LATER(ah)) {
1203 REG_WRITE(ah, AR_WA, ah->WARegVal);
1207 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1208 AR_RTC_FORCE_WAKE_ON_INT);
1210 if (AR_SREV_9100(ah)) {
1211 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1212 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1214 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1216 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1217 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1219 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1222 if (!AR_SREV_9300_20_OR_LATER(ah))
1224 REG_WRITE(ah, AR_RC, val);
1226 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1227 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1229 rst_flags = AR_RTC_RC_MAC_WARM;
1230 if (type == ATH9K_RESET_COLD)
1231 rst_flags |= AR_RTC_RC_MAC_COLD;
1234 if (AR_SREV_9330(ah)) {
1239 * call external reset function to reset WMAC if:
1240 * - doing a cold reset
1241 * - we have pending frames in the TX queues
1244 for (i = 0; i < AR_NUM_QCU; i++) {
1245 npend = ath9k_hw_numtxpending(ah, i);
1250 if (ah->external_reset &&
1251 (npend || type == ATH9K_RESET_COLD)) {
1254 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1255 "reset MAC via external reset\n");
1257 reset_err = ah->external_reset();
1259 ath_err(ath9k_hw_common(ah),
1260 "External reset failed, err=%d\n",
1265 REG_WRITE(ah, AR_RTC_RESET, 1);
1269 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1271 REGWRITE_BUFFER_FLUSH(ah);
1275 REG_WRITE(ah, AR_RTC_RC, 0);
1276 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1277 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1278 "RTC stuck in MAC reset\n");
1282 if (!AR_SREV_9100(ah))
1283 REG_WRITE(ah, AR_RC, 0);
1285 if (AR_SREV_9100(ah))
1291 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1293 ENABLE_REGWRITE_BUFFER(ah);
1295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1303 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1304 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1306 REG_WRITE(ah, AR_RTC_RESET, 0);
1308 REGWRITE_BUFFER_FLUSH(ah);
1310 if (!AR_SREV_9300_20_OR_LATER(ah))
1313 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1314 REG_WRITE(ah, AR_RC, 0);
1316 REG_WRITE(ah, AR_RTC_RESET, 1);
1318 if (!ath9k_hw_wait(ah,
1323 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1324 "RTC not waking up\n");
1328 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1331 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1333 if (AR_SREV_9300_20_OR_LATER(ah)) {
1334 REG_WRITE(ah, AR_WA, ah->WARegVal);
1338 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1339 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1342 case ATH9K_RESET_POWER_ON:
1343 return ath9k_hw_set_reset_power_on(ah);
1344 case ATH9K_RESET_WARM:
1345 case ATH9K_RESET_COLD:
1346 return ath9k_hw_set_reset(ah, type);
1352 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1353 struct ath9k_channel *chan)
1355 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1356 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1358 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1361 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1364 ah->chip_fullsleep = false;
1365 ath9k_hw_init_pll(ah, chan);
1366 ath9k_hw_set_rfmode(ah, chan);
1371 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1372 struct ath9k_channel *chan)
1374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1375 struct ath_common *common = ath9k_hw_common(ah);
1376 struct ieee80211_channel *channel = chan->chan;
1380 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1381 if (ath9k_hw_numtxpending(ah, qnum)) {
1382 ath_dbg(common, ATH_DBG_QUEUE,
1383 "Transmit frames pending on queue %d\n", qnum);
1388 if (!ath9k_hw_rfbus_req(ah)) {
1389 ath_err(common, "Could not kill baseband RX\n");
1393 ath9k_hw_set_channel_regs(ah, chan);
1395 r = ath9k_hw_rf_set_freq(ah, chan);
1397 ath_err(common, "Failed to set channel\n");
1400 ath9k_hw_set_clockrate(ah);
1402 ah->eep_ops->set_txpower(ah, chan,
1403 ath9k_regd_get_ctl(regulatory, chan),
1404 channel->max_antenna_gain * 2,
1405 channel->max_power * 2,
1406 min((u32) MAX_RATE_POWER,
1407 (u32) regulatory->power_limit), false);
1409 ath9k_hw_rfbus_done(ah);
1411 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1412 ath9k_hw_set_delta_slope(ah, chan);
1414 ath9k_hw_spur_mitigate_freq(ah, chan);
1419 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1421 u32 gpio_mask = ah->gpio_mask;
1424 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1425 if (!(gpio_mask & 1))
1428 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1429 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1433 bool ath9k_hw_check_alive(struct ath_hw *ah)
1438 if (AR_SREV_9285_12_OR_LATER(ah))
1442 reg = REG_READ(ah, AR_OBS_BUS_1);
1444 if ((reg & 0x7E7FFFEF) == 0x00702400)
1447 switch (reg & 0x7E000B00) {
1455 } while (count-- > 0);
1459 EXPORT_SYMBOL(ath9k_hw_check_alive);
1461 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1462 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1464 struct ath_common *common = ath9k_hw_common(ah);
1466 struct ath9k_channel *curchan = ah->curchan;
1472 ah->txchainmask = common->tx_chainmask;
1473 ah->rxchainmask = common->rx_chainmask;
1475 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1478 if (curchan && !ah->chip_fullsleep)
1479 ath9k_hw_getnf(ah, curchan);
1481 ah->caldata = caldata;
1483 (chan->channel != caldata->channel ||
1484 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1485 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1486 /* Operating channel changed, reset channel calibration data */
1487 memset(caldata, 0, sizeof(*caldata));
1488 ath9k_init_nfcal_hist_buffer(ah, chan);
1490 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1492 if (bChannelChange &&
1493 (ah->chip_fullsleep != true) &&
1494 (ah->curchan != NULL) &&
1495 (chan->channel != ah->curchan->channel) &&
1496 ((chan->channelFlags & CHANNEL_ALL) ==
1497 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1498 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1500 if (ath9k_hw_channel_change(ah, chan)) {
1501 ath9k_hw_loadnf(ah, ah->curchan);
1502 ath9k_hw_start_nfcal(ah, true);
1503 if (AR_SREV_9271(ah))
1504 ar9002_hw_load_ani_reg(ah, chan);
1509 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1510 if (saveDefAntenna == 0)
1513 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1515 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1516 if (AR_SREV_9100(ah) ||
1517 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1518 tsf = ath9k_hw_gettsf64(ah);
1520 saveLedState = REG_READ(ah, AR_CFG_LED) &
1521 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1522 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1524 ath9k_hw_mark_phy_inactive(ah);
1526 ah->paprd_table_write_done = false;
1528 /* Only required on the first reset */
1529 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1531 AR9271_RESET_POWER_DOWN_CONTROL,
1532 AR9271_RADIO_RF_RST);
1536 if (!ath9k_hw_chip_reset(ah, chan)) {
1537 ath_err(common, "Chip reset failed\n");
1541 /* Only required on the first reset */
1542 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1543 ah->htc_reset_init = false;
1545 AR9271_RESET_POWER_DOWN_CONTROL,
1546 AR9271_GATE_MAC_CTL);
1552 ath9k_hw_settsf64(ah, tsf);
1554 if (AR_SREV_9280_20_OR_LATER(ah))
1555 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1557 if (!AR_SREV_9300_20_OR_LATER(ah))
1558 ar9002_hw_enable_async_fifo(ah);
1560 r = ath9k_hw_process_ini(ah, chan);
1565 * Some AR91xx SoC devices frequently fail to accept TSF writes
1566 * right after the chip reset. When that happens, write a new
1567 * value after the initvals have been applied, with an offset
1568 * based on measured time difference
1570 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1572 ath9k_hw_settsf64(ah, tsf);
1575 /* Setup MFP options for CCMP */
1576 if (AR_SREV_9280_20_OR_LATER(ah)) {
1577 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1578 * frames when constructing CCMP AAD. */
1579 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1581 ah->sw_mgmt_crypto = false;
1582 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1583 /* Disable hardware crypto for management frames */
1584 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1585 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1586 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1587 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1588 ah->sw_mgmt_crypto = true;
1590 ah->sw_mgmt_crypto = true;
1592 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1593 ath9k_hw_set_delta_slope(ah, chan);
1595 ath9k_hw_spur_mitigate_freq(ah, chan);
1596 ah->eep_ops->set_board_values(ah, chan);
1598 ENABLE_REGWRITE_BUFFER(ah);
1600 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1601 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1603 | AR_STA_ID1_RTS_USE_DEF
1605 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1606 | ah->sta_id1_defaults);
1607 ath_hw_setbssidmask(common);
1608 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1609 ath9k_hw_write_associd(ah);
1610 REG_WRITE(ah, AR_ISR, ~0);
1611 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1613 REGWRITE_BUFFER_FLUSH(ah);
1615 ath9k_hw_set_operating_mode(ah, ah->opmode);
1617 r = ath9k_hw_rf_set_freq(ah, chan);
1621 ath9k_hw_set_clockrate(ah);
1623 ENABLE_REGWRITE_BUFFER(ah);
1625 for (i = 0; i < AR_NUM_DCU; i++)
1626 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1628 REGWRITE_BUFFER_FLUSH(ah);
1631 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1632 ath9k_hw_resettxqueue(ah, i);
1634 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1635 ath9k_hw_ani_cache_ini_regs(ah);
1636 ath9k_hw_init_qos(ah);
1638 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1639 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1641 ath9k_hw_init_global_settings(ah);
1643 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1644 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1645 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1646 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1647 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1648 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1649 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1652 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1654 ath9k_hw_set_dma(ah);
1656 REG_WRITE(ah, AR_OBS, 8);
1658 if (ah->config.rx_intr_mitigation) {
1659 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1660 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1663 if (ah->config.tx_intr_mitigation) {
1664 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1665 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1668 ath9k_hw_init_bb(ah, chan);
1670 if (!ath9k_hw_init_cal(ah, chan))
1673 ENABLE_REGWRITE_BUFFER(ah);
1675 ath9k_hw_restore_chainmask(ah);
1676 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1678 REGWRITE_BUFFER_FLUSH(ah);
1681 * For big endian systems turn on swapping for descriptors
1683 if (AR_SREV_9100(ah)) {
1685 mask = REG_READ(ah, AR_CFG);
1686 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1687 ath_dbg(common, ATH_DBG_RESET,
1688 "CFG Byte Swap Set 0x%x\n", mask);
1691 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1692 REG_WRITE(ah, AR_CFG, mask);
1693 ath_dbg(common, ATH_DBG_RESET,
1694 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1697 if (common->bus_ops->ath_bus_type == ATH_USB) {
1698 /* Configure AR9271 target WLAN */
1699 if (AR_SREV_9271(ah))
1700 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1702 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1705 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1706 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1708 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1712 if (ah->btcoex_hw.enabled)
1713 ath9k_hw_btcoex_enable(ah);
1715 if (AR_SREV_9300_20_OR_LATER(ah)) {
1716 ar9003_hw_bb_watchdog_config(ah);
1718 ar9003_hw_disable_phy_restart(ah);
1721 ath9k_hw_apply_gpio_override(ah);
1725 EXPORT_SYMBOL(ath9k_hw_reset);
1727 /******************************/
1728 /* Power Management (Chipset) */
1729 /******************************/
1732 * Notify Power Mgt is disabled in self-generated frames.
1733 * If requested, force chip to sleep.
1735 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1737 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1740 * Clear the RTC force wake bit to allow the
1741 * mac to go to sleep.
1743 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1744 AR_RTC_FORCE_WAKE_EN);
1745 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1746 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1748 /* Shutdown chip. Active low */
1749 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1750 REG_CLR_BIT(ah, (AR_RTC_RESET),
1754 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1755 if (AR_SREV_9300_20_OR_LATER(ah))
1756 REG_WRITE(ah, AR_WA,
1757 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1761 * Notify Power Management is enabled in self-generating
1762 * frames. If request, set power mode of chip to
1763 * auto/normal. Duration in units of 128us (1/8 TU).
1765 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1767 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1769 struct ath9k_hw_capabilities *pCap = &ah->caps;
1771 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1772 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1773 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1774 AR_RTC_FORCE_WAKE_ON_INT);
1777 * Clear the RTC force wake bit to allow the
1778 * mac to go to sleep.
1780 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1781 AR_RTC_FORCE_WAKE_EN);
1785 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1786 if (AR_SREV_9300_20_OR_LATER(ah))
1787 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1790 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1795 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1796 if (AR_SREV_9300_20_OR_LATER(ah)) {
1797 REG_WRITE(ah, AR_WA, ah->WARegVal);
1802 if ((REG_READ(ah, AR_RTC_STATUS) &
1803 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1804 if (ath9k_hw_set_reset_reg(ah,
1805 ATH9K_RESET_POWER_ON) != true) {
1808 if (!AR_SREV_9300_20_OR_LATER(ah))
1809 ath9k_hw_init_pll(ah, NULL);
1811 if (AR_SREV_9100(ah))
1812 REG_SET_BIT(ah, AR_RTC_RESET,
1815 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1816 AR_RTC_FORCE_WAKE_EN);
1819 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1820 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1821 if (val == AR_RTC_STATUS_ON)
1824 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1825 AR_RTC_FORCE_WAKE_EN);
1828 ath_err(ath9k_hw_common(ah),
1829 "Failed to wakeup in %uus\n",
1830 POWER_UP_TIME / 20);
1835 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1840 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1842 struct ath_common *common = ath9k_hw_common(ah);
1843 int status = true, setChip = true;
1844 static const char *modes[] = {
1851 if (ah->power_mode == mode)
1854 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1855 modes[ah->power_mode], modes[mode]);
1858 case ATH9K_PM_AWAKE:
1859 status = ath9k_hw_set_power_awake(ah, setChip);
1861 case ATH9K_PM_FULL_SLEEP:
1862 ath9k_set_power_sleep(ah, setChip);
1863 ah->chip_fullsleep = true;
1865 case ATH9K_PM_NETWORK_SLEEP:
1866 ath9k_set_power_network_sleep(ah, setChip);
1869 ath_err(common, "Unknown power mode %u\n", mode);
1872 ah->power_mode = mode;
1875 * XXX: If this warning never comes up after a while then
1876 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1877 * ath9k_hw_setpower() return type void.
1880 if (!(ah->ah_flags & AH_UNPLUGGED))
1881 ATH_DBG_WARN_ON_ONCE(!status);
1885 EXPORT_SYMBOL(ath9k_hw_setpower);
1887 /*******************/
1888 /* Beacon Handling */
1889 /*******************/
1891 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1895 ENABLE_REGWRITE_BUFFER(ah);
1897 switch (ah->opmode) {
1898 case NL80211_IFTYPE_ADHOC:
1899 case NL80211_IFTYPE_MESH_POINT:
1900 REG_SET_BIT(ah, AR_TXCFG,
1901 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1902 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1903 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1904 flags |= AR_NDP_TIMER_EN;
1905 case NL80211_IFTYPE_AP:
1906 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1907 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1908 TU_TO_USEC(ah->config.dma_beacon_response_time));
1909 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1910 TU_TO_USEC(ah->config.sw_beacon_response_time));
1912 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1915 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1916 "%s: unsupported opmode: %d\n",
1917 __func__, ah->opmode);
1922 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1923 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1924 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1925 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1927 REGWRITE_BUFFER_FLUSH(ah);
1929 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1931 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1933 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1934 const struct ath9k_beacon_state *bs)
1936 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1937 struct ath9k_hw_capabilities *pCap = &ah->caps;
1938 struct ath_common *common = ath9k_hw_common(ah);
1940 ENABLE_REGWRITE_BUFFER(ah);
1942 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1944 REG_WRITE(ah, AR_BEACON_PERIOD,
1945 TU_TO_USEC(bs->bs_intval));
1946 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1947 TU_TO_USEC(bs->bs_intval));
1949 REGWRITE_BUFFER_FLUSH(ah);
1951 REG_RMW_FIELD(ah, AR_RSSI_THR,
1952 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1954 beaconintval = bs->bs_intval;
1956 if (bs->bs_sleepduration > beaconintval)
1957 beaconintval = bs->bs_sleepduration;
1959 dtimperiod = bs->bs_dtimperiod;
1960 if (bs->bs_sleepduration > dtimperiod)
1961 dtimperiod = bs->bs_sleepduration;
1963 if (beaconintval == dtimperiod)
1964 nextTbtt = bs->bs_nextdtim;
1966 nextTbtt = bs->bs_nexttbtt;
1968 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1969 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1970 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1971 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1973 ENABLE_REGWRITE_BUFFER(ah);
1975 REG_WRITE(ah, AR_NEXT_DTIM,
1976 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1977 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1979 REG_WRITE(ah, AR_SLEEP1,
1980 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1981 | AR_SLEEP1_ASSUME_DTIM);
1983 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1984 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1986 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1988 REG_WRITE(ah, AR_SLEEP2,
1989 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1991 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1992 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1994 REGWRITE_BUFFER_FLUSH(ah);
1996 REG_SET_BIT(ah, AR_TIMER_MODE,
1997 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2000 /* TSF Out of Range Threshold */
2001 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2003 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2005 /*******************/
2006 /* HW Capabilities */
2007 /*******************/
2009 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2011 eeprom_chainmask &= chip_chainmask;
2012 if (eeprom_chainmask)
2013 return eeprom_chainmask;
2015 return chip_chainmask;
2018 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2020 struct ath9k_hw_capabilities *pCap = &ah->caps;
2021 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2022 struct ath_common *common = ath9k_hw_common(ah);
2023 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2024 unsigned int chip_chainmask;
2027 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2029 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2030 regulatory->current_rd = eeval;
2032 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2033 if (AR_SREV_9285_12_OR_LATER(ah))
2034 eeval |= AR9285_RDEXT_DEFAULT;
2035 regulatory->current_rd_ext = eeval;
2037 if (ah->opmode != NL80211_IFTYPE_AP &&
2038 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2039 if (regulatory->current_rd == 0x64 ||
2040 regulatory->current_rd == 0x65)
2041 regulatory->current_rd += 5;
2042 else if (regulatory->current_rd == 0x41)
2043 regulatory->current_rd = 0x43;
2044 ath_dbg(common, ATH_DBG_REGULATORY,
2045 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2048 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2049 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2051 "no band has been marked as supported in EEPROM\n");
2055 if (eeval & AR5416_OPFLAGS_11A)
2056 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2058 if (eeval & AR5416_OPFLAGS_11G)
2059 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2061 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2063 else if (!AR_SREV_9280_20_OR_LATER(ah))
2065 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2070 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2072 * For AR9271 we will temporarilly uses the rx chainmax as read from
2075 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2076 !(eeval & AR5416_OPFLAGS_11A) &&
2077 !(AR_SREV_9271(ah)))
2078 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2079 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2080 else if (AR_SREV_9100(ah))
2081 pCap->rx_chainmask = 0x7;
2083 /* Use rx_chainmask from EEPROM. */
2084 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2086 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2087 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2089 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2091 /* enable key search for every frame in an aggregate */
2092 if (AR_SREV_9300_20_OR_LATER(ah))
2093 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2095 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2097 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2098 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2100 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2102 if (AR_SREV_9271(ah))
2103 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2104 else if (AR_DEVID_7010(ah))
2105 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2106 else if (AR_SREV_9285_12_OR_LATER(ah))
2107 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2108 else if (AR_SREV_9280_20_OR_LATER(ah))
2109 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2111 pCap->num_gpio_pins = AR_NUM_GPIO;
2113 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2114 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2115 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2117 pCap->rts_aggr_limit = (8 * 1024);
2120 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2121 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2122 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2124 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2125 ah->rfkill_polarity =
2126 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2128 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2131 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2132 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2134 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2136 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2137 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2139 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2141 if (common->btcoex_enabled) {
2142 if (AR_SREV_9300_20_OR_LATER(ah)) {
2143 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2144 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2145 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2146 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2147 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2148 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2149 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2151 if (AR_SREV_9285(ah)) {
2152 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2153 btcoex_hw->btpriority_gpio =
2154 ATH_BTPRIORITY_GPIO_9285;
2156 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2160 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2163 if (AR_SREV_9300_20_OR_LATER(ah)) {
2164 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2165 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2166 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2168 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2169 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2170 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2171 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2172 pCap->txs_len = sizeof(struct ar9003_txs);
2173 if (!ah->config.paprd_disable &&
2174 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2175 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2177 pCap->tx_desc_len = sizeof(struct ath_desc);
2178 if (AR_SREV_9280_20(ah))
2179 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2182 if (AR_SREV_9300_20_OR_LATER(ah))
2183 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2185 if (AR_SREV_9300_20_OR_LATER(ah))
2186 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2188 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2189 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2191 if (AR_SREV_9285(ah))
2192 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2194 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2195 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2196 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2198 if (AR_SREV_9300_20_OR_LATER(ah)) {
2199 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2200 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2204 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2205 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2207 * enable the diversity-combining algorithm only when
2208 * both enable_lna_div and enable_fast_div are set
2209 * Table for Diversity
2210 * ant_div_alt_lnaconf bit 0-1
2211 * ant_div_main_lnaconf bit 2-3
2212 * ant_div_alt_gaintb bit 4
2213 * ant_div_main_gaintb bit 5
2214 * enable_ant_div_lnadiv bit 6
2215 * enable_ant_fast_div bit 7
2217 if ((ant_div_ctl1 >> 0x6) == 0x3)
2218 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2221 if (AR_SREV_9485_10(ah)) {
2222 pCap->pcie_lcr_extsync_en = true;
2223 pCap->pcie_lcr_offset = 0x80;
2226 tx_chainmask = pCap->tx_chainmask;
2227 rx_chainmask = pCap->rx_chainmask;
2228 while (tx_chainmask || rx_chainmask) {
2229 if (tx_chainmask & BIT(0))
2230 pCap->max_txchains++;
2231 if (rx_chainmask & BIT(0))
2232 pCap->max_rxchains++;
2241 /****************************/
2242 /* GPIO / RFKILL / Antennae */
2243 /****************************/
2245 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2249 u32 gpio_shift, tmp;
2252 addr = AR_GPIO_OUTPUT_MUX3;
2254 addr = AR_GPIO_OUTPUT_MUX2;
2256 addr = AR_GPIO_OUTPUT_MUX1;
2258 gpio_shift = (gpio % 6) * 5;
2260 if (AR_SREV_9280_20_OR_LATER(ah)
2261 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2262 REG_RMW(ah, addr, (type << gpio_shift),
2263 (0x1f << gpio_shift));
2265 tmp = REG_READ(ah, addr);
2266 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2267 tmp &= ~(0x1f << gpio_shift);
2268 tmp |= (type << gpio_shift);
2269 REG_WRITE(ah, addr, tmp);
2273 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2277 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2279 if (AR_DEVID_7010(ah)) {
2281 REG_RMW(ah, AR7010_GPIO_OE,
2282 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2283 (AR7010_GPIO_OE_MASK << gpio_shift));
2287 gpio_shift = gpio << 1;
2290 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2291 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2293 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2295 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2297 #define MS_REG_READ(x, y) \
2298 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2300 if (gpio >= ah->caps.num_gpio_pins)
2303 if (AR_DEVID_7010(ah)) {
2305 val = REG_READ(ah, AR7010_GPIO_IN);
2306 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2307 } else if (AR_SREV_9300_20_OR_LATER(ah))
2308 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2309 AR_GPIO_BIT(gpio)) != 0;
2310 else if (AR_SREV_9271(ah))
2311 return MS_REG_READ(AR9271, gpio) != 0;
2312 else if (AR_SREV_9287_11_OR_LATER(ah))
2313 return MS_REG_READ(AR9287, gpio) != 0;
2314 else if (AR_SREV_9285_12_OR_LATER(ah))
2315 return MS_REG_READ(AR9285, gpio) != 0;
2316 else if (AR_SREV_9280_20_OR_LATER(ah))
2317 return MS_REG_READ(AR928X, gpio) != 0;
2319 return MS_REG_READ(AR, gpio) != 0;
2321 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2323 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2328 if (AR_DEVID_7010(ah)) {
2330 REG_RMW(ah, AR7010_GPIO_OE,
2331 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2332 (AR7010_GPIO_OE_MASK << gpio_shift));
2336 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2337 gpio_shift = 2 * gpio;
2340 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2341 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2343 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2345 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2347 if (AR_DEVID_7010(ah)) {
2349 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2354 if (AR_SREV_9271(ah))
2357 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2360 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2362 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2364 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2366 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2368 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2370 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2372 EXPORT_SYMBOL(ath9k_hw_setantenna);
2374 /*********************/
2375 /* General Operation */
2376 /*********************/
2378 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2380 u32 bits = REG_READ(ah, AR_RX_FILTER);
2381 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2383 if (phybits & AR_PHY_ERR_RADAR)
2384 bits |= ATH9K_RX_FILTER_PHYRADAR;
2385 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2386 bits |= ATH9K_RX_FILTER_PHYERR;
2390 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2392 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2396 ENABLE_REGWRITE_BUFFER(ah);
2398 REG_WRITE(ah, AR_RX_FILTER, bits);
2401 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2402 phybits |= AR_PHY_ERR_RADAR;
2403 if (bits & ATH9K_RX_FILTER_PHYERR)
2404 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2405 REG_WRITE(ah, AR_PHY_ERR, phybits);
2408 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2410 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2412 REGWRITE_BUFFER_FLUSH(ah);
2414 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2416 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2418 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2421 ath9k_hw_init_pll(ah, NULL);
2424 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2426 bool ath9k_hw_disable(struct ath_hw *ah)
2428 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2431 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2434 ath9k_hw_init_pll(ah, NULL);
2437 EXPORT_SYMBOL(ath9k_hw_disable);
2439 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2441 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2442 struct ath9k_channel *chan = ah->curchan;
2443 struct ieee80211_channel *channel = chan->chan;
2444 int reg_pwr = min_t(int, MAX_RATE_POWER, regulatory->power_limit);
2445 int chan_pwr = channel->max_power * 2;
2448 reg_pwr = chan_pwr = MAX_RATE_POWER;
2450 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2452 ah->eep_ops->set_txpower(ah, chan,
2453 ath9k_regd_get_ctl(regulatory, chan),
2454 channel->max_antenna_gain * 2,
2455 chan_pwr, reg_pwr, test);
2457 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2459 void ath9k_hw_setopmode(struct ath_hw *ah)
2461 ath9k_hw_set_operating_mode(ah, ah->opmode);
2463 EXPORT_SYMBOL(ath9k_hw_setopmode);
2465 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2467 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2468 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2470 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2472 void ath9k_hw_write_associd(struct ath_hw *ah)
2474 struct ath_common *common = ath9k_hw_common(ah);
2476 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2477 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2478 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2480 EXPORT_SYMBOL(ath9k_hw_write_associd);
2482 #define ATH9K_MAX_TSF_READ 10
2484 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2486 u32 tsf_lower, tsf_upper1, tsf_upper2;
2489 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2490 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2491 tsf_lower = REG_READ(ah, AR_TSF_L32);
2492 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2493 if (tsf_upper2 == tsf_upper1)
2495 tsf_upper1 = tsf_upper2;
2498 WARN_ON( i == ATH9K_MAX_TSF_READ );
2500 return (((u64)tsf_upper1 << 32) | tsf_lower);
2502 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2504 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2506 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2507 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2509 EXPORT_SYMBOL(ath9k_hw_settsf64);
2511 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2513 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2514 AH_TSF_WRITE_TIMEOUT))
2515 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2516 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2518 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2520 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2522 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2525 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2527 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2529 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2531 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2533 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2536 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2537 macmode = AR_2040_JOINED_RX_CLEAR;
2541 REG_WRITE(ah, AR_2040_MODE, macmode);
2544 /* HW Generic timers configuration */
2546 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2548 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2549 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2550 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2551 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2552 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2553 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2554 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2555 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2556 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2557 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2558 AR_NDP2_TIMER_MODE, 0x0002},
2559 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2560 AR_NDP2_TIMER_MODE, 0x0004},
2561 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2562 AR_NDP2_TIMER_MODE, 0x0008},
2563 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2564 AR_NDP2_TIMER_MODE, 0x0010},
2565 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2566 AR_NDP2_TIMER_MODE, 0x0020},
2567 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2568 AR_NDP2_TIMER_MODE, 0x0040},
2569 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2570 AR_NDP2_TIMER_MODE, 0x0080}
2573 /* HW generic timer primitives */
2575 /* compute and clear index of rightmost 1 */
2576 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2586 return timer_table->gen_timer_index[b];
2589 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2591 return REG_READ(ah, AR_TSF_L32);
2593 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2595 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2596 void (*trigger)(void *),
2597 void (*overflow)(void *),
2601 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2602 struct ath_gen_timer *timer;
2604 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2606 if (timer == NULL) {
2607 ath_err(ath9k_hw_common(ah),
2608 "Failed to allocate memory for hw timer[%d]\n",
2613 /* allocate a hardware generic timer slot */
2614 timer_table->timers[timer_index] = timer;
2615 timer->index = timer_index;
2616 timer->trigger = trigger;
2617 timer->overflow = overflow;
2622 EXPORT_SYMBOL(ath_gen_timer_alloc);
2624 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2625 struct ath_gen_timer *timer,
2629 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2630 u32 tsf, timer_next;
2632 BUG_ON(!timer_period);
2634 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2636 tsf = ath9k_hw_gettsf32(ah);
2638 timer_next = tsf + trig_timeout;
2640 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2641 "current tsf %x period %x timer_next %x\n",
2642 tsf, timer_period, timer_next);
2645 * Program generic timer registers
2647 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2649 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2651 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2652 gen_tmr_configuration[timer->index].mode_mask);
2654 /* Enable both trigger and thresh interrupt masks */
2655 REG_SET_BIT(ah, AR_IMR_S5,
2656 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2657 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2659 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2661 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2663 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2665 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2666 (timer->index >= ATH_MAX_GEN_TIMER)) {
2670 /* Clear generic timer enable bits. */
2671 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2672 gen_tmr_configuration[timer->index].mode_mask);
2674 /* Disable both trigger and thresh interrupt masks */
2675 REG_CLR_BIT(ah, AR_IMR_S5,
2676 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2677 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2679 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2681 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2683 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2685 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2687 /* free the hardware generic timer slot */
2688 timer_table->timers[timer->index] = NULL;
2691 EXPORT_SYMBOL(ath_gen_timer_free);
2694 * Generic Timer Interrupts handling
2696 void ath_gen_timer_isr(struct ath_hw *ah)
2698 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2699 struct ath_gen_timer *timer;
2700 struct ath_common *common = ath9k_hw_common(ah);
2701 u32 trigger_mask, thresh_mask, index;
2703 /* get hardware generic timer interrupt status */
2704 trigger_mask = ah->intr_gen_timer_trigger;
2705 thresh_mask = ah->intr_gen_timer_thresh;
2706 trigger_mask &= timer_table->timer_mask.val;
2707 thresh_mask &= timer_table->timer_mask.val;
2709 trigger_mask &= ~thresh_mask;
2711 while (thresh_mask) {
2712 index = rightmost_index(timer_table, &thresh_mask);
2713 timer = timer_table->timers[index];
2715 ath_dbg(common, ATH_DBG_HWTIMER,
2716 "TSF overflow for Gen timer %d\n", index);
2717 timer->overflow(timer->arg);
2720 while (trigger_mask) {
2721 index = rightmost_index(timer_table, &trigger_mask);
2722 timer = timer_table->timers[index];
2724 ath_dbg(common, ATH_DBG_HWTIMER,
2725 "Gen timer[%d] trigger\n", index);
2726 timer->trigger(timer->arg);
2729 EXPORT_SYMBOL(ath_gen_timer_isr);
2735 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2737 ah->htc_reset_init = true;
2739 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2744 } ath_mac_bb_names[] = {
2745 /* Devices with external radios */
2746 { AR_SREV_VERSION_5416_PCI, "5416" },
2747 { AR_SREV_VERSION_5416_PCIE, "5418" },
2748 { AR_SREV_VERSION_9100, "9100" },
2749 { AR_SREV_VERSION_9160, "9160" },
2750 /* Single-chip solutions */
2751 { AR_SREV_VERSION_9280, "9280" },
2752 { AR_SREV_VERSION_9285, "9285" },
2753 { AR_SREV_VERSION_9287, "9287" },
2754 { AR_SREV_VERSION_9271, "9271" },
2755 { AR_SREV_VERSION_9300, "9300" },
2756 { AR_SREV_VERSION_9330, "9330" },
2757 { AR_SREV_VERSION_9485, "9485" },
2760 /* For devices with external radios */
2764 } ath_rf_names[] = {
2766 { AR_RAD5133_SREV_MAJOR, "5133" },
2767 { AR_RAD5122_SREV_MAJOR, "5122" },
2768 { AR_RAD2133_SREV_MAJOR, "2133" },
2769 { AR_RAD2122_SREV_MAJOR, "2122" }
2773 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2775 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2779 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2780 if (ath_mac_bb_names[i].version == mac_bb_version) {
2781 return ath_mac_bb_names[i].name;
2789 * Return the RF name. "????" is returned if the RF is unknown.
2790 * Used for devices with external radios.
2792 static const char *ath9k_hw_rf_name(u16 rf_version)
2796 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2797 if (ath_rf_names[i].version == rf_version) {
2798 return ath_rf_names[i].name;
2805 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2809 /* chipsets >= AR9280 are single-chip */
2810 if (AR_SREV_9280_20_OR_LATER(ah)) {
2811 used = snprintf(hw_name, len,
2812 "Atheros AR%s Rev:%x",
2813 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2814 ah->hw_version.macRev);
2817 used = snprintf(hw_name, len,
2818 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2819 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2820 ah->hw_version.macRev,
2821 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2822 AR_RADIO_SREV_MAJOR)),
2823 ah->hw_version.phyRev);
2826 hw_name[used] = '\0';
2828 EXPORT_SYMBOL(ath9k_hw_name);