2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
87 /********************/
88 /* Helper Functions */
89 /********************/
91 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
94 struct ath_common *common = ath9k_hw_common(ah);
95 unsigned int clockrate;
97 if (!ah->curchan) /* should really check for CCK instead */
98 clockrate = ATH9K_CLOCK_RATE_CCK;
99 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
106 if (conf_is_ht40(conf))
109 common->clockrate = clockrate;
112 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
114 struct ath_common *common = ath9k_hw_common(ah);
116 return usecs * common->clockrate;
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 BUG_ON(timeout < AH_TIME_QUANTUM);
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
129 udelay(AH_TIME_QUANTUM);
132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
138 EXPORT_SYMBOL(ath9k_hw_wait);
140 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
145 for (i = 0, retval = 0; i < n; i++) {
146 retval = (retval << 1) | (val & 1);
152 bool ath9k_get_channel_edges(struct ath_hw *ah,
156 struct ath9k_hw_capabilities *pCap = &ah->caps;
158 if (flags & CHANNEL_5GHZ) {
159 *low = pCap->low_5ghz_chan;
160 *high = pCap->high_5ghz_chan;
163 if ((flags & CHANNEL_2GHZ)) {
164 *low = pCap->low_2ghz_chan;
165 *high = pCap->high_2ghz_chan;
171 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
173 u32 frameLen, u16 rateix,
176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
182 case WLAN_RC_PHY_CCK:
183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
189 case WLAN_RC_PHY_OFDM:
190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
222 EXPORT_SYMBOL(ath9k_hw_computetxtime);
224 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers->ext_center =
251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
258 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
271 if (!AR_SREV_9100(ah))
272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
274 ah->hw_version.macRev = val & AR_SREV_REVISION;
276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
277 ah->is_pciexpress = true;
281 /************************************/
282 /* HW Attach, Detach, Init Routines */
283 /************************************/
285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
287 if (AR_SREV_9100(ah))
290 ENABLE_REGWRITE_BUFFER(ah);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
304 REGWRITE_BUFFER_FLUSH(ah);
307 /* This should work for all families including legacy */
308 static bool ath9k_hw_chip_test(struct ath_hw *ah)
310 struct ath_common *common = ath9k_hw_common(ah);
311 u32 regAddr[2] = { AR_STA_ID0 };
313 u32 patternData[4] = { 0x55555555,
319 if (!AR_SREV_9300_20_OR_LATER(ah)) {
321 regAddr[1] = AR_PHY_BASE + (8 << 2);
325 for (i = 0; i < loop_max; i++) {
326 u32 addr = regAddr[i];
329 regHold[i] = REG_READ(ah, addr);
330 for (j = 0; j < 0x100; j++) {
331 wrData = (j << 16) | j;
332 REG_WRITE(ah, addr, wrData);
333 rdData = REG_READ(ah, addr);
334 if (rdData != wrData) {
335 ath_print(common, ATH_DBG_FATAL,
336 "address test failed "
337 "addr: 0x%08x - wr:0x%08x != "
339 addr, wrData, rdData);
343 for (j = 0; j < 4; j++) {
344 wrData = patternData[j];
345 REG_WRITE(ah, addr, wrData);
346 rdData = REG_READ(ah, addr);
347 if (wrData != rdData) {
348 ath_print(common, ATH_DBG_FATAL,
349 "address test failed "
350 "addr: 0x%08x - wr:0x%08x != "
352 addr, wrData, rdData);
356 REG_WRITE(ah, regAddr[i], regHold[i]);
363 static void ath9k_hw_init_config(struct ath_hw *ah)
367 ah->config.dma_beacon_response_time = 2;
368 ah->config.sw_beacon_response_time = 10;
369 ah->config.additional_swba_backoff = 0;
370 ah->config.ack_6mb = 0x0;
371 ah->config.cwm_ignore_extcca = 0;
372 ah->config.pcie_powersave_enable = 0;
373 ah->config.pcie_clock_req = 0;
374 ah->config.pcie_waen = 0;
375 ah->config.analog_shiftreg = 1;
376 ah->config.enable_ani = true;
378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
383 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
384 ah->config.ht_enable = 1;
386 ah->config.ht_enable = 0;
388 ah->config.rx_intr_mitigation = true;
389 ah->config.pcieSerDesWrite = true;
392 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
393 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
394 * This means we use it for all AR5416 devices, and the few
395 * minor PCI AR9280 devices out there.
397 * Serialization is required because these devices do not handle
398 * well the case of two concurrent reads/writes due to the latency
399 * involved. During one read/write another read/write can be issued
400 * on another CPU while the previous read/write may still be working
401 * on our hardware, if we hit this case the hardware poops in a loop.
402 * We prevent this by serializing reads and writes.
404 * This issue is not present on PCI-Express devices or pre-AR5416
405 * devices (legacy, 802.11abg).
407 if (num_possible_cpus() > 1)
408 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
411 static void ath9k_hw_init_defaults(struct ath_hw *ah)
413 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
415 regulatory->country_code = CTRY_DEFAULT;
416 regulatory->power_limit = MAX_RATE_POWER;
417 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
419 ah->hw_version.magic = AR5416_MAGIC;
420 ah->hw_version.subvendorid = 0;
423 if (!AR_SREV_9100(ah))
424 ah->ah_flags = AH_USE_EEPROM;
427 ah->sta_id1_defaults =
428 AR_STA_ID1_CRPT_MIC_ENABLE |
429 AR_STA_ID1_MCAST_KSRCH;
430 ah->beacon_interval = 100;
431 ah->enable_32kHz_clock = DONT_USE_32KHZ;
432 ah->slottime = (u32) -1;
433 ah->globaltxtimeout = (u32) -1;
434 ah->power_mode = ATH9K_PM_UNDEFINED;
437 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
439 struct ath_common *common = ath9k_hw_common(ah);
443 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
446 for (i = 0; i < 3; i++) {
447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
449 common->macaddr[2 * i] = eeval >> 8;
450 common->macaddr[2 * i + 1] = eeval & 0xff;
452 if (sum == 0 || sum == 0xffff * 3)
453 return -EADDRNOTAVAIL;
458 static int ath9k_hw_post_init(struct ath_hw *ah)
462 if (!AR_SREV_9271(ah)) {
463 if (!ath9k_hw_chip_test(ah))
467 if (!AR_SREV_9300_20_OR_LATER(ah)) {
468 ecode = ar9002_hw_rf_claim(ah);
473 ecode = ath9k_hw_eeprom_init(ah);
477 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
478 "Eeprom VER: %d, REV: %d\n",
479 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah));
482 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
484 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
485 "Failed allocating banks for "
490 if (!AR_SREV_9100(ah)) {
491 ath9k_hw_ani_setup(ah);
492 ath9k_hw_ani_init(ah);
498 static void ath9k_hw_attach_ops(struct ath_hw *ah)
500 if (AR_SREV_9300_20_OR_LATER(ah))
501 ar9003_hw_attach_ops(ah);
503 ar9002_hw_attach_ops(ah);
506 /* Called for all hardware families */
507 static int __ath9k_hw_init(struct ath_hw *ah)
509 struct ath_common *common = ath9k_hw_common(ah);
512 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
513 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
515 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
516 ath_print(common, ATH_DBG_FATAL,
517 "Couldn't reset chip\n");
521 ath9k_hw_init_defaults(ah);
522 ath9k_hw_init_config(ah);
524 ath9k_hw_attach_ops(ah);
526 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
527 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
531 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
532 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
533 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
534 !ah->is_pciexpress)) {
535 ah->config.serialize_regmode =
538 ah->config.serialize_regmode =
543 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
544 ah->config.serialize_regmode);
546 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
547 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
551 if (!ath9k_hw_macversion_supported(ah)) {
552 ath_print(common, ATH_DBG_FATAL,
553 "Mac Chip Rev 0x%02x.%x is not supported by "
554 "this driver\n", ah->hw_version.macVersion,
555 ah->hw_version.macRev);
559 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
560 ah->is_pciexpress = false;
562 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
563 ath9k_hw_init_cal_settings(ah);
565 ah->ani_function = ATH9K_ANI_ALL;
566 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
567 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
568 if (!AR_SREV_9300_20_OR_LATER(ah))
569 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
571 ath9k_hw_init_mode_regs(ah);
574 * Read back AR_WA into a permanent copy and set bits 14 and 17.
575 * We need to do this to avoid RMW of this register. We cannot
576 * read the reg when chip is asleep.
578 ah->WARegVal = REG_READ(ah, AR_WA);
579 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
580 AR_WA_ASPM_TIMER_BASED_DISABLE);
582 if (ah->is_pciexpress)
583 ath9k_hw_configpcipowersave(ah, 0, 0);
585 ath9k_hw_disablepcie(ah);
587 if (!AR_SREV_9300_20_OR_LATER(ah))
588 ar9002_hw_cck_chan14_spread(ah);
590 r = ath9k_hw_post_init(ah);
594 ath9k_hw_init_mode_gain_regs(ah);
595 r = ath9k_hw_fill_cap_info(ah);
599 r = ath9k_hw_init_macaddr(ah);
601 ath_print(common, ATH_DBG_FATAL,
602 "Failed to initialize MAC address\n");
606 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
607 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
609 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
611 ah->bb_watchdog_timeout_ms = 25;
613 common->state = ATH_HW_INITIALIZED;
618 int ath9k_hw_init(struct ath_hw *ah)
621 struct ath_common *common = ath9k_hw_common(ah);
623 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
624 switch (ah->hw_version.devid) {
625 case AR5416_DEVID_PCI:
626 case AR5416_DEVID_PCIE:
627 case AR5416_AR9100_DEVID:
628 case AR9160_DEVID_PCI:
629 case AR9280_DEVID_PCI:
630 case AR9280_DEVID_PCIE:
631 case AR9285_DEVID_PCIE:
632 case AR9287_DEVID_PCI:
633 case AR9287_DEVID_PCIE:
634 case AR2427_DEVID_PCIE:
635 case AR9300_DEVID_PCIE:
638 if (common->bus_ops->ath_bus_type == ATH_USB)
640 ath_print(common, ATH_DBG_FATAL,
641 "Hardware device ID 0x%04x not supported\n",
642 ah->hw_version.devid);
646 ret = __ath9k_hw_init(ah);
648 ath_print(common, ATH_DBG_FATAL,
649 "Unable to initialize hardware; "
650 "initialization status: %d\n", ret);
656 EXPORT_SYMBOL(ath9k_hw_init);
658 static void ath9k_hw_init_qos(struct ath_hw *ah)
660 ENABLE_REGWRITE_BUFFER(ah);
662 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
663 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
665 REG_WRITE(ah, AR_QOS_NO_ACK,
666 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
667 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
668 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
670 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
671 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
672 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
673 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
674 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
676 REGWRITE_BUFFER_FLUSH(ah);
679 static void ath9k_hw_init_pll(struct ath_hw *ah,
680 struct ath9k_channel *chan)
682 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
684 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
686 /* Switch the core clock for ar9271 to 117Mhz */
687 if (AR_SREV_9271(ah)) {
689 REG_WRITE(ah, 0x50040, 0x304);
692 udelay(RTC_PLL_SETTLE_DELAY);
694 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
697 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
698 enum nl80211_iftype opmode)
700 u32 imr_reg = AR_IMR_TXERR |
706 if (AR_SREV_9300_20_OR_LATER(ah)) {
707 imr_reg |= AR_IMR_RXOK_HP;
708 if (ah->config.rx_intr_mitigation)
709 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
711 imr_reg |= AR_IMR_RXOK_LP;
714 if (ah->config.rx_intr_mitigation)
715 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
717 imr_reg |= AR_IMR_RXOK;
720 if (ah->config.tx_intr_mitigation)
721 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
723 imr_reg |= AR_IMR_TXOK;
725 if (opmode == NL80211_IFTYPE_AP)
726 imr_reg |= AR_IMR_MIB;
728 ENABLE_REGWRITE_BUFFER(ah);
730 REG_WRITE(ah, AR_IMR, imr_reg);
731 ah->imrs2_reg |= AR_IMR_S2_GTT;
732 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
734 if (!AR_SREV_9100(ah)) {
735 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
736 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
737 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
740 REGWRITE_BUFFER_FLUSH(ah);
742 if (AR_SREV_9300_20_OR_LATER(ah)) {
743 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
744 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
745 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
746 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
750 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
752 u32 val = ath9k_hw_mac_to_clks(ah, us);
753 val = min(val, (u32) 0xFFFF);
754 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
757 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
759 u32 val = ath9k_hw_mac_to_clks(ah, us);
760 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
761 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
764 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
766 u32 val = ath9k_hw_mac_to_clks(ah, us);
767 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
768 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
771 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
774 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
775 "bad global tx timeout %u\n", tu);
776 ah->globaltxtimeout = (u32) -1;
779 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
780 ah->globaltxtimeout = tu;
785 void ath9k_hw_init_global_settings(struct ath_hw *ah)
787 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
792 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
795 if (ah->misc_mode != 0)
796 REG_WRITE(ah, AR_PCU_MISC,
797 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
799 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
804 /* As defined by IEEE 802.11-2007 17.3.8.6 */
805 slottime = ah->slottime + 3 * ah->coverage_class;
806 acktimeout = slottime + sifstime;
809 * Workaround for early ACK timeouts, add an offset to match the
810 * initval's 64us ack timeout value.
811 * This was initially only meant to work around an issue with delayed
812 * BA frames in some implementations, but it has been found to fix ACK
813 * timeout issues in other cases as well.
815 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
816 acktimeout += 64 - sifstime - ah->slottime;
818 ath9k_hw_setslottime(ah, slottime);
819 ath9k_hw_set_ack_timeout(ah, acktimeout);
820 ath9k_hw_set_cts_timeout(ah, acktimeout);
821 if (ah->globaltxtimeout != (u32) -1)
822 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
824 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
826 void ath9k_hw_deinit(struct ath_hw *ah)
828 struct ath_common *common = ath9k_hw_common(ah);
830 if (common->state < ATH_HW_INITIALIZED)
833 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
836 ath9k_hw_rf_free_ext_banks(ah);
838 EXPORT_SYMBOL(ath9k_hw_deinit);
844 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
846 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
850 else if (IS_CHAN_G(chan))
858 /****************************************/
859 /* Reset and Channel Switching Routines */
860 /****************************************/
862 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
864 struct ath_common *common = ath9k_hw_common(ah);
867 ENABLE_REGWRITE_BUFFER(ah);
870 * set AHB_MODE not to do cacheline prefetches
872 if (!AR_SREV_9300_20_OR_LATER(ah)) {
873 regval = REG_READ(ah, AR_AHB_MODE);
874 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
878 * let mac dma reads be in 128 byte chunks
880 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
881 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
883 REGWRITE_BUFFER_FLUSH(ah);
886 * Restore TX Trigger Level to its pre-reset value.
887 * The initial value depends on whether aggregation is enabled, and is
888 * adjusted whenever underruns are detected.
890 if (!AR_SREV_9300_20_OR_LATER(ah))
891 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
893 ENABLE_REGWRITE_BUFFER(ah);
896 * let mac dma writes be in 128 byte chunks
898 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
899 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
902 * Setup receive FIFO threshold to hold off TX activities
904 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
906 if (AR_SREV_9300_20_OR_LATER(ah)) {
907 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
908 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
910 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
911 ah->caps.rx_status_len);
915 * reduce the number of usable entries in PCU TXBUF to avoid
916 * wrap around issues.
918 if (AR_SREV_9285(ah)) {
919 /* For AR9285 the number of Fifos are reduced to half.
920 * So set the usable tx buf size also to half to
921 * avoid data/delimiter underruns
923 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
924 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
925 } else if (!AR_SREV_9271(ah)) {
926 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
927 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
930 REGWRITE_BUFFER_FLUSH(ah);
932 if (AR_SREV_9300_20_OR_LATER(ah))
933 ath9k_hw_reset_txstatus_ring(ah);
936 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
940 val = REG_READ(ah, AR_STA_ID1);
941 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
943 case NL80211_IFTYPE_AP:
944 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
945 | AR_STA_ID1_KSRCH_MODE);
946 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
948 case NL80211_IFTYPE_ADHOC:
949 case NL80211_IFTYPE_MESH_POINT:
950 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
951 | AR_STA_ID1_KSRCH_MODE);
952 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
954 case NL80211_IFTYPE_STATION:
955 case NL80211_IFTYPE_MONITOR:
956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
961 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
962 u32 *coef_mantissa, u32 *coef_exponent)
964 u32 coef_exp, coef_man;
966 for (coef_exp = 31; coef_exp > 0; coef_exp--)
967 if ((coef_scaled >> coef_exp) & 0x1)
970 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
972 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
974 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
975 *coef_exponent = coef_exp - 16;
978 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
983 if (AR_SREV_9100(ah)) {
984 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
985 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
986 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
987 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
988 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
991 ENABLE_REGWRITE_BUFFER(ah);
993 if (AR_SREV_9300_20_OR_LATER(ah)) {
994 REG_WRITE(ah, AR_WA, ah->WARegVal);
998 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
999 AR_RTC_FORCE_WAKE_ON_INT);
1001 if (AR_SREV_9100(ah)) {
1002 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1003 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1005 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1007 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1008 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1010 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1013 if (!AR_SREV_9300_20_OR_LATER(ah))
1015 REG_WRITE(ah, AR_RC, val);
1017 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1018 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1020 rst_flags = AR_RTC_RC_MAC_WARM;
1021 if (type == ATH9K_RESET_COLD)
1022 rst_flags |= AR_RTC_RC_MAC_COLD;
1025 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1027 REGWRITE_BUFFER_FLUSH(ah);
1031 REG_WRITE(ah, AR_RTC_RC, 0);
1032 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1033 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1034 "RTC stuck in MAC reset\n");
1038 if (!AR_SREV_9100(ah))
1039 REG_WRITE(ah, AR_RC, 0);
1041 if (AR_SREV_9100(ah))
1047 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1049 ENABLE_REGWRITE_BUFFER(ah);
1051 if (AR_SREV_9300_20_OR_LATER(ah)) {
1052 REG_WRITE(ah, AR_WA, ah->WARegVal);
1056 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1057 AR_RTC_FORCE_WAKE_ON_INT);
1059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1060 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1062 REG_WRITE(ah, AR_RTC_RESET, 0);
1065 REGWRITE_BUFFER_FLUSH(ah);
1067 if (!AR_SREV_9300_20_OR_LATER(ah))
1070 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1071 REG_WRITE(ah, AR_RC, 0);
1073 REG_WRITE(ah, AR_RTC_RESET, 1);
1075 if (!ath9k_hw_wait(ah,
1080 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1081 "RTC not waking up\n");
1085 ath9k_hw_read_revisions(ah);
1087 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1090 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1092 if (AR_SREV_9300_20_OR_LATER(ah)) {
1093 REG_WRITE(ah, AR_WA, ah->WARegVal);
1097 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1098 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1101 case ATH9K_RESET_POWER_ON:
1102 return ath9k_hw_set_reset_power_on(ah);
1103 case ATH9K_RESET_WARM:
1104 case ATH9K_RESET_COLD:
1105 return ath9k_hw_set_reset(ah, type);
1111 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1112 struct ath9k_channel *chan)
1114 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1115 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1117 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1120 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1123 ah->chip_fullsleep = false;
1124 ath9k_hw_init_pll(ah, chan);
1125 ath9k_hw_set_rfmode(ah, chan);
1130 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1131 struct ath9k_channel *chan)
1133 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1134 struct ath_common *common = ath9k_hw_common(ah);
1135 struct ieee80211_channel *channel = chan->chan;
1139 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1140 if (ath9k_hw_numtxpending(ah, qnum)) {
1141 ath_print(common, ATH_DBG_QUEUE,
1142 "Transmit frames pending on "
1143 "queue %d\n", qnum);
1148 if (!ath9k_hw_rfbus_req(ah)) {
1149 ath_print(common, ATH_DBG_FATAL,
1150 "Could not kill baseband RX\n");
1154 ath9k_hw_set_channel_regs(ah, chan);
1156 r = ath9k_hw_rf_set_freq(ah, chan);
1158 ath_print(common, ATH_DBG_FATAL,
1159 "Failed to set channel\n");
1162 ath9k_hw_set_clockrate(ah);
1164 ah->eep_ops->set_txpower(ah, chan,
1165 ath9k_regd_get_ctl(regulatory, chan),
1166 channel->max_antenna_gain * 2,
1167 channel->max_power * 2,
1168 min((u32) MAX_RATE_POWER,
1169 (u32) regulatory->power_limit));
1171 ath9k_hw_rfbus_done(ah);
1173 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1174 ath9k_hw_set_delta_slope(ah, chan);
1176 ath9k_hw_spur_mitigate_freq(ah, chan);
1181 bool ath9k_hw_check_alive(struct ath_hw *ah)
1186 if (AR_SREV_9285_12_OR_LATER(ah))
1190 reg = REG_READ(ah, AR_OBS_BUS_1);
1192 if ((reg & 0x7E7FFFEF) == 0x00702400)
1195 switch (reg & 0x7E000B00) {
1203 } while (count-- > 0);
1207 EXPORT_SYMBOL(ath9k_hw_check_alive);
1209 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1210 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1212 struct ath_common *common = ath9k_hw_common(ah);
1214 struct ath9k_channel *curchan = ah->curchan;
1220 ah->txchainmask = common->tx_chainmask;
1221 ah->rxchainmask = common->rx_chainmask;
1223 if (!ah->chip_fullsleep) {
1224 ath9k_hw_abortpcurecv(ah);
1225 if (!ath9k_hw_stopdmarecv(ah)) {
1226 ath_print(common, ATH_DBG_XMIT,
1227 "Failed to stop receive dma\n");
1228 bChannelChange = false;
1232 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1235 if (curchan && !ah->chip_fullsleep)
1236 ath9k_hw_getnf(ah, curchan);
1238 ah->caldata = caldata;
1240 (chan->channel != caldata->channel ||
1241 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1242 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1243 /* Operating channel changed, reset channel calibration data */
1244 memset(caldata, 0, sizeof(*caldata));
1245 ath9k_init_nfcal_hist_buffer(ah, chan);
1248 if (bChannelChange &&
1249 (ah->chip_fullsleep != true) &&
1250 (ah->curchan != NULL) &&
1251 (chan->channel != ah->curchan->channel) &&
1252 ((chan->channelFlags & CHANNEL_ALL) ==
1253 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1254 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1256 if (ath9k_hw_channel_change(ah, chan)) {
1257 ath9k_hw_loadnf(ah, ah->curchan);
1258 ath9k_hw_start_nfcal(ah, true);
1259 if (AR_SREV_9271(ah))
1260 ar9002_hw_load_ani_reg(ah, chan);
1265 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1266 if (saveDefAntenna == 0)
1269 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1271 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1272 if (AR_SREV_9100(ah) ||
1273 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1274 tsf = ath9k_hw_gettsf64(ah);
1276 saveLedState = REG_READ(ah, AR_CFG_LED) &
1277 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1278 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1280 ath9k_hw_mark_phy_inactive(ah);
1282 /* Only required on the first reset */
1283 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1285 AR9271_RESET_POWER_DOWN_CONTROL,
1286 AR9271_RADIO_RF_RST);
1290 if (!ath9k_hw_chip_reset(ah, chan)) {
1291 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1295 /* Only required on the first reset */
1296 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1297 ah->htc_reset_init = false;
1299 AR9271_RESET_POWER_DOWN_CONTROL,
1300 AR9271_GATE_MAC_CTL);
1306 ath9k_hw_settsf64(ah, tsf);
1308 if (AR_SREV_9280_20_OR_LATER(ah))
1309 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1311 if (!AR_SREV_9300_20_OR_LATER(ah))
1312 ar9002_hw_enable_async_fifo(ah);
1314 r = ath9k_hw_process_ini(ah, chan);
1319 * Some AR91xx SoC devices frequently fail to accept TSF writes
1320 * right after the chip reset. When that happens, write a new
1321 * value after the initvals have been applied, with an offset
1322 * based on measured time difference
1324 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1326 ath9k_hw_settsf64(ah, tsf);
1329 /* Setup MFP options for CCMP */
1330 if (AR_SREV_9280_20_OR_LATER(ah)) {
1331 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1332 * frames when constructing CCMP AAD. */
1333 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1335 ah->sw_mgmt_crypto = false;
1336 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1337 /* Disable hardware crypto for management frames */
1338 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1339 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1340 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1341 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1342 ah->sw_mgmt_crypto = true;
1344 ah->sw_mgmt_crypto = true;
1346 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1347 ath9k_hw_set_delta_slope(ah, chan);
1349 ath9k_hw_spur_mitigate_freq(ah, chan);
1350 ah->eep_ops->set_board_values(ah, chan);
1352 ath9k_hw_set_operating_mode(ah, ah->opmode);
1354 ENABLE_REGWRITE_BUFFER(ah);
1356 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1357 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1359 | AR_STA_ID1_RTS_USE_DEF
1361 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1362 | ah->sta_id1_defaults);
1363 ath_hw_setbssidmask(common);
1364 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1365 ath9k_hw_write_associd(ah);
1366 REG_WRITE(ah, AR_ISR, ~0);
1367 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1369 REGWRITE_BUFFER_FLUSH(ah);
1371 r = ath9k_hw_rf_set_freq(ah, chan);
1375 ath9k_hw_set_clockrate(ah);
1377 ENABLE_REGWRITE_BUFFER(ah);
1379 for (i = 0; i < AR_NUM_DCU; i++)
1380 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1382 REGWRITE_BUFFER_FLUSH(ah);
1385 for (i = 0; i < ah->caps.total_queues; i++)
1386 ath9k_hw_resettxqueue(ah, i);
1388 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1389 ath9k_hw_ani_cache_ini_regs(ah);
1390 ath9k_hw_init_qos(ah);
1392 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1393 ath9k_enable_rfkill(ah);
1395 ath9k_hw_init_global_settings(ah);
1397 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1398 ar9002_hw_update_async_fifo(ah);
1399 ar9002_hw_enable_wep_aggregation(ah);
1402 REG_WRITE(ah, AR_STA_ID1,
1403 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1405 ath9k_hw_set_dma(ah);
1407 REG_WRITE(ah, AR_OBS, 8);
1409 if (ah->config.rx_intr_mitigation) {
1410 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1411 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1414 if (ah->config.tx_intr_mitigation) {
1415 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1416 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1419 ath9k_hw_init_bb(ah, chan);
1421 if (!ath9k_hw_init_cal(ah, chan))
1424 ENABLE_REGWRITE_BUFFER(ah);
1426 ath9k_hw_restore_chainmask(ah);
1427 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1429 REGWRITE_BUFFER_FLUSH(ah);
1432 * For big endian systems turn on swapping for descriptors
1434 if (AR_SREV_9100(ah)) {
1436 mask = REG_READ(ah, AR_CFG);
1437 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1438 ath_print(common, ATH_DBG_RESET,
1439 "CFG Byte Swap Set 0x%x\n", mask);
1442 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1443 REG_WRITE(ah, AR_CFG, mask);
1444 ath_print(common, ATH_DBG_RESET,
1445 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1448 if (common->bus_ops->ath_bus_type == ATH_USB) {
1449 /* Configure AR9271 target WLAN */
1450 if (AR_SREV_9271(ah))
1451 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1453 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1457 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1461 if (ah->btcoex_hw.enabled)
1462 ath9k_hw_btcoex_enable(ah);
1464 if (AR_SREV_9300_20_OR_LATER(ah))
1465 ar9003_hw_bb_watchdog_config(ah);
1469 EXPORT_SYMBOL(ath9k_hw_reset);
1471 /******************************/
1472 /* Power Management (Chipset) */
1473 /******************************/
1476 * Notify Power Mgt is disabled in self-generated frames.
1477 * If requested, force chip to sleep.
1479 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1481 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1484 * Clear the RTC force wake bit to allow the
1485 * mac to go to sleep.
1487 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1488 AR_RTC_FORCE_WAKE_EN);
1489 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1490 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1492 /* Shutdown chip. Active low */
1493 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1494 REG_CLR_BIT(ah, (AR_RTC_RESET),
1498 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1499 if (AR_SREV_9300_20_OR_LATER(ah))
1500 REG_WRITE(ah, AR_WA,
1501 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1505 * Notify Power Management is enabled in self-generating
1506 * frames. If request, set power mode of chip to
1507 * auto/normal. Duration in units of 128us (1/8 TU).
1509 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1511 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1513 struct ath9k_hw_capabilities *pCap = &ah->caps;
1515 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1516 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1517 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1518 AR_RTC_FORCE_WAKE_ON_INT);
1521 * Clear the RTC force wake bit to allow the
1522 * mac to go to sleep.
1524 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1525 AR_RTC_FORCE_WAKE_EN);
1529 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1530 if (AR_SREV_9300_20_OR_LATER(ah))
1531 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1534 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1539 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1540 if (AR_SREV_9300_20_OR_LATER(ah)) {
1541 REG_WRITE(ah, AR_WA, ah->WARegVal);
1546 if ((REG_READ(ah, AR_RTC_STATUS) &
1547 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1548 if (ath9k_hw_set_reset_reg(ah,
1549 ATH9K_RESET_POWER_ON) != true) {
1552 if (!AR_SREV_9300_20_OR_LATER(ah))
1553 ath9k_hw_init_pll(ah, NULL);
1555 if (AR_SREV_9100(ah))
1556 REG_SET_BIT(ah, AR_RTC_RESET,
1559 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1560 AR_RTC_FORCE_WAKE_EN);
1563 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1564 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1565 if (val == AR_RTC_STATUS_ON)
1568 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1569 AR_RTC_FORCE_WAKE_EN);
1572 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1573 "Failed to wakeup in %uus\n",
1574 POWER_UP_TIME / 20);
1579 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1584 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1586 struct ath_common *common = ath9k_hw_common(ah);
1587 int status = true, setChip = true;
1588 static const char *modes[] = {
1595 if (ah->power_mode == mode)
1598 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1599 modes[ah->power_mode], modes[mode]);
1602 case ATH9K_PM_AWAKE:
1603 status = ath9k_hw_set_power_awake(ah, setChip);
1605 case ATH9K_PM_FULL_SLEEP:
1606 ath9k_set_power_sleep(ah, setChip);
1607 ah->chip_fullsleep = true;
1609 case ATH9K_PM_NETWORK_SLEEP:
1610 ath9k_set_power_network_sleep(ah, setChip);
1613 ath_print(common, ATH_DBG_FATAL,
1614 "Unknown power mode %u\n", mode);
1617 ah->power_mode = mode;
1621 EXPORT_SYMBOL(ath9k_hw_setpower);
1623 /*******************/
1624 /* Beacon Handling */
1625 /*******************/
1627 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1631 ah->beacon_interval = beacon_period;
1633 ENABLE_REGWRITE_BUFFER(ah);
1635 switch (ah->opmode) {
1636 case NL80211_IFTYPE_STATION:
1637 case NL80211_IFTYPE_MONITOR:
1638 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1639 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1640 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1641 flags |= AR_TBTT_TIMER_EN;
1643 case NL80211_IFTYPE_ADHOC:
1644 case NL80211_IFTYPE_MESH_POINT:
1645 REG_SET_BIT(ah, AR_TXCFG,
1646 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1647 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1648 TU_TO_USEC(next_beacon +
1649 (ah->atim_window ? ah->
1651 flags |= AR_NDP_TIMER_EN;
1652 case NL80211_IFTYPE_AP:
1653 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1654 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1655 TU_TO_USEC(next_beacon -
1657 dma_beacon_response_time));
1658 REG_WRITE(ah, AR_NEXT_SWBA,
1659 TU_TO_USEC(next_beacon -
1661 sw_beacon_response_time));
1663 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1666 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1667 "%s: unsupported opmode: %d\n",
1668 __func__, ah->opmode);
1673 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1674 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1675 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1676 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1678 REGWRITE_BUFFER_FLUSH(ah);
1680 beacon_period &= ~ATH9K_BEACON_ENA;
1681 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1682 ath9k_hw_reset_tsf(ah);
1685 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1687 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1689 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1690 const struct ath9k_beacon_state *bs)
1692 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1693 struct ath9k_hw_capabilities *pCap = &ah->caps;
1694 struct ath_common *common = ath9k_hw_common(ah);
1696 ENABLE_REGWRITE_BUFFER(ah);
1698 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1700 REG_WRITE(ah, AR_BEACON_PERIOD,
1701 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1702 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1703 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1705 REGWRITE_BUFFER_FLUSH(ah);
1707 REG_RMW_FIELD(ah, AR_RSSI_THR,
1708 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1710 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1712 if (bs->bs_sleepduration > beaconintval)
1713 beaconintval = bs->bs_sleepduration;
1715 dtimperiod = bs->bs_dtimperiod;
1716 if (bs->bs_sleepduration > dtimperiod)
1717 dtimperiod = bs->bs_sleepduration;
1719 if (beaconintval == dtimperiod)
1720 nextTbtt = bs->bs_nextdtim;
1722 nextTbtt = bs->bs_nexttbtt;
1724 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1725 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1726 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1727 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1729 ENABLE_REGWRITE_BUFFER(ah);
1731 REG_WRITE(ah, AR_NEXT_DTIM,
1732 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1733 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1735 REG_WRITE(ah, AR_SLEEP1,
1736 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1737 | AR_SLEEP1_ASSUME_DTIM);
1739 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1740 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1742 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1744 REG_WRITE(ah, AR_SLEEP2,
1745 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1747 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1748 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1750 REGWRITE_BUFFER_FLUSH(ah);
1752 REG_SET_BIT(ah, AR_TIMER_MODE,
1753 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1756 /* TSF Out of Range Threshold */
1757 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1759 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1761 /*******************/
1762 /* HW Capabilities */
1763 /*******************/
1765 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1767 struct ath9k_hw_capabilities *pCap = &ah->caps;
1768 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1769 struct ath_common *common = ath9k_hw_common(ah);
1770 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1772 u16 capField = 0, eeval;
1775 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1776 regulatory->current_rd = eeval;
1778 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1779 if (AR_SREV_9285_12_OR_LATER(ah))
1780 eeval |= AR9285_RDEXT_DEFAULT;
1781 regulatory->current_rd_ext = eeval;
1783 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1785 if (ah->opmode != NL80211_IFTYPE_AP &&
1786 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1787 if (regulatory->current_rd == 0x64 ||
1788 regulatory->current_rd == 0x65)
1789 regulatory->current_rd += 5;
1790 else if (regulatory->current_rd == 0x41)
1791 regulatory->current_rd = 0x43;
1792 ath_print(common, ATH_DBG_REGULATORY,
1793 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1796 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1797 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1798 ath_print(common, ATH_DBG_FATAL,
1799 "no band has been marked as supported in EEPROM.\n");
1803 if (eeval & AR5416_OPFLAGS_11A)
1804 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1806 if (eeval & AR5416_OPFLAGS_11G)
1807 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1809 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1811 * For AR9271 we will temporarilly uses the rx chainmax as read from
1814 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1815 !(eeval & AR5416_OPFLAGS_11A) &&
1816 !(AR_SREV_9271(ah)))
1817 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1818 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1820 /* Use rx_chainmask from EEPROM. */
1821 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1823 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1825 pCap->low_2ghz_chan = 2312;
1826 pCap->high_2ghz_chan = 2732;
1828 pCap->low_5ghz_chan = 4920;
1829 pCap->high_5ghz_chan = 6100;
1831 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1833 if (ah->config.ht_enable)
1834 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1836 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1838 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1839 pCap->total_queues =
1840 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1842 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1844 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1845 pCap->keycache_size =
1846 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1848 pCap->keycache_size = AR_KEYTABLE_SIZE;
1850 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1851 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1853 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1855 if (AR_SREV_9271(ah))
1856 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1857 else if (AR_DEVID_7010(ah))
1858 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1859 else if (AR_SREV_9285_12_OR_LATER(ah))
1860 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1861 else if (AR_SREV_9280_20_OR_LATER(ah))
1862 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1864 pCap->num_gpio_pins = AR_NUM_GPIO;
1866 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1867 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1868 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1870 pCap->rts_aggr_limit = (8 * 1024);
1873 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1875 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1876 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1877 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1879 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1880 ah->rfkill_polarity =
1881 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1883 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1886 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1887 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1889 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1891 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1892 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1894 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1896 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1898 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1899 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1900 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1901 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1904 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1905 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1908 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1909 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1911 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1913 pCap->num_antcfg_5ghz =
1914 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1915 pCap->num_antcfg_2ghz =
1916 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1918 if (AR_SREV_9280_20_OR_LATER(ah) &&
1919 ath9k_hw_btcoex_supported(ah)) {
1920 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1921 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1923 if (AR_SREV_9285(ah)) {
1924 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1925 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1927 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1930 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1933 if (AR_SREV_9300_20_OR_LATER(ah)) {
1934 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
1935 ATH9K_HW_CAP_FASTCLOCK;
1936 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1937 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1938 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1939 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1940 pCap->txs_len = sizeof(struct ar9003_txs);
1941 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1942 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1944 pCap->tx_desc_len = sizeof(struct ath_desc);
1945 if (AR_SREV_9280_20(ah) &&
1946 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1947 AR5416_EEP_MINOR_VER_16) ||
1948 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1949 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1952 if (AR_SREV_9300_20_OR_LATER(ah))
1953 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1955 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1956 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1958 if (AR_SREV_9285(ah))
1959 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1961 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1962 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1963 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1969 /****************************/
1970 /* GPIO / RFKILL / Antennae */
1971 /****************************/
1973 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1977 u32 gpio_shift, tmp;
1980 addr = AR_GPIO_OUTPUT_MUX3;
1982 addr = AR_GPIO_OUTPUT_MUX2;
1984 addr = AR_GPIO_OUTPUT_MUX1;
1986 gpio_shift = (gpio % 6) * 5;
1988 if (AR_SREV_9280_20_OR_LATER(ah)
1989 || (addr != AR_GPIO_OUTPUT_MUX1)) {
1990 REG_RMW(ah, addr, (type << gpio_shift),
1991 (0x1f << gpio_shift));
1993 tmp = REG_READ(ah, addr);
1994 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
1995 tmp &= ~(0x1f << gpio_shift);
1996 tmp |= (type << gpio_shift);
1997 REG_WRITE(ah, addr, tmp);
2001 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2005 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2007 if (AR_DEVID_7010(ah)) {
2009 REG_RMW(ah, AR7010_GPIO_OE,
2010 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2011 (AR7010_GPIO_OE_MASK << gpio_shift));
2015 gpio_shift = gpio << 1;
2018 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2019 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2021 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2023 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2025 #define MS_REG_READ(x, y) \
2026 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2028 if (gpio >= ah->caps.num_gpio_pins)
2031 if (AR_DEVID_7010(ah)) {
2033 val = REG_READ(ah, AR7010_GPIO_IN);
2034 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2035 } else if (AR_SREV_9300_20_OR_LATER(ah))
2036 return MS_REG_READ(AR9300, gpio) != 0;
2037 else if (AR_SREV_9271(ah))
2038 return MS_REG_READ(AR9271, gpio) != 0;
2039 else if (AR_SREV_9287_11_OR_LATER(ah))
2040 return MS_REG_READ(AR9287, gpio) != 0;
2041 else if (AR_SREV_9285_12_OR_LATER(ah))
2042 return MS_REG_READ(AR9285, gpio) != 0;
2043 else if (AR_SREV_9280_20_OR_LATER(ah))
2044 return MS_REG_READ(AR928X, gpio) != 0;
2046 return MS_REG_READ(AR, gpio) != 0;
2048 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2050 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2055 if (AR_DEVID_7010(ah)) {
2057 REG_RMW(ah, AR7010_GPIO_OE,
2058 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2059 (AR7010_GPIO_OE_MASK << gpio_shift));
2063 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2064 gpio_shift = 2 * gpio;
2067 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2068 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2070 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2072 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2074 if (AR_DEVID_7010(ah)) {
2076 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2081 if (AR_SREV_9271(ah))
2084 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2087 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2089 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2091 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2093 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2095 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2097 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2099 EXPORT_SYMBOL(ath9k_hw_setantenna);
2101 /*********************/
2102 /* General Operation */
2103 /*********************/
2105 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2107 u32 bits = REG_READ(ah, AR_RX_FILTER);
2108 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2110 if (phybits & AR_PHY_ERR_RADAR)
2111 bits |= ATH9K_RX_FILTER_PHYRADAR;
2112 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2113 bits |= ATH9K_RX_FILTER_PHYERR;
2117 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2119 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2123 ENABLE_REGWRITE_BUFFER(ah);
2125 REG_WRITE(ah, AR_RX_FILTER, bits);
2128 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2129 phybits |= AR_PHY_ERR_RADAR;
2130 if (bits & ATH9K_RX_FILTER_PHYERR)
2131 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2132 REG_WRITE(ah, AR_PHY_ERR, phybits);
2135 REG_WRITE(ah, AR_RXCFG,
2136 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2138 REG_WRITE(ah, AR_RXCFG,
2139 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2141 REGWRITE_BUFFER_FLUSH(ah);
2143 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2145 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2147 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2150 ath9k_hw_init_pll(ah, NULL);
2153 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2155 bool ath9k_hw_disable(struct ath_hw *ah)
2157 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2160 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2163 ath9k_hw_init_pll(ah, NULL);
2166 EXPORT_SYMBOL(ath9k_hw_disable);
2168 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2170 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2171 struct ath9k_channel *chan = ah->curchan;
2172 struct ieee80211_channel *channel = chan->chan;
2174 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2176 ah->eep_ops->set_txpower(ah, chan,
2177 ath9k_regd_get_ctl(regulatory, chan),
2178 channel->max_antenna_gain * 2,
2179 channel->max_power * 2,
2180 min((u32) MAX_RATE_POWER,
2181 (u32) regulatory->power_limit));
2183 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2185 void ath9k_hw_setopmode(struct ath_hw *ah)
2187 ath9k_hw_set_operating_mode(ah, ah->opmode);
2189 EXPORT_SYMBOL(ath9k_hw_setopmode);
2191 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2193 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2194 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2196 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2198 void ath9k_hw_write_associd(struct ath_hw *ah)
2200 struct ath_common *common = ath9k_hw_common(ah);
2202 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2203 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2204 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2206 EXPORT_SYMBOL(ath9k_hw_write_associd);
2208 #define ATH9K_MAX_TSF_READ 10
2210 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2212 u32 tsf_lower, tsf_upper1, tsf_upper2;
2215 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2216 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2217 tsf_lower = REG_READ(ah, AR_TSF_L32);
2218 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2219 if (tsf_upper2 == tsf_upper1)
2221 tsf_upper1 = tsf_upper2;
2224 WARN_ON( i == ATH9K_MAX_TSF_READ );
2226 return (((u64)tsf_upper1 << 32) | tsf_lower);
2228 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2230 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2232 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2233 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2235 EXPORT_SYMBOL(ath9k_hw_settsf64);
2237 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2239 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2240 AH_TSF_WRITE_TIMEOUT))
2241 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2242 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2244 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2246 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2248 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2251 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2253 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2255 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2257 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2259 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2262 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2263 macmode = AR_2040_JOINED_RX_CLEAR;
2267 REG_WRITE(ah, AR_2040_MODE, macmode);
2270 /* HW Generic timers configuration */
2272 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2274 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2275 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2276 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2277 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2278 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2279 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2280 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2281 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2282 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2283 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2284 AR_NDP2_TIMER_MODE, 0x0002},
2285 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2286 AR_NDP2_TIMER_MODE, 0x0004},
2287 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2288 AR_NDP2_TIMER_MODE, 0x0008},
2289 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2290 AR_NDP2_TIMER_MODE, 0x0010},
2291 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2292 AR_NDP2_TIMER_MODE, 0x0020},
2293 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2294 AR_NDP2_TIMER_MODE, 0x0040},
2295 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2296 AR_NDP2_TIMER_MODE, 0x0080}
2299 /* HW generic timer primitives */
2301 /* compute and clear index of rightmost 1 */
2302 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2312 return timer_table->gen_timer_index[b];
2315 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2317 return REG_READ(ah, AR_TSF_L32);
2319 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2321 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2322 void (*trigger)(void *),
2323 void (*overflow)(void *),
2327 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2328 struct ath_gen_timer *timer;
2330 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2332 if (timer == NULL) {
2333 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2334 "Failed to allocate memory"
2335 "for hw timer[%d]\n", timer_index);
2339 /* allocate a hardware generic timer slot */
2340 timer_table->timers[timer_index] = timer;
2341 timer->index = timer_index;
2342 timer->trigger = trigger;
2343 timer->overflow = overflow;
2348 EXPORT_SYMBOL(ath_gen_timer_alloc);
2350 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2351 struct ath_gen_timer *timer,
2355 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2358 BUG_ON(!timer_period);
2360 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2362 tsf = ath9k_hw_gettsf32(ah);
2364 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2365 "curent tsf %x period %x"
2366 "timer_next %x\n", tsf, timer_period, timer_next);
2369 * Pull timer_next forward if the current TSF already passed it
2370 * because of software latency
2372 if (timer_next < tsf)
2373 timer_next = tsf + timer_period;
2376 * Program generic timer registers
2378 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2380 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2382 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2383 gen_tmr_configuration[timer->index].mode_mask);
2385 /* Enable both trigger and thresh interrupt masks */
2386 REG_SET_BIT(ah, AR_IMR_S5,
2387 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2388 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2390 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2392 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2394 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2396 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2397 (timer->index >= ATH_MAX_GEN_TIMER)) {
2401 /* Clear generic timer enable bits. */
2402 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2403 gen_tmr_configuration[timer->index].mode_mask);
2405 /* Disable both trigger and thresh interrupt masks */
2406 REG_CLR_BIT(ah, AR_IMR_S5,
2407 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2408 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2410 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2412 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2414 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2416 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2418 /* free the hardware generic timer slot */
2419 timer_table->timers[timer->index] = NULL;
2422 EXPORT_SYMBOL(ath_gen_timer_free);
2425 * Generic Timer Interrupts handling
2427 void ath_gen_timer_isr(struct ath_hw *ah)
2429 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2430 struct ath_gen_timer *timer;
2431 struct ath_common *common = ath9k_hw_common(ah);
2432 u32 trigger_mask, thresh_mask, index;
2434 /* get hardware generic timer interrupt status */
2435 trigger_mask = ah->intr_gen_timer_trigger;
2436 thresh_mask = ah->intr_gen_timer_thresh;
2437 trigger_mask &= timer_table->timer_mask.val;
2438 thresh_mask &= timer_table->timer_mask.val;
2440 trigger_mask &= ~thresh_mask;
2442 while (thresh_mask) {
2443 index = rightmost_index(timer_table, &thresh_mask);
2444 timer = timer_table->timers[index];
2446 ath_print(common, ATH_DBG_HWTIMER,
2447 "TSF overflow for Gen timer %d\n", index);
2448 timer->overflow(timer->arg);
2451 while (trigger_mask) {
2452 index = rightmost_index(timer_table, &trigger_mask);
2453 timer = timer_table->timers[index];
2455 ath_print(common, ATH_DBG_HWTIMER,
2456 "Gen timer[%d] trigger\n", index);
2457 timer->trigger(timer->arg);
2460 EXPORT_SYMBOL(ath_gen_timer_isr);
2466 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2468 ah->htc_reset_init = true;
2470 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2475 } ath_mac_bb_names[] = {
2476 /* Devices with external radios */
2477 { AR_SREV_VERSION_5416_PCI, "5416" },
2478 { AR_SREV_VERSION_5416_PCIE, "5418" },
2479 { AR_SREV_VERSION_9100, "9100" },
2480 { AR_SREV_VERSION_9160, "9160" },
2481 /* Single-chip solutions */
2482 { AR_SREV_VERSION_9280, "9280" },
2483 { AR_SREV_VERSION_9285, "9285" },
2484 { AR_SREV_VERSION_9287, "9287" },
2485 { AR_SREV_VERSION_9271, "9271" },
2486 { AR_SREV_VERSION_9300, "9300" },
2489 /* For devices with external radios */
2493 } ath_rf_names[] = {
2495 { AR_RAD5133_SREV_MAJOR, "5133" },
2496 { AR_RAD5122_SREV_MAJOR, "5122" },
2497 { AR_RAD2133_SREV_MAJOR, "2133" },
2498 { AR_RAD2122_SREV_MAJOR, "2122" }
2502 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2504 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2508 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2509 if (ath_mac_bb_names[i].version == mac_bb_version) {
2510 return ath_mac_bb_names[i].name;
2518 * Return the RF name. "????" is returned if the RF is unknown.
2519 * Used for devices with external radios.
2521 static const char *ath9k_hw_rf_name(u16 rf_version)
2525 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2526 if (ath_rf_names[i].version == rf_version) {
2527 return ath_rf_names[i].name;
2534 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2538 /* chipsets >= AR9280 are single-chip */
2539 if (AR_SREV_9280_20_OR_LATER(ah)) {
2540 used = snprintf(hw_name, len,
2541 "Atheros AR%s Rev:%x",
2542 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2543 ah->hw_version.macRev);
2546 used = snprintf(hw_name, len,
2547 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2548 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2549 ah->hw_version.macRev,
2550 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2551 AR_RADIO_SREV_MAJOR)),
2552 ah->hw_version.phyRev);
2555 hw_name[used] = '\0';
2557 EXPORT_SYMBOL(ath9k_hw_name);