drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33
  34 MODULE_AUTHOR("Atheros Communications");
  35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  37 MODULE_LICENSE("Dual BSD/GPL");
  38
  39 static int __init ath9k_init(void)
  40 {
  41         return 0;
  42 }
  43 module_init(ath9k_init);
  44
  45 static void __exit ath9k_exit(void)
  46 {
  47         return;
  48 }
  49 module_exit(ath9k_exit);
  50
  51 /********************/
  52 /* Helper Functions */
  53 /********************/
  54
  55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  56 {
  57         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  58
  59         if (!ah->curchan) /* should really check for CCK instead */
  60                 return usecs *ATH9K_CLOCK_RATE_CCK;
  61         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  62                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  63         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  64 }
  65
  66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  69
  70         if (conf_is_ht40(conf))
  71                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  72         else
  73                 return ath9k_hw_mac_clks(ah, usecs);
  74 }
  75
  76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  77 {
  78         int i;
  79
  80         BUG_ON(timeout < AH_TIME_QUANTUM);
  81
  82         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  83                 if ((REG_READ(ah, reg) & mask) == val)
  84                         return true;
  85
  86                 udelay(AH_TIME_QUANTUM);
  87         }
  88
  89         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  90                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  91                   timeout, reg, REG_READ(ah, reg), mask, val);
  92
  93         return false;
  94 }
  95 EXPORT_SYMBOL(ath9k_hw_wait);
  96
  97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  98 {
  99         u32 retval;
 100         int i;
 101
 102         for (i = 0, retval = 0; i < n; i++) {
 103                 retval = (retval << 1) | (val & 1);
 104                 val >>= 1;
 105         }
 106         return retval;
 107 }
 108
 109 bool ath9k_get_channel_edges(struct ath_hw *ah,
 110                              u16 flags, u16 *low,
 111                              u16 *high)
 112 {
 113         struct ath9k_hw_capabilities *pCap = &ah->caps;
 114
 115         if (flags & CHANNEL_5GHZ) {
 116                 *low = pCap->low_5ghz_chan;
 117                 *high = pCap->high_5ghz_chan;
 118                 return true;
 119         }
 120         if ((flags & CHANNEL_2GHZ)) {
 121                 *low = pCap->low_2ghz_chan;
 122                 *high = pCap->high_2ghz_chan;
 123                 return true;
 124         }
 125         return false;
 126 }
 127
 128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 129                            u8 phy, int kbps,
 130                            u32 frameLen, u16 rateix,
 131                            bool shortPreamble)
 132 {
 133         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 134
 135         if (kbps == 0)
 136                 return 0;
 137
 138         switch (phy) {
 139         case WLAN_RC_PHY_CCK:
 140                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 141                 if (shortPreamble)
 142                         phyTime >>= 1;
 143                 numBits = frameLen << 3;
 144                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 145                 break;
 146         case WLAN_RC_PHY_OFDM:
 147                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 148                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 149                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 150                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 151                         txTime = OFDM_SIFS_TIME_QUARTER
 152                                 + OFDM_PREAMBLE_TIME_QUARTER
 153                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 154                 } else if (ah->curchan &&
 155                            IS_CHAN_HALF_RATE(ah->curchan)) {
 156                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 157                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 158                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 159                         txTime = OFDM_SIFS_TIME_HALF +
 160                                 OFDM_PREAMBLE_TIME_HALF
 161                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 162                 } else {
 163                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 164                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 165                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 166                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 167                                 + (numSymbols * OFDM_SYMBOL_TIME);
 168                 }
 169                 break;
 170         default:
 171                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 172                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 173                 txTime = 0;
 174                 break;
 175         }
 176
 177         return txTime;
 178 }
 179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 180
 181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 182                                   struct ath9k_channel *chan,
 183                                   struct chan_centers *centers)
 184 {
 185         int8_t extoff;
 186
 187         if (!IS_CHAN_HT40(chan)) {
 188                 centers->ctl_center = centers->ext_center =
 189                         centers->synth_center = chan->channel;
 190                 return;
 191         }
 192
 193         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 194             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 195                 centers->synth_center =
 196                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 197                 extoff = 1;
 198         } else {
 199                 centers->synth_center =
 200                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 201                 extoff = -1;
 202         }
 203
 204         centers->ctl_center =
 205                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 206         /* 25 MHz spacing is supported by hw but not on upper layers */
 207         centers->ext_center =
 208                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 209 }
 210
 211 /******************/
 212 /* Chip Revisions */
 213 /******************/
 214
 215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 216 {
 217         u32 val;
 218
 219         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 220
 221         if (val == 0xFF) {
 222                 val = REG_READ(ah, AR_SREV);
 223                 ah->hw_version.macVersion =
 224                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 225                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 226                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 227         } else {
 228                 if (!AR_SREV_9100(ah))
 229                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 230
 231                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 232
 233                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 234                         ah->is_pciexpress = true;
 235         }
 236 }
 237
 238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 239 {
 240         u32 val;
 241         int i;
 242
 243         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 244
 245         for (i = 0; i < 8; i++)
 246                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 247         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 248         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 249
 250         return ath9k_hw_reverse_bits(val, 8);
 251 }
 252
 253 /************************************/
 254 /* HW Attach, Detach, Init Routines */
 255 /************************************/
 256
 257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 258 {
 259         if (AR_SREV_9100(ah))
 260                 return;
 261
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 269         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 270         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 271
 272         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 273 }
 274
 275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 276 {
 277         struct ath_common *common = ath9k_hw_common(ah);
 278         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 279         u32 regHold[2];
 280         u32 patternData[4] = { 0x55555555,
 281                                0xaaaaaaaa,
 282                                0x66666666,
 283                                0x99999999 };
 284         int i, j;
 285
 286         for (i = 0; i < 2; i++) {
 287                 u32 addr = regAddr[i];
 288                 u32 wrData, rdData;
 289
 290                 regHold[i] = REG_READ(ah, addr);
 291                 for (j = 0; j < 0x100; j++) {
 292                         wrData = (j << 16) | j;
 293                         REG_WRITE(ah, addr, wrData);
 294                         rdData = REG_READ(ah, addr);
 295                         if (rdData != wrData) {
 296                                 ath_print(common, ATH_DBG_FATAL,
 297                                           "address test failed "
 298                                           "addr: 0x%08x - wr:0x%08x != "
 299                                           "rd:0x%08x\n",
 300                                           addr, wrData, rdData);
 301                                 return false;
 302                         }
 303                 }
 304                 for (j = 0; j < 4; j++) {
 305                         wrData = patternData[j];
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (wrData != rdData) {
 309                                 ath_print(common, ATH_DBG_FATAL,
 310                                           "address test failed "
 311                                           "addr: 0x%08x - wr:0x%08x != "
 312                                           "rd:0x%08x\n",
 313                                           addr, wrData, rdData);
 314                                 return false;
 315                         }
 316                 }
 317                 REG_WRITE(ah, regAddr[i], regHold[i]);
 318         }
 319         udelay(100);
 320
 321         return true;
 322 }
 323
 324 static void ath9k_hw_init_config(struct ath_hw *ah)
 325 {
 326         int i;
 327
 328         ah->config.dma_beacon_response_time = 2;
 329         ah->config.sw_beacon_response_time = 10;
 330         ah->config.additional_swba_backoff = 0;
 331         ah->config.ack_6mb = 0x0;
 332         ah->config.cwm_ignore_extcca = 0;
 333         ah->config.pcie_powersave_enable = 0;
 334         ah->config.pcie_clock_req = 0;
 335         ah->config.pcie_waen = 0;
 336         ah->config.analog_shiftreg = 1;
 337         ah->config.ht_enable = 1;
 338         ah->config.ofdm_trig_low = 200;
 339         ah->config.ofdm_trig_high = 500;
 340         ah->config.cck_trig_high = 200;
 341         ah->config.cck_trig_low = 100;
 342         ah->config.enable_ani = 1;
 343
 344         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 345                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 346                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 347         }
 348
 349         ah->config.rx_intr_mitigation = true;
 350
 351         /*
 352          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 353          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 354          * This means we use it for all AR5416 devices, and the few
 355          * minor PCI AR9280 devices out there.
 356          *
 357          * Serialization is required because these devices do not handle
 358          * well the case of two concurrent reads/writes due to the latency
 359          * involved. During one read/write another read/write can be issued
 360          * on another CPU while the previous read/write may still be working
 361          * on our hardware, if we hit this case the hardware poops in a loop.
 362          * We prevent this by serializing reads and writes.
 363          *
 364          * This issue is not present on PCI-Express devices or pre-AR5416
 365          * devices (legacy, 802.11abg).
 366          */
 367         if (num_possible_cpus() > 1)
 368                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 369 }
 370 EXPORT_SYMBOL(ath9k_hw_init);
 371
 372 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 373 {
 374         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 375
 376         regulatory->country_code = CTRY_DEFAULT;
 377         regulatory->power_limit = MAX_RATE_POWER;
 378         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 379
 380         ah->hw_version.magic = AR5416_MAGIC;
 381         ah->hw_version.subvendorid = 0;
 382
 383         ah->ah_flags = 0;
 384         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 385                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 386         if (!AR_SREV_9100(ah))
 387                 ah->ah_flags = AH_USE_EEPROM;
 388
 389         ah->atim_window = 0;
 390         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 391         ah->beacon_interval = 100;
 392         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 393         ah->slottime = (u32) -1;
 394         ah->globaltxtimeout = (u32) -1;
 395         ah->power_mode = ATH9K_PM_UNDEFINED;
 396 }
 397
 398 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 399 {
 400         u32 val;
 401
 402         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 403
 404         val = ath9k_hw_get_radiorev(ah);
 405         switch (val & AR_RADIO_SREV_MAJOR) {
 406         case 0:
 407                 val = AR_RAD5133_SREV_MAJOR;
 408                 break;
 409         case AR_RAD5133_SREV_MAJOR:
 410         case AR_RAD5122_SREV_MAJOR:
 411         case AR_RAD2133_SREV_MAJOR:
 412         case AR_RAD2122_SREV_MAJOR:
 413                 break;
 414         default:
 415                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 416                           "Radio Chip Rev 0x%02X not supported\n",
 417                           val & AR_RADIO_SREV_MAJOR);
 418                 return -EOPNOTSUPP;
 419         }
 420
 421         ah->hw_version.analog5GhzRev = val;
 422
 423         return 0;
 424 }
 425
 426 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 427 {
 428         struct ath_common *common = ath9k_hw_common(ah);
 429         u32 sum;
 430         int i;
 431         u16 eeval;
 432
 433         sum = 0;
 434         for (i = 0; i < 3; i++) {
 435                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 436                 sum += eeval;
 437                 common->macaddr[2 * i] = eeval >> 8;
 438                 common->macaddr[2 * i + 1] = eeval & 0xff;
 439         }
 440         if (sum == 0 || sum == 0xffff * 3)
 441                 return -EADDRNOTAVAIL;
 442
 443         return 0;
 444 }
 445
 446 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 447 {
 448         u32 rxgain_type;
 449
 450         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 451                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 452
 453                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 454                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 455                         ar9280Modes_backoff_13db_rxgain_9280_2,
 456                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 457                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 458                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 459                         ar9280Modes_backoff_23db_rxgain_9280_2,
 460                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 461                 else
 462                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 463                         ar9280Modes_original_rxgain_9280_2,
 464                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 465         } else {
 466                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 467                         ar9280Modes_original_rxgain_9280_2,
 468                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 469         }
 470 }
 471
 472 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 473 {
 474         u32 txgain_type;
 475
 476         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 477                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 478
 479                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 480                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 481                         ar9280Modes_high_power_tx_gain_9280_2,
 482                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 483                 else
 484                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9280Modes_original_tx_gain_9280_2,
 486                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 487         } else {
 488                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                 ar9280Modes_original_tx_gain_9280_2,
 490                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 491         }
 492 }
 493
 494 static int ath9k_hw_post_init(struct ath_hw *ah)
 495 {
 496         int ecode;
 497
 498         if (!ath9k_hw_chip_test(ah))
 499                 return -ENODEV;
 500
 501         ecode = ath9k_hw_rf_claim(ah);
 502         if (ecode != 0)
 503                 return ecode;
 504
 505         ecode = ath9k_hw_eeprom_init(ah);
 506         if (ecode != 0)
 507                 return ecode;
 508
 509         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 510                   "Eeprom VER: %d, REV: %d\n",
 511                   ah->eep_ops->get_eeprom_ver(ah),
 512                   ah->eep_ops->get_eeprom_rev(ah));
 513
 514         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 515                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 516                 if (ecode) {
 517                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 518                                   "Failed allocating banks for "
 519                                   "external radio\n");
 520                         return ecode;
 521                 }
 522         }
 523
 524         if (!AR_SREV_9100(ah)) {
 525                 ath9k_hw_ani_setup(ah);
 526                 ath9k_hw_ani_init(ah);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static bool ath9k_hw_devid_supported(u16 devid)
 533 {
 534         switch (devid) {
 535         case AR5416_DEVID_PCI:
 536         case AR5416_DEVID_PCIE:
 537         case AR5416_AR9100_DEVID:
 538         case AR9160_DEVID_PCI:
 539         case AR9280_DEVID_PCI:
 540         case AR9280_DEVID_PCIE:
 541         case AR9285_DEVID_PCIE:
 542         case AR5416_DEVID_AR9287_PCI:
 543         case AR5416_DEVID_AR9287_PCIE:
 544         case AR9271_USB:
 545                 return true;
 546         default:
 547                 break;
 548         }
 549         return false;
 550 }
 551
 552 static bool ath9k_hw_macversion_supported(u32 macversion)
 553 {
 554         switch (macversion) {
 555         case AR_SREV_VERSION_5416_PCI:
 556         case AR_SREV_VERSION_5416_PCIE:
 557         case AR_SREV_VERSION_9160:
 558         case AR_SREV_VERSION_9100:
 559         case AR_SREV_VERSION_9280:
 560         case AR_SREV_VERSION_9285:
 561         case AR_SREV_VERSION_9287:
 562         case AR_SREV_VERSION_9271:
 563                 return true;
 564         default:
 565                 break;
 566         }
 567         return false;
 568 }
 569
 570 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 571 {
 572         if (AR_SREV_9160_10_OR_LATER(ah)) {
 573                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 574                         ah->iq_caldata.calData = &iq_cal_single_sample;
 575                         ah->adcgain_caldata.calData =
 576                                 &adc_gain_cal_single_sample;
 577                         ah->adcdc_caldata.calData =
 578                                 &adc_dc_cal_single_sample;
 579                         ah->adcdc_calinitdata.calData =
 580                                 &adc_init_dc_cal;
 581                 } else {
 582                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 583                         ah->adcgain_caldata.calData =
 584                                 &adc_gain_cal_multi_sample;
 585                         ah->adcdc_caldata.calData =
 586                                 &adc_dc_cal_multi_sample;
 587                         ah->adcdc_calinitdata.calData =
 588                                 &adc_init_dc_cal;
 589                 }
 590                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 591         }
 592 }
 593
 594 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 595 {
 596         if (AR_SREV_9271(ah)) {
 597                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 598                                ARRAY_SIZE(ar9271Modes_9271), 6);
 599                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 600                                ARRAY_SIZE(ar9271Common_9271), 2);
 601                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 602                                ar9271Modes_9271_1_0_only,
 603                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 604                 return;
 605         }
 606
 607         if (AR_SREV_9287_11_OR_LATER(ah)) {
 608                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 609                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 610                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 611                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 612                 if (ah->config.pcie_clock_req)
 613                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 614                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 615                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 616                 else
 617                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 618                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 619                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 620                                         2);
 621         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 622                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 623                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 624                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 625                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 626
 627                 if (ah->config.pcie_clock_req)
 628                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 629                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 630                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 631                 else
 632                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 633                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 634                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 635                                   2);
 636         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 637
 638
 639                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 640                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 641                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 642                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 643
 644                 if (ah->config.pcie_clock_req) {
 645                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 646                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 647                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 648                 } else {
 649                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 650                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 651                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 652                                   2);
 653                 }
 654         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 655                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 656                                ARRAY_SIZE(ar9285Modes_9285), 6);
 657                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 658                                ARRAY_SIZE(ar9285Common_9285), 2);
 659
 660                 if (ah->config.pcie_clock_req) {
 661                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 662                         ar9285PciePhy_clkreq_off_L1_9285,
 663                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 664                 } else {
 665                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 666                         ar9285PciePhy_clkreq_always_on_L1_9285,
 667                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 668                 }
 669         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 670                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 671                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 672                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 673                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 674
 675                 if (ah->config.pcie_clock_req) {
 676                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 677                                ar9280PciePhy_clkreq_off_L1_9280,
 678                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 679                 } else {
 680                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 681                                ar9280PciePhy_clkreq_always_on_L1_9280,
 682                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 683                 }
 684                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 685                                ar9280Modes_fast_clock_9280_2,
 686                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 687         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 688                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 689                                ARRAY_SIZE(ar9280Modes_9280), 6);
 690                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 691                                ARRAY_SIZE(ar9280Common_9280), 2);
 692         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 693                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 694                                ARRAY_SIZE(ar5416Modes_9160), 6);
 695                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 696                                ARRAY_SIZE(ar5416Common_9160), 2);
 697                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 698                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 699                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 700                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 701                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 702                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 703                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 704                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 705                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 706                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 707                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 708                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 709                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 710                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 711                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 712                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 713                 if (AR_SREV_9160_11(ah)) {
 714                         INIT_INI_ARRAY(&ah->iniAddac,
 715                                        ar5416Addac_91601_1,
 716                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 717                 } else {
 718                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 719                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 720                 }
 721         } else if (AR_SREV_9100_OR_LATER(ah)) {
 722                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 723                                ARRAY_SIZE(ar5416Modes_9100), 6);
 724                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 725                                ARRAY_SIZE(ar5416Common_9100), 2);
 726                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 727                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 728                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 729                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 730                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 731                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 732                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 733                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 734                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 735                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 736                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 737                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 738                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 739                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 740                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 741                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 742                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 743                                ARRAY_SIZE(ar5416Addac_9100), 2);
 744         } else {
 745                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 746                                ARRAY_SIZE(ar5416Modes), 6);
 747                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 748                                ARRAY_SIZE(ar5416Common), 2);
 749                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 750                                ARRAY_SIZE(ar5416Bank0), 2);
 751                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 752                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 753                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 754                                ARRAY_SIZE(ar5416Bank1), 2);
 755                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 756                                ARRAY_SIZE(ar5416Bank2), 2);
 757                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 758                                ARRAY_SIZE(ar5416Bank3), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 760                                ARRAY_SIZE(ar5416Bank6), 3);
 761                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 762                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 763                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 764                                ARRAY_SIZE(ar5416Bank7), 2);
 765                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 766                                ARRAY_SIZE(ar5416Addac), 2);
 767         }
 768 }
 769
 770 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 771 {
 772         if (AR_SREV_9287_11_OR_LATER(ah))
 773                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 774                 ar9287Modes_rx_gain_9287_1_1,
 775                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 776         else if (AR_SREV_9287_10(ah))
 777                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 778                 ar9287Modes_rx_gain_9287_1_0,
 779                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 780         else if (AR_SREV_9280_20(ah))
 781                 ath9k_hw_init_rxgain_ini(ah);
 782
 783         if (AR_SREV_9287_11_OR_LATER(ah)) {
 784                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 785                 ar9287Modes_tx_gain_9287_1_1,
 786                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 787         } else if (AR_SREV_9287_10(ah)) {
 788                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 789                 ar9287Modes_tx_gain_9287_1_0,
 790                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 791         } else if (AR_SREV_9280_20(ah)) {
 792                 ath9k_hw_init_txgain_ini(ah);
 793         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 794                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 795
 796                 /* txgain table */
 797                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 798                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 799                         ar9285Modes_high_power_tx_gain_9285_1_2,
 800                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 801                 } else {
 802                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 803                         ar9285Modes_original_tx_gain_9285_1_2,
 804                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 805                 }
 806
 807         }
 808 }
 809
 810 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 811 {
 812         u32 i, j;
 813
 814         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 815             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 816
 817                 /* EEPROM Fixup */
 818                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 819                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 820
 821                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 822                                 u32 val = INI_RA(&ah->iniModes, i, j);
 823
 824                                 INI_RA(&ah->iniModes, i, j) =
 825                                         ath9k_hw_ini_fixup(ah,
 826                                                            &ah->eeprom.def,
 827                                                            reg, val);
 828                         }
 829                 }
 830         }
 831 }
 832
 833 int ath9k_hw_init(struct ath_hw *ah)
 834 {
 835         struct ath_common *common = ath9k_hw_common(ah);
 836         int r = 0;
 837
 838         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 839                 ath_print(common, ATH_DBG_FATAL,
 840                           "Unsupported device ID: 0x%0x\n",
 841                           ah->hw_version.devid);
 842                 return -EOPNOTSUPP;
 843         }
 844
 845         ath9k_hw_init_defaults(ah);
 846         ath9k_hw_init_config(ah);
 847
 848         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 849                 ath_print(common, ATH_DBG_FATAL,
 850                           "Couldn't reset chip\n");
 851                 return -EIO;
 852         }
 853
 854         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 855                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 856                 return -EIO;
 857         }
 858
 859         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 860                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 861                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 862                         ah->config.serialize_regmode =
 863                                 SER_REG_MODE_ON;
 864                 } else {
 865                         ah->config.serialize_regmode =
 866                                 SER_REG_MODE_OFF;
 867                 }
 868         }
 869
 870         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 871                 ah->config.serialize_regmode);
 872
 873         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 874                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 875         else
 876                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 877
 878         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 879                 ath_print(common, ATH_DBG_FATAL,
 880                           "Mac Chip Rev 0x%02x.%x is not supported by "
 881                           "this driver\n", ah->hw_version.macVersion,
 882                           ah->hw_version.macRev);
 883                 return -EOPNOTSUPP;
 884         }
 885
 886         if (AR_SREV_9100(ah)) {
 887                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 888                 ah->supp_cals = IQ_MISMATCH_CAL;
 889                 ah->is_pciexpress = false;
 890         }
 891
 892         if (AR_SREV_9271(ah))
 893                 ah->is_pciexpress = false;
 894
 895         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 896
 897         ath9k_hw_init_cal_settings(ah);
 898
 899         ah->ani_function = ATH9K_ANI_ALL;
 900         if (AR_SREV_9280_10_OR_LATER(ah)) {
 901                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 902                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 903                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 904         } else {
 905                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 906                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 907         }
 908
 909         ath9k_hw_init_mode_regs(ah);
 910
 911         if (ah->is_pciexpress)
 912                 ath9k_hw_configpcipowersave(ah, 0, 0);
 913         else
 914                 ath9k_hw_disablepcie(ah);
 915
 916         /* Support for Japan ch.14 (2484) spread */
 917         if (AR_SREV_9287_11_OR_LATER(ah)) {
 918                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 919                        ar9287Common_normal_cck_fir_coeff_92871_1,
 920                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 921                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 922                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 923                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 924         }
 925
 926         r = ath9k_hw_post_init(ah);
 927         if (r)
 928                 return r;
 929
 930         ath9k_hw_init_mode_gain_regs(ah);
 931         r = ath9k_hw_fill_cap_info(ah);
 932         if (r)
 933                 return r;
 934
 935         ath9k_hw_init_11a_eeprom_fix(ah);
 936
 937         r = ath9k_hw_init_macaddr(ah);
 938         if (r) {
 939                 ath_print(common, ATH_DBG_FATAL,
 940                           "Failed to initialize MAC address\n");
 941                 return r;
 942         }
 943
 944         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 945                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 946         else
 947                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 948
 949         ath9k_init_nfcal_hist_buffer(ah);
 950
 951         common->state = ATH_HW_INITIALIZED;
 952
 953         return 0;
 954 }
 955
 956 static void ath9k_hw_init_bb(struct ath_hw *ah,
 957                              struct ath9k_channel *chan)
 958 {
 959         u32 synthDelay;
 960
 961         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 962         if (IS_CHAN_B(chan))
 963                 synthDelay = (4 * synthDelay) / 22;
 964         else
 965                 synthDelay /= 10;
 966
 967         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 968
 969         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 970 }
 971
 972 static void ath9k_hw_init_qos(struct ath_hw *ah)
 973 {
 974         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 975         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 976
 977         REG_WRITE(ah, AR_QOS_NO_ACK,
 978                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 979                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 980                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 981
 982         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 983         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 984         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 985         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 986         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 987 }
 988
 989 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
 990 {
 991         u32 lcr;
 992         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
 993
 994         lcr = REG_READ(ah , 0x5100c);
 995         lcr |= 0x80;
 996
 997         REG_WRITE(ah, 0x5100c, lcr);
 998         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
 999         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1000
1001         lcr &= ~0x80;
1002         REG_WRITE(ah, 0x5100c, lcr);
1003 }
1004
1005 static void ath9k_hw_init_pll(struct ath_hw *ah,
1006                               struct ath9k_channel *chan)
1007 {
1008         u32 pll;
1009
1010         if (AR_SREV_9100(ah)) {
1011                 if (chan && IS_CHAN_5GHZ(chan))
1012                         pll = 0x1450;
1013                 else
1014                         pll = 0x1458;
1015         } else {
1016                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1017                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1018
1019                         if (chan && IS_CHAN_HALF_RATE(chan))
1020                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1021                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1022                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1023
1024                         if (chan && IS_CHAN_5GHZ(chan)) {
1025                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1026
1027
1028                                 if (AR_SREV_9280_20(ah)) {
1029                                         if (((chan->channel % 20) == 0)
1030                                             || ((chan->channel % 10) == 0))
1031                                                 pll = 0x2850;
1032                                         else
1033                                                 pll = 0x142c;
1034                                 }
1035                         } else {
1036                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1037                         }
1038
1039                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1040
1041                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1042
1043                         if (chan && IS_CHAN_HALF_RATE(chan))
1044                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1045                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1046                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1047
1048                         if (chan && IS_CHAN_5GHZ(chan))
1049                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1050                         else
1051                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1052                 } else {
1053                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1054
1055                         if (chan && IS_CHAN_HALF_RATE(chan))
1056                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1057                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1058                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1059
1060                         if (chan && IS_CHAN_5GHZ(chan))
1061                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1062                         else
1063                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1064                 }
1065         }
1066         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1067
1068         /* Switch the core clock for ar9271 to 117Mhz */
1069         if (AR_SREV_9271(ah)) {
1070                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1071                         udelay(500);
1072                         /* set CLKOBS to output AHB clock */
1073                         REG_WRITE(ah, 0x7020, 0xe);
1074                         /*
1075                          * 0x304: 117Mhz, ahb_ratio: 1x1
1076                          * 0x306: 40Mhz, ahb_ratio: 1x1
1077                          */
1078                         REG_WRITE(ah, 0x50040, 0x304);
1079                         /*
1080                          * makes adjustments for the baud dividor to keep the
1081                          * targetted baud rate based on the used core clock.
1082                          */
1083                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1084                                                     AR9271_TARGET_BAUD_RATE);
1085                 }
1086         }
1087
1088         udelay(RTC_PLL_SETTLE_DELAY);
1089
1090         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1091 }
1092
1093 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1094 {
1095         int rx_chainmask, tx_chainmask;
1096
1097         rx_chainmask = ah->rxchainmask;
1098         tx_chainmask = ah->txchainmask;
1099
1100         switch (rx_chainmask) {
1101         case 0x5:
1102                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1103                             AR_PHY_SWAP_ALT_CHAIN);
1104         case 0x3:
1105                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1106                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1107                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1108                         break;
1109                 }
1110         case 0x1:
1111         case 0x2:
1112         case 0x7:
1113                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1114                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1115                 break;
1116         default:
1117                 break;
1118         }
1119
1120         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1121         if (tx_chainmask == 0x5) {
1122                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1123                             AR_PHY_SWAP_ALT_CHAIN);
1124         }
1125         if (AR_SREV_9100(ah))
1126                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1127                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1128 }
1129
1130 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1131                                           enum nl80211_iftype opmode)
1132 {
1133         ah->mask_reg = AR_IMR_TXERR |
1134                 AR_IMR_TXURN |
1135                 AR_IMR_RXERR |
1136                 AR_IMR_RXORN |
1137                 AR_IMR_BCNMISC;
1138
1139         if (ah->config.rx_intr_mitigation)
1140                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1141         else
1142                 ah->mask_reg |= AR_IMR_RXOK;
1143
1144         ah->mask_reg |= AR_IMR_TXOK;
1145
1146         if (opmode == NL80211_IFTYPE_AP)
1147                 ah->mask_reg |= AR_IMR_MIB;
1148
1149         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1150         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1151
1152         if (!AR_SREV_9100(ah)) {
1153                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1154                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1155                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1156         }
1157 }
1158
1159 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1160 {
1161         u32 val = ath9k_hw_mac_to_clks(ah, us);
1162         val = min(val, (u32) 0xFFFF);
1163         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1164 }
1165
1166 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1167 {
1168         u32 val = ath9k_hw_mac_to_clks(ah, us);
1169         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1170         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1171 }
1172
1173 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1174 {
1175         u32 val = ath9k_hw_mac_to_clks(ah, us);
1176         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1177         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1178 }
1179
1180 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1181 {
1182         if (tu > 0xFFFF) {
1183                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1184                           "bad global tx timeout %u\n", tu);
1185                 ah->globaltxtimeout = (u32) -1;
1186                 return false;
1187         } else {
1188                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1189                 ah->globaltxtimeout = tu;
1190                 return true;
1191         }
1192 }
1193
1194 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1195 {
1196         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1197         int acktimeout;
1198         int sifstime;
1199
1200         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1201                   ah->misc_mode);
1202
1203         if (ah->misc_mode != 0)
1204                 REG_WRITE(ah, AR_PCU_MISC,
1205                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1206
1207         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1208                 sifstime = 16;
1209         else
1210                 sifstime = 10;
1211
1212         acktimeout = ah->slottime + sifstime;
1213         ath9k_hw_setslottime(ah, ah->slottime);
1214         ath9k_hw_set_ack_timeout(ah, acktimeout);
1215         ath9k_hw_set_cts_timeout(ah, acktimeout);
1216         if (ah->globaltxtimeout != (u32) -1)
1217                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1218 }
1219 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1220
1221 void ath9k_hw_deinit(struct ath_hw *ah)
1222 {
1223         struct ath_common *common = ath9k_hw_common(ah);
1224
1225         if (common->state <= ATH_HW_INITIALIZED)
1226                 goto free_hw;
1227
1228         if (!AR_SREV_9100(ah))
1229                 ath9k_hw_ani_disable(ah);
1230
1231         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1232
1233 free_hw:
1234         if (!AR_SREV_9280_10_OR_LATER(ah))
1235                 ath9k_hw_rf_free_ext_banks(ah);
1236         kfree(ah);
1237         ah = NULL;
1238 }
1239 EXPORT_SYMBOL(ath9k_hw_deinit);
1240
1241 /*******/
1242 /* INI */
1243 /*******/
1244
1245 static void ath9k_hw_override_ini(struct ath_hw *ah,
1246                                   struct ath9k_channel *chan)
1247 {
1248         u32 val;
1249
1250         if (AR_SREV_9271(ah)) {
1251                 /*
1252                  * Enable spectral scan to solution for issues with stuck
1253                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1254                  * AR9271 1.1
1255                  */
1256                 if (AR_SREV_9271_10(ah)) {
1257                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1258                               AR_PHY_SPECTRAL_SCAN_ENABLE;
1259                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1260                 }
1261                 else if (AR_SREV_9271_11(ah))
1262                         /*
1263                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1264                          * present on AR9271 1.1
1265                          */
1266                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1267                 return;
1268         }
1269
1270         /*
1271          * Set the RX_ABORT and RX_DIS and clear if off only after
1272          * RXE is set for MAC. This prevents frames with corrupted
1273          * descriptor status.
1274          */
1275         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1276
1277         if (AR_SREV_9280_10_OR_LATER(ah)) {
1278                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1279                                (~AR_PCU_MISC_MODE2_HWWAR1);
1280
1281                 if (AR_SREV_9287_10_OR_LATER(ah))
1282                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1283
1284                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1285         }
1286
1287         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1288             AR_SREV_9280_10_OR_LATER(ah))
1289                 return;
1290         /*
1291          * Disable BB clock gating
1292          * Necessary to avoid issues on AR5416 2.0
1293          */
1294         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1295 }
1296
1297 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1298                               struct ar5416_eeprom_def *pEepData,
1299                               u32 reg, u32 value)
1300 {
1301         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1302         struct ath_common *common = ath9k_hw_common(ah);
1303
1304         switch (ah->hw_version.devid) {
1305         case AR9280_DEVID_PCI:
1306                 if (reg == 0x7894) {
1307                         ath_print(common, ATH_DBG_EEPROM,
1308                                 "ini VAL: %x  EEPROM: %x\n", value,
1309                                 (pBase->version & 0xff));
1310
1311                         if ((pBase->version & 0xff) > 0x0a) {
1312                                 ath_print(common, ATH_DBG_EEPROM,
1313                                           "PWDCLKIND: %d\n",
1314                                           pBase->pwdclkind);
1315                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1316                                 value |= AR_AN_TOP2_PWDCLKIND &
1317                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1318                         } else {
1319                                 ath_print(common, ATH_DBG_EEPROM,
1320                                           "PWDCLKIND Earlier Rev\n");
1321                         }
1322
1323                         ath_print(common, ATH_DBG_EEPROM,
1324                                   "final ini VAL: %x\n", value);
1325                 }
1326                 break;
1327         }
1328
1329         return value;
1330 }
1331
1332 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1333                               struct ar5416_eeprom_def *pEepData,
1334                               u32 reg, u32 value)
1335 {
1336         if (ah->eep_map == EEP_MAP_4KBITS)
1337                 return value;
1338         else
1339                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1340 }
1341
1342 static void ath9k_olc_init(struct ath_hw *ah)
1343 {
1344         u32 i;
1345
1346         if (OLC_FOR_AR9287_10_LATER) {
1347                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1348                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1349                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1350                                 AR9287_AN_TXPC0_TXPCMODE,
1351                                 AR9287_AN_TXPC0_TXPCMODE_S,
1352                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1353                 udelay(100);
1354         } else {
1355                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1356                         ah->originalGain[i] =
1357                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1358                                                 AR_PHY_TX_GAIN);
1359                 ah->PDADCdelta = 0;
1360         }
1361 }
1362
1363 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1364                               struct ath9k_channel *chan)
1365 {
1366         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1367
1368         if (IS_CHAN_B(chan))
1369                 ctl |= CTL_11B;
1370         else if (IS_CHAN_G(chan))
1371                 ctl |= CTL_11G;
1372         else
1373                 ctl |= CTL_11A;
1374
1375         return ctl;
1376 }
1377
1378 static int ath9k_hw_process_ini(struct ath_hw *ah,
1379                                 struct ath9k_channel *chan)
1380 {
1381         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1382         int i, regWrites = 0;
1383         struct ieee80211_channel *channel = chan->chan;
1384         u32 modesIndex, freqIndex;
1385
1386         switch (chan->chanmode) {
1387         case CHANNEL_A:
1388         case CHANNEL_A_HT20:
1389                 modesIndex = 1;
1390                 freqIndex = 1;
1391                 break;
1392         case CHANNEL_A_HT40PLUS:
1393         case CHANNEL_A_HT40MINUS:
1394                 modesIndex = 2;
1395                 freqIndex = 1;
1396                 break;
1397         case CHANNEL_G:
1398         case CHANNEL_G_HT20:
1399         case CHANNEL_B:
1400                 modesIndex = 4;
1401                 freqIndex = 2;
1402                 break;
1403         case CHANNEL_G_HT40PLUS:
1404         case CHANNEL_G_HT40MINUS:
1405                 modesIndex = 3;
1406                 freqIndex = 2;
1407                 break;
1408
1409         default:
1410                 return -EINVAL;
1411         }
1412
1413         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1414         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1415         ah->eep_ops->set_addac(ah, chan);
1416
1417         if (AR_SREV_5416_22_OR_LATER(ah)) {
1418                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1419         } else {
1420                 struct ar5416IniArray temp;
1421                 u32 addacSize =
1422                         sizeof(u32) * ah->iniAddac.ia_rows *
1423                         ah->iniAddac.ia_columns;
1424
1425                 memcpy(ah->addac5416_21,
1426                        ah->iniAddac.ia_array, addacSize);
1427
1428                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1429
1430                 temp.ia_array = ah->addac5416_21;
1431                 temp.ia_columns = ah->iniAddac.ia_columns;
1432                 temp.ia_rows = ah->iniAddac.ia_rows;
1433                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1434         }
1435
1436         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1437
1438         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1439                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1440                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1441
1442                 REG_WRITE(ah, reg, val);
1443
1444                 if (reg >= 0x7800 && reg < 0x78a0
1445                     && ah->config.analog_shiftreg) {
1446                         udelay(100);
1447                 }
1448
1449                 DO_DELAY(regWrites);
1450         }
1451
1452         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1453                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1454
1455         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1456             AR_SREV_9287_10_OR_LATER(ah))
1457                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1458
1459         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1460                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1461                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1462
1463                 REG_WRITE(ah, reg, val);
1464
1465                 if (reg >= 0x7800 && reg < 0x78a0
1466                     && ah->config.analog_shiftreg) {
1467                         udelay(100);
1468                 }
1469
1470                 DO_DELAY(regWrites);
1471         }
1472
1473         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1474
1475         if (AR_SREV_9271_10(ah))
1476                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1477                                 modesIndex, regWrites);
1478
1479         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1480                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1481                                 regWrites);
1482         }
1483
1484         ath9k_hw_override_ini(ah, chan);
1485         ath9k_hw_set_regs(ah, chan);
1486         ath9k_hw_init_chain_masks(ah);
1487
1488         if (OLC_FOR_AR9280_20_LATER)
1489                 ath9k_olc_init(ah);
1490
1491         ah->eep_ops->set_txpower(ah, chan,
1492                                  ath9k_regd_get_ctl(regulatory, chan),
1493                                  channel->max_antenna_gain * 2,
1494                                  channel->max_power * 2,
1495                                  min((u32) MAX_RATE_POWER,
1496                                  (u32) regulatory->power_limit));
1497
1498         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1499                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1500                           "ar5416SetRfRegs failed\n");
1501                 return -EIO;
1502         }
1503
1504         return 0;
1505 }
1506
1507 /****************************************/
1508 /* Reset and Channel Switching Routines */
1509 /****************************************/
1510
1511 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1512 {
1513         u32 rfMode = 0;
1514
1515         if (chan == NULL)
1516                 return;
1517
1518         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1519                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1520
1521         if (!AR_SREV_9280_10_OR_LATER(ah))
1522                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1523                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1524
1525         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1526                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1527
1528         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1529 }
1530
1531 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1532 {
1533         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1534 }
1535
1536 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1537 {
1538         u32 regval;
1539
1540         /*
1541          * set AHB_MODE not to do cacheline prefetches
1542         */
1543         regval = REG_READ(ah, AR_AHB_MODE);
1544         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1545
1546         /*
1547          * let mac dma reads be in 128 byte chunks
1548          */
1549         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1550         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1551
1552         /*
1553          * Restore TX Trigger Level to its pre-reset value.
1554          * The initial value depends on whether aggregation is enabled, and is
1555          * adjusted whenever underruns are detected.
1556          */
1557         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1558
1559         /*
1560          * let mac dma writes be in 128 byte chunks
1561          */
1562         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1563         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1564
1565         /*
1566          * Setup receive FIFO threshold to hold off TX activities
1567          */
1568         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1569
1570         /*
1571          * reduce the number of usable entries in PCU TXBUF to avoid
1572          * wrap around issues.
1573          */
1574         if (AR_SREV_9285(ah)) {
1575                 /* For AR9285 the number of Fifos are reduced to half.
1576                  * So set the usable tx buf size also to half to
1577                  * avoid data/delimiter underruns
1578                  */
1579                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1580                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1581         } else if (!AR_SREV_9271(ah)) {
1582                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1583                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1584         }
1585 }
1586
1587 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1588 {
1589         u32 val;
1590
1591         val = REG_READ(ah, AR_STA_ID1);
1592         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1593         switch (opmode) {
1594         case NL80211_IFTYPE_AP:
1595                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1596                           | AR_STA_ID1_KSRCH_MODE);
1597                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1598                 break;
1599         case NL80211_IFTYPE_ADHOC:
1600         case NL80211_IFTYPE_MESH_POINT:
1601                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1602                           | AR_STA_ID1_KSRCH_MODE);
1603                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1604                 break;
1605         case NL80211_IFTYPE_STATION:
1606         case NL80211_IFTYPE_MONITOR:
1607                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1608                 break;
1609         }
1610 }
1611
1612 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1613                                                  u32 coef_scaled,
1614                                                  u32 *coef_mantissa,
1615                                                  u32 *coef_exponent)
1616 {
1617         u32 coef_exp, coef_man;
1618
1619         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1620                 if ((coef_scaled >> coef_exp) & 0x1)
1621                         break;
1622
1623         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1624
1625         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1626
1627         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1628         *coef_exponent = coef_exp - 16;
1629 }
1630
1631 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1632                                      struct ath9k_channel *chan)
1633 {
1634         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1635         u32 clockMhzScaled = 0x64000000;
1636         struct chan_centers centers;
1637
1638         if (IS_CHAN_HALF_RATE(chan))
1639                 clockMhzScaled = clockMhzScaled >> 1;
1640         else if (IS_CHAN_QUARTER_RATE(chan))
1641                 clockMhzScaled = clockMhzScaled >> 2;
1642
1643         ath9k_hw_get_channel_centers(ah, chan, &centers);
1644         coef_scaled = clockMhzScaled / centers.synth_center;
1645
1646         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1647                                       &ds_coef_exp);
1648
1649         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1650                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1651         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1652                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1653
1654         coef_scaled = (9 * coef_scaled) / 10;
1655
1656         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1657                                       &ds_coef_exp);
1658
1659         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1660                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1661         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1662                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1663 }
1664
1665 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1666 {
1667         u32 rst_flags;
1668         u32 tmpReg;
1669
1670         if (AR_SREV_9100(ah)) {
1671                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1672                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1673                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1674                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1675                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1676         }
1677
1678         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1679                   AR_RTC_FORCE_WAKE_ON_INT);
1680
1681         if (AR_SREV_9100(ah)) {
1682                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1683                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1684         } else {
1685                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1686                 if (tmpReg &
1687                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1688                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1689                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1690                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1691                 } else {
1692                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1693                 }
1694
1695                 rst_flags = AR_RTC_RC_MAC_WARM;
1696                 if (type == ATH9K_RESET_COLD)
1697                         rst_flags |= AR_RTC_RC_MAC_COLD;
1698         }
1699
1700         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1701         udelay(50);
1702
1703         REG_WRITE(ah, AR_RTC_RC, 0);
1704         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1705                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1706                           "RTC stuck in MAC reset\n");
1707                 return false;
1708         }
1709
1710         if (!AR_SREV_9100(ah))
1711                 REG_WRITE(ah, AR_RC, 0);
1712
1713         if (AR_SREV_9100(ah))
1714                 udelay(50);
1715
1716         return true;
1717 }
1718
1719 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1720 {
1721         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1722                   AR_RTC_FORCE_WAKE_ON_INT);
1723
1724         if (!AR_SREV_9100(ah))
1725                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1726
1727         REG_WRITE(ah, AR_RTC_RESET, 0);
1728         udelay(2);
1729
1730         if (!AR_SREV_9100(ah))
1731                 REG_WRITE(ah, AR_RC, 0);
1732
1733         REG_WRITE(ah, AR_RTC_RESET, 1);
1734
1735         if (!ath9k_hw_wait(ah,
1736                            AR_RTC_STATUS,
1737                            AR_RTC_STATUS_M,
1738                            AR_RTC_STATUS_ON,
1739                            AH_WAIT_TIMEOUT)) {
1740                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1741                           "RTC not waking up\n");
1742                 return false;
1743         }
1744
1745         ath9k_hw_read_revisions(ah);
1746
1747         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1748 }
1749
1750 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1751 {
1752         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1753                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1754
1755         switch (type) {
1756         case ATH9K_RESET_POWER_ON:
1757                 return ath9k_hw_set_reset_power_on(ah);
1758         case ATH9K_RESET_WARM:
1759         case ATH9K_RESET_COLD:
1760                 return ath9k_hw_set_reset(ah, type);
1761         default:
1762                 return false;
1763         }
1764 }
1765
1766 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1767 {
1768         u32 phymode;
1769         u32 enableDacFifo = 0;
1770
1771         if (AR_SREV_9285_10_OR_LATER(ah))
1772                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1773                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1774
1775         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1776                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1777
1778         if (IS_CHAN_HT40(chan)) {
1779                 phymode |= AR_PHY_FC_DYN2040_EN;
1780
1781                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1782                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1783                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1784
1785         }
1786         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1787
1788         ath9k_hw_set11nmac2040(ah);
1789
1790         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1791         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1792 }
1793
1794 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1795                                 struct ath9k_channel *chan)
1796 {
1797         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1798                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1799                         return false;
1800         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1801                 return false;
1802
1803         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1804                 return false;
1805
1806         ah->chip_fullsleep = false;
1807         ath9k_hw_init_pll(ah, chan);
1808         ath9k_hw_set_rfmode(ah, chan);
1809
1810         return true;
1811 }
1812
1813 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1814                                     struct ath9k_channel *chan)
1815 {
1816         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1817         struct ath_common *common = ath9k_hw_common(ah);
1818         struct ieee80211_channel *channel = chan->chan;
1819         u32 synthDelay, qnum;
1820         int r;
1821
1822         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1823                 if (ath9k_hw_numtxpending(ah, qnum)) {
1824                         ath_print(common, ATH_DBG_QUEUE,
1825                                   "Transmit frames pending on "
1826                                   "queue %d\n", qnum);
1827                         return false;
1828                 }
1829         }
1830
1831         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1832         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1833                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1834                 ath_print(common, ATH_DBG_FATAL,
1835                           "Could not kill baseband RX\n");
1836                 return false;
1837         }
1838
1839         ath9k_hw_set_regs(ah, chan);
1840
1841         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1842         if (r) {
1843                 ath_print(common, ATH_DBG_FATAL,
1844                           "Failed to set channel\n");
1845                 return false;
1846         }
1847
1848         ah->eep_ops->set_txpower(ah, chan,
1849                              ath9k_regd_get_ctl(regulatory, chan),
1850                              channel->max_antenna_gain * 2,
1851                              channel->max_power * 2,
1852                              min((u32) MAX_RATE_POWER,
1853                              (u32) regulatory->power_limit));
1854
1855         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1856         if (IS_CHAN_B(chan))
1857                 synthDelay = (4 * synthDelay) / 22;
1858         else
1859                 synthDelay /= 10;
1860
1861         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1862
1863         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1864
1865         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1866                 ath9k_hw_set_delta_slope(ah, chan);
1867
1868         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1869
1870         if (!chan->oneTimeCalsDone)
1871                 chan->oneTimeCalsDone = true;
1872
1873         return true;
1874 }
1875
1876 static void ath9k_enable_rfkill(struct ath_hw *ah)
1877 {
1878         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1879                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1880
1881         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1882                     AR_GPIO_INPUT_MUX2_RFSILENT);
1883
1884         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1885         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1886 }
1887
1888 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1889                     bool bChannelChange)
1890 {
1891         struct ath_common *common = ath9k_hw_common(ah);
1892         u32 saveLedState;
1893         struct ath9k_channel *curchan = ah->curchan;
1894         u32 saveDefAntenna;
1895         u32 macStaId1;
1896         u64 tsf = 0;
1897         int i, rx_chainmask, r;
1898
1899         ah->txchainmask = common->tx_chainmask;
1900         ah->rxchainmask = common->rx_chainmask;
1901
1902         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1903                 return -EIO;
1904
1905         if (curchan && !ah->chip_fullsleep)
1906                 ath9k_hw_getnf(ah, curchan);
1907
1908         if (bChannelChange &&
1909             (ah->chip_fullsleep != true) &&
1910             (ah->curchan != NULL) &&
1911             (chan->channel != ah->curchan->channel) &&
1912             ((chan->channelFlags & CHANNEL_ALL) ==
1913              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1914              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1915              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1916
1917                 if (ath9k_hw_channel_change(ah, chan)) {
1918                         ath9k_hw_loadnf(ah, ah->curchan);
1919                         ath9k_hw_start_nfcal(ah);
1920                         return 0;
1921                 }
1922         }
1923
1924         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1925         if (saveDefAntenna == 0)
1926                 saveDefAntenna = 1;
1927
1928         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1929
1930         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1931         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1932                 tsf = ath9k_hw_gettsf64(ah);
1933
1934         saveLedState = REG_READ(ah, AR_CFG_LED) &
1935                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1936                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1937
1938         ath9k_hw_mark_phy_inactive(ah);
1939
1940         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1941                 REG_WRITE(ah,
1942                           AR9271_RESET_POWER_DOWN_CONTROL,
1943                           AR9271_RADIO_RF_RST);
1944                 udelay(50);
1945         }
1946
1947         if (!ath9k_hw_chip_reset(ah, chan)) {
1948                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1949                 return -EINVAL;
1950         }
1951
1952         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1953                 ah->htc_reset_init = false;
1954                 REG_WRITE(ah,
1955                           AR9271_RESET_POWER_DOWN_CONTROL,
1956                           AR9271_GATE_MAC_CTL);
1957                 udelay(50);
1958         }
1959
1960         /* Restore TSF */
1961         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1962                 ath9k_hw_settsf64(ah, tsf);
1963
1964         if (AR_SREV_9280_10_OR_LATER(ah))
1965                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1966
1967         if (AR_SREV_9287_12_OR_LATER(ah)) {
1968                 /* Enable ASYNC FIFO */
1969                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1970                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1971                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1972                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1973                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1974                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1975                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1976         }
1977         r = ath9k_hw_process_ini(ah, chan);
1978         if (r)
1979                 return r;
1980
1981         /* Setup MFP options for CCMP */
1982         if (AR_SREV_9280_20_OR_LATER(ah)) {
1983                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1984                  * frames when constructing CCMP AAD. */
1985                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1986                               0xc7ff);
1987                 ah->sw_mgmt_crypto = false;
1988         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1989                 /* Disable hardware crypto for management frames */
1990                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1991                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1992                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1993                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1994                 ah->sw_mgmt_crypto = true;
1995         } else
1996                 ah->sw_mgmt_crypto = true;
1997
1998         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1999                 ath9k_hw_set_delta_slope(ah, chan);
2000
2001         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2002         ah->eep_ops->set_board_values(ah, chan);
2003
2004         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2005         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2006                   | macStaId1
2007                   | AR_STA_ID1_RTS_USE_DEF
2008                   | (ah->config.
2009                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2010                   | ah->sta_id1_defaults);
2011         ath9k_hw_set_operating_mode(ah, ah->opmode);
2012
2013         ath_hw_setbssidmask(common);
2014
2015         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2016
2017         ath9k_hw_write_associd(ah);
2018
2019         REG_WRITE(ah, AR_ISR, ~0);
2020
2021         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2022
2023         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2024         if (r)
2025                 return r;
2026
2027         for (i = 0; i < AR_NUM_DCU; i++)
2028                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2029
2030         ah->intr_txqs = 0;
2031         for (i = 0; i < ah->caps.total_queues; i++)
2032                 ath9k_hw_resettxqueue(ah, i);
2033
2034         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2035         ath9k_hw_init_qos(ah);
2036
2037         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2038                 ath9k_enable_rfkill(ah);
2039
2040         ath9k_hw_init_global_settings(ah);
2041
2042         if (AR_SREV_9287_12_OR_LATER(ah)) {
2043                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2044                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2045                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2046                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2047                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2048                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2049
2050                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2051                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2052
2053                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2054                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2055                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2056                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2057         }
2058         if (AR_SREV_9287_12_OR_LATER(ah)) {
2059                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2060                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2061         }
2062
2063         REG_WRITE(ah, AR_STA_ID1,
2064                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2065
2066         ath9k_hw_set_dma(ah);
2067
2068         REG_WRITE(ah, AR_OBS, 8);
2069
2070         if (ah->config.rx_intr_mitigation) {
2071                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2072                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2073         }
2074
2075         ath9k_hw_init_bb(ah, chan);
2076
2077         if (!ath9k_hw_init_cal(ah, chan))
2078                 return -EIO;
2079
2080         rx_chainmask = ah->rxchainmask;
2081         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2082                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2083                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2084         }
2085
2086         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2087
2088         /*
2089          * For big endian systems turn on swapping for descriptors
2090          */
2091         if (AR_SREV_9100(ah)) {
2092                 u32 mask;
2093                 mask = REG_READ(ah, AR_CFG);
2094                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2095                         ath_print(common, ATH_DBG_RESET,
2096                                 "CFG Byte Swap Set 0x%x\n", mask);
2097                 } else {
2098                         mask =
2099                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2100                         REG_WRITE(ah, AR_CFG, mask);
2101                         ath_print(common, ATH_DBG_RESET,
2102                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2103                 }
2104         } else {
2105                 /* Configure AR9271 target WLAN */
2106                 if (AR_SREV_9271(ah))
2107                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2108 #ifdef __BIG_ENDIAN
2109                 else
2110                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2111 #endif
2112         }
2113
2114         if (ah->btcoex_hw.enabled)
2115                 ath9k_hw_btcoex_enable(ah);
2116
2117         return 0;
2118 }
2119 EXPORT_SYMBOL(ath9k_hw_reset);
2120
2121 /************************/
2122 /* Key Cache Management */
2123 /************************/
2124
2125 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2126 {
2127         u32 keyType;
2128
2129         if (entry >= ah->caps.keycache_size) {
2130                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2131                           "keychache entry %u out of range\n", entry);
2132                 return false;
2133         }
2134
2135         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2136
2137         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2138         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2139         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2140         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2141         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2142         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2143         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2144         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2145
2146         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2147                 u16 micentry = entry + 64;
2148
2149                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2150                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2151                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2152                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2153
2154         }
2155
2156         return true;
2157 }
2158 EXPORT_SYMBOL(ath9k_hw_keyreset);
2159
2160 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2161 {
2162         u32 macHi, macLo;
2163
2164         if (entry >= ah->caps.keycache_size) {
2165                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2166                           "keychache entry %u out of range\n", entry);
2167                 return false;
2168         }
2169
2170         if (mac != NULL) {
2171                 macHi = (mac[5] << 8) | mac[4];
2172                 macLo = (mac[3] << 24) |
2173                         (mac[2] << 16) |
2174                         (mac[1] << 8) |
2175                         mac[0];
2176                 macLo >>= 1;
2177                 macLo |= (macHi & 1) << 31;
2178                 macHi >>= 1;
2179         } else {
2180                 macLo = macHi = 0;
2181         }
2182         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2183         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2184
2185         return true;
2186 }
2187 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2188
2189 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2190                                  const struct ath9k_keyval *k,
2191                                  const u8 *mac)
2192 {
2193         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2194         struct ath_common *common = ath9k_hw_common(ah);
2195         u32 key0, key1, key2, key3, key4;
2196         u32 keyType;
2197
2198         if (entry >= pCap->keycache_size) {
2199                 ath_print(common, ATH_DBG_FATAL,
2200                           "keycache entry %u out of range\n", entry);
2201                 return false;
2202         }
2203
2204         switch (k->kv_type) {
2205         case ATH9K_CIPHER_AES_OCB:
2206                 keyType = AR_KEYTABLE_TYPE_AES;
2207                 break;
2208         case ATH9K_CIPHER_AES_CCM:
2209                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2210                         ath_print(common, ATH_DBG_ANY,
2211                                   "AES-CCM not supported by mac rev 0x%x\n",
2212                                   ah->hw_version.macRev);
2213                         return false;
2214                 }
2215                 keyType = AR_KEYTABLE_TYPE_CCM;
2216                 break;
2217         case ATH9K_CIPHER_TKIP:
2218                 keyType = AR_KEYTABLE_TYPE_TKIP;
2219                 if (ATH9K_IS_MIC_ENABLED(ah)
2220                     && entry + 64 >= pCap->keycache_size) {
2221                         ath_print(common, ATH_DBG_ANY,
2222                                   "entry %u inappropriate for TKIP\n", entry);
2223                         return false;
2224                 }
2225                 break;
2226         case ATH9K_CIPHER_WEP:
2227                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2228                         ath_print(common, ATH_DBG_ANY,
2229                                   "WEP key length %u too small\n", k->kv_len);
2230                         return false;
2231                 }
2232                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2233                         keyType = AR_KEYTABLE_TYPE_40;
2234                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2235                         keyType = AR_KEYTABLE_TYPE_104;
2236                 else
2237                         keyType = AR_KEYTABLE_TYPE_128;
2238                 break;
2239         case ATH9K_CIPHER_CLR:
2240                 keyType = AR_KEYTABLE_TYPE_CLR;
2241                 break;
2242         default:
2243                 ath_print(common, ATH_DBG_FATAL,
2244                           "cipher %u not supported\n", k->kv_type);
2245                 return false;
2246         }
2247
2248         key0 = get_unaligned_le32(k->kv_val + 0);
2249         key1 = get_unaligned_le16(k->kv_val + 4);
2250         key2 = get_unaligned_le32(k->kv_val + 6);
2251         key3 = get_unaligned_le16(k->kv_val + 10);
2252         key4 = get_unaligned_le32(k->kv_val + 12);
2253         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2254                 key4 &= 0xff;
2255
2256         /*
2257          * Note: Key cache registers access special memory area that requires
2258          * two 32-bit writes to actually update the values in the internal
2259          * memory. Consequently, the exact order and pairs used here must be
2260          * maintained.
2261          */
2262
2263         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2264                 u16 micentry = entry + 64;
2265
2266                 /*
2267                  * Write inverted key[47:0] first to avoid Michael MIC errors
2268                  * on frames that could be sent or received at the same time.
2269                  * The correct key will be written in the end once everything
2270                  * else is ready.
2271                  */
2272                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2273                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2274
2275                 /* Write key[95:48] */
2276                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2277                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2278
2279                 /* Write key[127:96] and key type */
2280                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2281                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2282
2283                 /* Write MAC address for the entry */
2284                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2285
2286                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2287                         /*
2288                          * TKIP uses two key cache entries:
2289                          * Michael MIC TX/RX keys in the same key cache entry
2290                          * (idx = main index + 64):
2291                          * key0 [31:0] = RX key [31:0]
2292                          * key1 [15:0] = TX key [31:16]
2293                          * key1 [31:16] = reserved
2294                          * key2 [31:0] = RX key [63:32]
2295                          * key3 [15:0] = TX key [15:0]
2296                          * key3 [31:16] = reserved
2297                          * key4 [31:0] = TX key [63:32]
2298                          */
2299                         u32 mic0, mic1, mic2, mic3, mic4;
2300
2301                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2302                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2303                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2304                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2305                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2306
2307                         /* Write RX[31:0] and TX[31:16] */
2308                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2309                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2310
2311                         /* Write RX[63:32] and TX[15:0] */
2312                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2313                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2314
2315                         /* Write TX[63:32] and keyType(reserved) */
2316                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2317                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2318                                   AR_KEYTABLE_TYPE_CLR);
2319
2320                 } else {
2321                         /*
2322                          * TKIP uses four key cache entries (two for group
2323                          * keys):
2324                          * Michael MIC TX/RX keys are in different key cache
2325                          * entries (idx = main index + 64 for TX and
2326                          * main index + 32 + 96 for RX):
2327                          * key0 [31:0] = TX/RX MIC key [31:0]
2328                          * key1 [31:0] = reserved
2329                          * key2 [31:0] = TX/RX MIC key [63:32]
2330                          * key3 [31:0] = reserved
2331                          * key4 [31:0] = reserved
2332                          *
2333                          * Upper layer code will call this function separately
2334                          * for TX and RX keys when these registers offsets are
2335                          * used.
2336                          */
2337                         u32 mic0, mic2;
2338
2339                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2340                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2341
2342                         /* Write MIC key[31:0] */
2343                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2344                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2345
2346                         /* Write MIC key[63:32] */
2347                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2348                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2349
2350                         /* Write TX[63:32] and keyType(reserved) */
2351                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2352                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2353                                   AR_KEYTABLE_TYPE_CLR);
2354                 }
2355
2356                 /* MAC address registers are reserved for the MIC entry */
2357                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2358                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2359
2360                 /*
2361                  * Write the correct (un-inverted) key[47:0] last to enable
2362                  * TKIP now that all other registers are set with correct
2363                  * values.
2364                  */
2365                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2366                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2367         } else {
2368                 /* Write key[47:0] */
2369                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2370                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2371
2372                 /* Write key[95:48] */
2373                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2374                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2375
2376                 /* Write key[127:96] and key type */
2377                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2378                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2379
2380                 /* Write MAC address for the entry */
2381                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2382         }
2383
2384         return true;
2385 }
2386 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2387
2388 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2389 {
2390         if (entry < ah->caps.keycache_size) {
2391                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2392                 if (val & AR_KEYTABLE_VALID)
2393                         return true;
2394         }
2395         return false;
2396 }
2397 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2398
2399 /******************************/
2400 /* Power Management (Chipset) */
2401 /******************************/
2402
2403 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2404 {
2405         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2406         if (setChip) {
2407                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2408                             AR_RTC_FORCE_WAKE_EN);
2409                 if (!AR_SREV_9100(ah))
2410                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2411
2412                 if(!AR_SREV_5416(ah))
2413                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2414                                     AR_RTC_RESET_EN);
2415         }
2416 }
2417
2418 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2419 {
2420         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2421         if (setChip) {
2422                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2423
2424                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2425                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2426                                   AR_RTC_FORCE_WAKE_ON_INT);
2427                 } else {
2428                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2429                                     AR_RTC_FORCE_WAKE_EN);
2430                 }
2431         }
2432 }
2433
2434 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2435 {
2436         u32 val;
2437         int i;
2438
2439         if (setChip) {
2440                 if ((REG_READ(ah, AR_RTC_STATUS) &
2441                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2442                         if (ath9k_hw_set_reset_reg(ah,
2443                                            ATH9K_RESET_POWER_ON) != true) {
2444                                 return false;
2445                         }
2446                         ath9k_hw_init_pll(ah, NULL);
2447                 }
2448                 if (AR_SREV_9100(ah))
2449                         REG_SET_BIT(ah, AR_RTC_RESET,
2450                                     AR_RTC_RESET_EN);
2451
2452                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2453                             AR_RTC_FORCE_WAKE_EN);
2454                 udelay(50);
2455
2456                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2457                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2458                         if (val == AR_RTC_STATUS_ON)
2459                                 break;
2460                         udelay(50);
2461                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2462                                     AR_RTC_FORCE_WAKE_EN);
2463                 }
2464                 if (i == 0) {
2465                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2466                                   "Failed to wakeup in %uus\n",
2467                                   POWER_UP_TIME / 20);
2468                         return false;
2469                 }
2470         }
2471
2472         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2473
2474         return true;
2475 }
2476
2477 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2478 {
2479         struct ath_common *common = ath9k_hw_common(ah);
2480         int status = true, setChip = true;
2481         static const char *modes[] = {
2482                 "AWAKE",
2483                 "FULL-SLEEP",
2484                 "NETWORK SLEEP",
2485                 "UNDEFINED"
2486         };
2487
2488         if (ah->power_mode == mode)
2489                 return status;
2490
2491         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2492                   modes[ah->power_mode], modes[mode]);
2493
2494         switch (mode) {
2495         case ATH9K_PM_AWAKE:
2496                 status = ath9k_hw_set_power_awake(ah, setChip);
2497                 break;
2498         case ATH9K_PM_FULL_SLEEP:
2499                 ath9k_set_power_sleep(ah, setChip);
2500                 ah->chip_fullsleep = true;
2501                 break;
2502         case ATH9K_PM_NETWORK_SLEEP:
2503                 ath9k_set_power_network_sleep(ah, setChip);
2504                 break;
2505         default:
2506                 ath_print(common, ATH_DBG_FATAL,
2507                           "Unknown power mode %u\n", mode);
2508                 return false;
2509         }
2510         ah->power_mode = mode;
2511
2512         return status;
2513 }
2514 EXPORT_SYMBOL(ath9k_hw_setpower);
2515
2516 /*
2517  * Helper for ASPM support.
2518  *
2519  * Disable PLL when in L0s as well as receiver clock when in L1.
2520  * This power saving option must be enabled through the SerDes.
2521  *
2522  * Programming the SerDes must go through the same 288 bit serial shift
2523  * register as the other analog registers.  Hence the 9 writes.
2524  */
2525 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2526 {
2527         u8 i;
2528         u32 val;
2529
2530         if (ah->is_pciexpress != true)
2531                 return;
2532
2533         /* Do not touch SerDes registers */
2534         if (ah->config.pcie_powersave_enable == 2)
2535                 return;
2536
2537         /* Nothing to do on restore for 11N */
2538         if (!restore) {
2539                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2540                         /*
2541                          * AR9280 2.0 or later chips use SerDes values from the
2542                          * initvals.h initialized depending on chipset during
2543                          * ath9k_hw_init()
2544                          */
2545                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2546                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2547                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2548                         }
2549                 } else if (AR_SREV_9280(ah) &&
2550                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2551                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2552                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2553
2554                         /* RX shut off when elecidle is asserted */
2555                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2556                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2557                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2558
2559                         /* Shut off CLKREQ active in L1 */
2560                         if (ah->config.pcie_clock_req)
2561                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2562                         else
2563                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2564
2565                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2566                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2567                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2568
2569                         /* Load the new settings */
2570                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2571
2572                 } else {
2573                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2574                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2575
2576                         /* RX shut off when elecidle is asserted */
2577                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2578                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2579                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2580
2581                         /*
2582                          * Ignore ah->ah_config.pcie_clock_req setting for
2583                          * pre-AR9280 11n
2584                          */
2585                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2586
2587                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2588                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2589                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2590
2591                         /* Load the new settings */
2592                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2593                 }
2594
2595                 udelay(1000);
2596
2597                 /* set bit 19 to allow forcing of pcie core into L1 state */
2598                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2599
2600                 /* Several PCIe massages to ensure proper behaviour */
2601                 if (ah->config.pcie_waen) {
2602                         val = ah->config.pcie_waen;
2603                         if (!power_off)
2604                                 val &= (~AR_WA_D3_L1_DISABLE);
2605                 } else {
2606                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2607                             AR_SREV_9287(ah)) {
2608                                 val = AR9285_WA_DEFAULT;
2609                                 if (!power_off)
2610                                         val &= (~AR_WA_D3_L1_DISABLE);
2611                         } else if (AR_SREV_9280(ah)) {
2612                                 /*
2613                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2614                                  * set otherwise card may disappear.
2615                                  */
2616                                 val = AR9280_WA_DEFAULT;
2617                                 if (!power_off)
2618                                         val &= (~AR_WA_D3_L1_DISABLE);
2619                         } else
2620                                 val = AR_WA_DEFAULT;
2621                 }
2622
2623                 REG_WRITE(ah, AR_WA, val);
2624         }
2625
2626         if (power_off) {
2627                 /*
2628                  * Set PCIe workaround bits
2629                  * bit 14 in WA register (disable L1) should only
2630                  * be set when device enters D3 and be cleared
2631                  * when device comes back to D0.
2632                  */
2633                 if (ah->config.pcie_waen) {
2634                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2635                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2636                 } else {
2637                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2638                               AR_SREV_9287(ah)) &&
2639                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2640                             (AR_SREV_9280(ah) &&
2641                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2642                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2643                         }
2644                 }
2645         }
2646 }
2647 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2648
2649 /**********************/
2650 /* Interrupt Handling */
2651 /**********************/
2652
2653 bool ath9k_hw_intrpend(struct ath_hw *ah)
2654 {
2655         u32 host_isr;
2656
2657         if (AR_SREV_9100(ah))
2658                 return true;
2659
2660         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2661         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2662                 return true;
2663
2664         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2665         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2666             && (host_isr != AR_INTR_SPURIOUS))
2667                 return true;
2668
2669         return false;
2670 }
2671 EXPORT_SYMBOL(ath9k_hw_intrpend);
2672
2673 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2674 {
2675         u32 isr = 0;
2676         u32 mask2 = 0;
2677         struct ath9k_hw_capabilities *pCap = &ah->caps;
2678         u32 sync_cause = 0;
2679         bool fatal_int = false;
2680         struct ath_common *common = ath9k_hw_common(ah);
2681
2682         if (!AR_SREV_9100(ah)) {
2683                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2684                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2685                             == AR_RTC_STATUS_ON) {
2686                                 isr = REG_READ(ah, AR_ISR);
2687                         }
2688                 }
2689
2690                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2691                         AR_INTR_SYNC_DEFAULT;
2692
2693                 *masked = 0;
2694
2695                 if (!isr && !sync_cause)
2696                         return false;
2697         } else {
2698                 *masked = 0;
2699                 isr = REG_READ(ah, AR_ISR);
2700         }
2701
2702         if (isr) {
2703                 if (isr & AR_ISR_BCNMISC) {
2704                         u32 isr2;
2705                         isr2 = REG_READ(ah, AR_ISR_S2);
2706                         if (isr2 & AR_ISR_S2_TIM)
2707                                 mask2 |= ATH9K_INT_TIM;
2708                         if (isr2 & AR_ISR_S2_DTIM)
2709                                 mask2 |= ATH9K_INT_DTIM;
2710                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2711                                 mask2 |= ATH9K_INT_DTIMSYNC;
2712                         if (isr2 & (AR_ISR_S2_CABEND))
2713                                 mask2 |= ATH9K_INT_CABEND;
2714                         if (isr2 & AR_ISR_S2_GTT)
2715                                 mask2 |= ATH9K_INT_GTT;
2716                         if (isr2 & AR_ISR_S2_CST)
2717                                 mask2 |= ATH9K_INT_CST;
2718                         if (isr2 & AR_ISR_S2_TSFOOR)
2719                                 mask2 |= ATH9K_INT_TSFOOR;
2720                 }
2721
2722                 isr = REG_READ(ah, AR_ISR_RAC);
2723                 if (isr == 0xffffffff) {
2724                         *masked = 0;
2725                         return false;
2726                 }
2727
2728                 *masked = isr & ATH9K_INT_COMMON;
2729
2730                 if (ah->config.rx_intr_mitigation) {
2731                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2732                                 *masked |= ATH9K_INT_RX;
2733                 }
2734
2735                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2736                         *masked |= ATH9K_INT_RX;
2737                 if (isr &
2738                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2739                      AR_ISR_TXEOL)) {
2740                         u32 s0_s, s1_s;
2741
2742                         *masked |= ATH9K_INT_TX;
2743
2744                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2745                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2746                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2747
2748                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2749                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2750                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2751                 }
2752
2753                 if (isr & AR_ISR_RXORN) {
2754                         ath_print(common, ATH_DBG_INTERRUPT,
2755                                   "receive FIFO overrun interrupt\n");
2756                 }
2757
2758                 if (!AR_SREV_9100(ah)) {
2759                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2760                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2761                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2762                                         *masked |= ATH9K_INT_TIM_TIMER;
2763                         }
2764                 }
2765
2766                 *masked |= mask2;
2767         }
2768
2769         if (AR_SREV_9100(ah))
2770                 return true;
2771
2772         if (isr & AR_ISR_GENTMR) {
2773                 u32 s5_s;
2774
2775                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2776                 if (isr & AR_ISR_GENTMR) {
2777                         ah->intr_gen_timer_trigger =
2778                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2779
2780                         ah->intr_gen_timer_thresh =
2781                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2782
2783                         if (ah->intr_gen_timer_trigger)
2784                                 *masked |= ATH9K_INT_GENTIMER;
2785
2786                 }
2787         }
2788
2789         if (sync_cause) {
2790                 fatal_int =
2791                         (sync_cause &
2792                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2793                         ? true : false;
2794
2795                 if (fatal_int) {
2796                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2797                                 ath_print(common, ATH_DBG_ANY,
2798                                           "received PCI FATAL interrupt\n");
2799                         }
2800                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2801                                 ath_print(common, ATH_DBG_ANY,
2802                                           "received PCI PERR interrupt\n");
2803                         }
2804                         *masked |= ATH9K_INT_FATAL;
2805                 }
2806                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2807                         ath_print(common, ATH_DBG_INTERRUPT,
2808                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2809                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2810                         REG_WRITE(ah, AR_RC, 0);
2811                         *masked |= ATH9K_INT_FATAL;
2812                 }
2813                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2814                         ath_print(common, ATH_DBG_INTERRUPT,
2815                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2816                 }
2817
2818                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2819                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2820         }
2821
2822         return true;
2823 }
2824 EXPORT_SYMBOL(ath9k_hw_getisr);
2825
2826 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2827 {
2828         u32 omask = ah->mask_reg;
2829         u32 mask, mask2;
2830         struct ath9k_hw_capabilities *pCap = &ah->caps;
2831         struct ath_common *common = ath9k_hw_common(ah);
2832
2833         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2834
2835         if (omask & ATH9K_INT_GLOBAL) {
2836                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2837                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2838                 (void) REG_READ(ah, AR_IER);
2839                 if (!AR_SREV_9100(ah)) {
2840                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2841                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2842
2843                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2844                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2845                 }
2846         }
2847
2848         mask = ints & ATH9K_INT_COMMON;
2849         mask2 = 0;
2850
2851         if (ints & ATH9K_INT_TX) {
2852                 if (ah->txok_interrupt_mask)
2853                         mask |= AR_IMR_TXOK;
2854                 if (ah->txdesc_interrupt_mask)
2855                         mask |= AR_IMR_TXDESC;
2856                 if (ah->txerr_interrupt_mask)
2857                         mask |= AR_IMR_TXERR;
2858                 if (ah->txeol_interrupt_mask)
2859                         mask |= AR_IMR_TXEOL;
2860         }
2861         if (ints & ATH9K_INT_RX) {
2862                 mask |= AR_IMR_RXERR;
2863                 if (ah->config.rx_intr_mitigation)
2864                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2865                 else
2866                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2867                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2868                         mask |= AR_IMR_GENTMR;
2869         }
2870
2871         if (ints & (ATH9K_INT_BMISC)) {
2872                 mask |= AR_IMR_BCNMISC;
2873                 if (ints & ATH9K_INT_TIM)
2874                         mask2 |= AR_IMR_S2_TIM;
2875                 if (ints & ATH9K_INT_DTIM)
2876                         mask2 |= AR_IMR_S2_DTIM;
2877                 if (ints & ATH9K_INT_DTIMSYNC)
2878                         mask2 |= AR_IMR_S2_DTIMSYNC;
2879                 if (ints & ATH9K_INT_CABEND)
2880                         mask2 |= AR_IMR_S2_CABEND;
2881                 if (ints & ATH9K_INT_TSFOOR)
2882                         mask2 |= AR_IMR_S2_TSFOOR;
2883         }
2884
2885         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2886                 mask |= AR_IMR_BCNMISC;
2887                 if (ints & ATH9K_INT_GTT)
2888                         mask2 |= AR_IMR_S2_GTT;
2889                 if (ints & ATH9K_INT_CST)
2890                         mask2 |= AR_IMR_S2_CST;
2891         }
2892
2893         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2894         REG_WRITE(ah, AR_IMR, mask);
2895         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2896                                            AR_IMR_S2_DTIM |
2897                                            AR_IMR_S2_DTIMSYNC |
2898                                            AR_IMR_S2_CABEND |
2899                                            AR_IMR_S2_CABTO |
2900                                            AR_IMR_S2_TSFOOR |
2901                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2902         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2903         ah->mask_reg = ints;
2904
2905         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2906                 if (ints & ATH9K_INT_TIM_TIMER)
2907                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2908                 else
2909                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2910         }
2911
2912         if (ints & ATH9K_INT_GLOBAL) {
2913                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2914                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2915                 if (!AR_SREV_9100(ah)) {
2916                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2917                                   AR_INTR_MAC_IRQ);
2918                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2919
2920
2921                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2922                                   AR_INTR_SYNC_DEFAULT);
2923                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2924                                   AR_INTR_SYNC_DEFAULT);
2925                 }
2926                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2927                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2928         }
2929
2930         return omask;
2931 }
2932 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2933
2934 /*******************/
2935 /* Beacon Handling */
2936 /*******************/
2937
2938 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2939 {
2940         int flags = 0;
2941
2942         ah->beacon_interval = beacon_period;
2943
2944         switch (ah->opmode) {
2945         case NL80211_IFTYPE_STATION:
2946         case NL80211_IFTYPE_MONITOR:
2947                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2948                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2949                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2950                 flags |= AR_TBTT_TIMER_EN;
2951                 break;
2952         case NL80211_IFTYPE_ADHOC:
2953         case NL80211_IFTYPE_MESH_POINT:
2954                 REG_SET_BIT(ah, AR_TXCFG,
2955                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2956                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2957                           TU_TO_USEC(next_beacon +
2958                                      (ah->atim_window ? ah->
2959                                       atim_window : 1)));
2960                 flags |= AR_NDP_TIMER_EN;
2961         case NL80211_IFTYPE_AP:
2962                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2963                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2964                           TU_TO_USEC(next_beacon -
2965                                      ah->config.
2966                                      dma_beacon_response_time));
2967                 REG_WRITE(ah, AR_NEXT_SWBA,
2968                           TU_TO_USEC(next_beacon -
2969                                      ah->config.
2970                                      sw_beacon_response_time));
2971                 flags |=
2972                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2973                 break;
2974         default:
2975                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2976                           "%s: unsupported opmode: %d\n",
2977                           __func__, ah->opmode);
2978                 return;
2979                 break;
2980         }
2981
2982         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2983         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2984         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2985         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2986
2987         beacon_period &= ~ATH9K_BEACON_ENA;
2988         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2989                 ath9k_hw_reset_tsf(ah);
2990         }
2991
2992         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2993 }
2994 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2995
2996 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2997                                     const struct ath9k_beacon_state *bs)
2998 {
2999         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3000         struct ath9k_hw_capabilities *pCap = &ah->caps;
3001         struct ath_common *common = ath9k_hw_common(ah);
3002
3003         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3004
3005         REG_WRITE(ah, AR_BEACON_PERIOD,
3006                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3007         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3008                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3009
3010         REG_RMW_FIELD(ah, AR_RSSI_THR,
3011                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3012
3013         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3014
3015         if (bs->bs_sleepduration > beaconintval)
3016                 beaconintval = bs->bs_sleepduration;
3017
3018         dtimperiod = bs->bs_dtimperiod;
3019         if (bs->bs_sleepduration > dtimperiod)
3020                 dtimperiod = bs->bs_sleepduration;
3021
3022         if (beaconintval == dtimperiod)
3023                 nextTbtt = bs->bs_nextdtim;
3024         else
3025                 nextTbtt = bs->bs_nexttbtt;
3026
3027         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3028         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3029         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3030         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3031
3032         REG_WRITE(ah, AR_NEXT_DTIM,
3033                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3034         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3035
3036         REG_WRITE(ah, AR_SLEEP1,
3037                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3038                   | AR_SLEEP1_ASSUME_DTIM);
3039
3040         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3041                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3042         else
3043                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3044
3045         REG_WRITE(ah, AR_SLEEP2,
3046                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3047
3048         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3049         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3050
3051         REG_SET_BIT(ah, AR_TIMER_MODE,
3052                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3053                     AR_DTIM_TIMER_EN);
3054
3055         /* TSF Out of Range Threshold */
3056         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3057 }
3058 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3059
3060 /*******************/
3061 /* HW Capabilities */
3062 /*******************/
3063
3064 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3065 {
3066         struct ath9k_hw_capabilities *pCap = &ah->caps;
3067         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3068         struct ath_common *common = ath9k_hw_common(ah);
3069         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3070
3071         u16 capField = 0, eeval;
3072
3073         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3074         regulatory->current_rd = eeval;
3075
3076         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3077         if (AR_SREV_9285_10_OR_LATER(ah))
3078                 eeval |= AR9285_RDEXT_DEFAULT;
3079         regulatory->current_rd_ext = eeval;
3080
3081         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3082
3083         if (ah->opmode != NL80211_IFTYPE_AP &&
3084             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3085                 if (regulatory->current_rd == 0x64 ||
3086                     regulatory->current_rd == 0x65)
3087                         regulatory->current_rd += 5;
3088                 else if (regulatory->current_rd == 0x41)
3089                         regulatory->current_rd = 0x43;
3090                 ath_print(common, ATH_DBG_REGULATORY,
3091                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3092         }
3093
3094         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3095         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3096                 ath_print(common, ATH_DBG_FATAL,
3097                           "no band has been marked as supported in EEPROM.\n");
3098                 return -EINVAL;
3099         }
3100
3101         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3102
3103         if (eeval & AR5416_OPFLAGS_11A) {
3104                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3105                 if (ah->config.ht_enable) {
3106                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3107                                 set_bit(ATH9K_MODE_11NA_HT20,
3108                                         pCap->wireless_modes);
3109                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3110                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3111                                         pCap->wireless_modes);
3112                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3113                                         pCap->wireless_modes);
3114                         }
3115                 }
3116         }
3117
3118         if (eeval & AR5416_OPFLAGS_11G) {
3119                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3120                 if (ah->config.ht_enable) {
3121                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3122                                 set_bit(ATH9K_MODE_11NG_HT20,
3123                                         pCap->wireless_modes);
3124                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3125                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3126                                         pCap->wireless_modes);
3127                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3128                                         pCap->wireless_modes);
3129                         }
3130                 }
3131         }
3132
3133         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3134         /*
3135          * For AR9271 we will temporarilly uses the rx chainmax as read from
3136          * the EEPROM.
3137          */
3138         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3139             !(eeval & AR5416_OPFLAGS_11A) &&
3140             !(AR_SREV_9271(ah)))
3141                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3142                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3143         else
3144                 /* Use rx_chainmask from EEPROM. */
3145                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3146
3147         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3148                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3149
3150         pCap->low_2ghz_chan = 2312;
3151         pCap->high_2ghz_chan = 2732;
3152
3153         pCap->low_5ghz_chan = 4920;
3154         pCap->high_5ghz_chan = 6100;
3155
3156         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3157         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3158         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3159
3160         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3161         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3162         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3163
3164         if (ah->config.ht_enable)
3165                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3166         else
3167                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3168
3169         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3170         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3171         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3172         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3173
3174         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3175                 pCap->total_queues =
3176                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3177         else
3178                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3179
3180         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3181                 pCap->keycache_size =
3182                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3183         else
3184                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3185
3186         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3187
3188         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3189                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3190         else
3191                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3192
3193         if (AR_SREV_9285_10_OR_LATER(ah))
3194                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3195         else if (AR_SREV_9280_10_OR_LATER(ah))
3196                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3197         else
3198                 pCap->num_gpio_pins = AR_NUM_GPIO;
3199
3200         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3201                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3202                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3203         } else {
3204                 pCap->rts_aggr_limit = (8 * 1024);
3205         }
3206
3207         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3208
3209 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3210         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3211         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3212                 ah->rfkill_gpio =
3213                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3214                 ah->rfkill_polarity =
3215                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3216
3217                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3218         }
3219 #endif
3220
3221         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3222
3223         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3224                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3225         else
3226                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3227
3228         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3229                 pCap->reg_cap =
3230                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3231                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3232                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3233                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3234         } else {
3235                 pCap->reg_cap =
3236                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3237                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3238         }
3239
3240         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3241         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3242             AR_SREV_5416(ah))
3243                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3244
3245         pCap->num_antcfg_5ghz =
3246                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3247         pCap->num_antcfg_2ghz =
3248                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3249
3250         if (AR_SREV_9280_10_OR_LATER(ah) &&
3251             ath9k_hw_btcoex_supported(ah)) {
3252                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3253                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3254
3255                 if (AR_SREV_9285(ah)) {
3256                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3257                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3258                 } else {
3259                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3260                 }
3261         } else {
3262                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3263         }
3264
3265         return 0;
3266 }
3267
3268 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3269                             u32 capability, u32 *result)
3270 {
3271         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3272         switch (type) {
3273         case ATH9K_CAP_CIPHER:
3274                 switch (capability) {
3275                 case ATH9K_CIPHER_AES_CCM:
3276                 case ATH9K_CIPHER_AES_OCB:
3277                 case ATH9K_CIPHER_TKIP:
3278                 case ATH9K_CIPHER_WEP:
3279                 case ATH9K_CIPHER_MIC:
3280                 case ATH9K_CIPHER_CLR:
3281                         return true;
3282                 default:
3283                         return false;
3284                 }
3285         case ATH9K_CAP_TKIP_MIC:
3286                 switch (capability) {
3287                 case 0:
3288                         return true;
3289                 case 1:
3290                         return (ah->sta_id1_defaults &
3291                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3292                         false;
3293                 }
3294         case ATH9K_CAP_TKIP_SPLIT:
3295                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3296                         false : true;
3297         case ATH9K_CAP_DIVERSITY:
3298                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3299                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3300                         true : false;
3301         case ATH9K_CAP_MCAST_KEYSRCH:
3302                 switch (capability) {
3303                 case 0:
3304                         return true;
3305                 case 1:
3306                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3307                                 return false;
3308                         } else {
3309                                 return (ah->sta_id1_defaults &
3310                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3311                                         false;
3312                         }
3313                 }
3314                 return false;
3315         case ATH9K_CAP_TXPOW:
3316                 switch (capability) {
3317                 case 0:
3318                         return 0;
3319                 case 1:
3320                         *result = regulatory->power_limit;
3321                         return 0;
3322                 case 2:
3323                         *result = regulatory->max_power_level;
3324                         return 0;
3325                 case 3:
3326                         *result = regulatory->tp_scale;
3327                         return 0;
3328                 }
3329                 return false;
3330         case ATH9K_CAP_DS:
3331                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3332                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3333                         ? false : true;
3334         default:
3335                 return false;
3336         }
3337 }
3338 EXPORT_SYMBOL(ath9k_hw_getcapability);
3339
3340 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3341                             u32 capability, u32 setting, int *status)
3342 {
3343         u32 v;
3344
3345         switch (type) {
3346         case ATH9K_CAP_TKIP_MIC:
3347                 if (setting)
3348                         ah->sta_id1_defaults |=
3349                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3350                 else
3351                         ah->sta_id1_defaults &=
3352                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3353                 return true;
3354         case ATH9K_CAP_DIVERSITY:
3355                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3356                 if (setting)
3357                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3358                 else
3359                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3360                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3361                 return true;
3362         case ATH9K_CAP_MCAST_KEYSRCH:
3363                 if (setting)
3364                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3365                 else
3366                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3367                 return true;
3368         default:
3369                 return false;
3370         }
3371 }
3372 EXPORT_SYMBOL(ath9k_hw_setcapability);
3373
3374 /****************************/
3375 /* GPIO / RFKILL / Antennae */
3376 /****************************/
3377
3378 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3379                                          u32 gpio, u32 type)
3380 {
3381         int addr;
3382         u32 gpio_shift, tmp;
3383
3384         if (gpio > 11)
3385                 addr = AR_GPIO_OUTPUT_MUX3;
3386         else if (gpio > 5)
3387                 addr = AR_GPIO_OUTPUT_MUX2;
3388         else
3389                 addr = AR_GPIO_OUTPUT_MUX1;
3390
3391         gpio_shift = (gpio % 6) * 5;
3392
3393         if (AR_SREV_9280_20_OR_LATER(ah)
3394             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3395                 REG_RMW(ah, addr, (type << gpio_shift),
3396                         (0x1f << gpio_shift));
3397         } else {
3398                 tmp = REG_READ(ah, addr);
3399                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3400                 tmp &= ~(0x1f << gpio_shift);
3401                 tmp |= (type << gpio_shift);
3402                 REG_WRITE(ah, addr, tmp);
3403         }
3404 }
3405
3406 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3407 {
3408         u32 gpio_shift;
3409
3410         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3411
3412         gpio_shift = gpio << 1;
3413
3414         REG_RMW(ah,
3415                 AR_GPIO_OE_OUT,
3416                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3417                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3418 }
3419 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3420
3421 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3422 {
3423 #define MS_REG_READ(x, y) \
3424         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3425
3426         if (gpio >= ah->caps.num_gpio_pins)
3427                 return 0xffffffff;
3428
3429         if (AR_SREV_9287_10_OR_LATER(ah))
3430                 return MS_REG_READ(AR9287, gpio) != 0;
3431         else if (AR_SREV_9285_10_OR_LATER(ah))
3432                 return MS_REG_READ(AR9285, gpio) != 0;
3433         else if (AR_SREV_9280_10_OR_LATER(ah))
3434                 return MS_REG_READ(AR928X, gpio) != 0;
3435         else
3436                 return MS_REG_READ(AR, gpio) != 0;
3437 }
3438 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3439
3440 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3441                          u32 ah_signal_type)
3442 {
3443         u32 gpio_shift;
3444
3445         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3446
3447         gpio_shift = 2 * gpio;
3448
3449         REG_RMW(ah,
3450                 AR_GPIO_OE_OUT,
3451                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3452                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3453 }
3454 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3455
3456 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3457 {
3458         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3459                 AR_GPIO_BIT(gpio));
3460 }
3461 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3462
3463 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3464 {
3465         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3466 }
3467 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3468
3469 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3470 {
3471         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3472 }
3473 EXPORT_SYMBOL(ath9k_hw_setantenna);
3474
3475 /*********************/
3476 /* General Operation */
3477 /*********************/
3478
3479 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3480 {
3481         u32 bits = REG_READ(ah, AR_RX_FILTER);
3482         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3483
3484         if (phybits & AR_PHY_ERR_RADAR)
3485                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3486         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3487                 bits |= ATH9K_RX_FILTER_PHYERR;
3488
3489         return bits;
3490 }
3491 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3492
3493 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3494 {
3495         u32 phybits;
3496
3497         REG_WRITE(ah, AR_RX_FILTER, bits);
3498
3499         phybits = 0;
3500         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3501                 phybits |= AR_PHY_ERR_RADAR;
3502         if (bits & ATH9K_RX_FILTER_PHYERR)
3503                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3504         REG_WRITE(ah, AR_PHY_ERR, phybits);
3505
3506         if (phybits)
3507                 REG_WRITE(ah, AR_RXCFG,
3508                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3509         else
3510                 REG_WRITE(ah, AR_RXCFG,
3511                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3512 }
3513 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3514
3515 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3516 {
3517         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3518                 return false;
3519
3520         ath9k_hw_init_pll(ah, NULL);
3521         return true;
3522 }
3523 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3524
3525 bool ath9k_hw_disable(struct ath_hw *ah)
3526 {
3527         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3528                 return false;
3529
3530         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3531                 return false;
3532
3533         ath9k_hw_init_pll(ah, NULL);
3534         return true;
3535 }
3536 EXPORT_SYMBOL(ath9k_hw_disable);
3537
3538 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3539 {
3540         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3541         struct ath9k_channel *chan = ah->curchan;
3542         struct ieee80211_channel *channel = chan->chan;
3543
3544         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3545
3546         ah->eep_ops->set_txpower(ah, chan,
3547                                  ath9k_regd_get_ctl(regulatory, chan),
3548                                  channel->max_antenna_gain * 2,
3549                                  channel->max_power * 2,
3550                                  min((u32) MAX_RATE_POWER,
3551                                  (u32) regulatory->power_limit));
3552 }
3553 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3554
3555 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3556 {
3557         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3558 }
3559 EXPORT_SYMBOL(ath9k_hw_setmac);
3560
3561 void ath9k_hw_setopmode(struct ath_hw *ah)
3562 {
3563         ath9k_hw_set_operating_mode(ah, ah->opmode);
3564 }
3565 EXPORT_SYMBOL(ath9k_hw_setopmode);
3566
3567 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3568 {
3569         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3570         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3571 }
3572 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3573
3574 void ath9k_hw_write_associd(struct ath_hw *ah)
3575 {
3576         struct ath_common *common = ath9k_hw_common(ah);
3577
3578         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3579         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3580                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3581 }
3582 EXPORT_SYMBOL(ath9k_hw_write_associd);
3583
3584 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3585 {
3586         u64 tsf;
3587
3588         tsf = REG_READ(ah, AR_TSF_U32);
3589         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3590
3591         return tsf;
3592 }
3593 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3594
3595 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3596 {
3597         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3598         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3599 }
3600 EXPORT_SYMBOL(ath9k_hw_settsf64);
3601
3602 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3603 {
3604         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3605                            AH_TSF_WRITE_TIMEOUT))
3606                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3607                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3608
3609         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3610 }
3611 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3612
3613 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3614 {
3615         if (setting)
3616                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3617         else
3618                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3619 }
3620 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3621
3622 /*
3623  *  Extend 15-bit time stamp from rx descriptor to
3624  *  a full 64-bit TSF using the current h/w TSF.
3625 */
3626 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3627 {
3628         u64 tsf;
3629
3630         tsf = ath9k_hw_gettsf64(ah);
3631         if ((tsf & 0x7fff) < rstamp)
3632                 tsf -= 0x8000;
3633         return (tsf & ~0x7fff) | rstamp;
3634 }
3635 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3636
3637 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3638 {
3639         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3640         u32 macmode;
3641
3642         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3643                 macmode = AR_2040_JOINED_RX_CLEAR;
3644         else
3645                 macmode = 0;
3646
3647         REG_WRITE(ah, AR_2040_MODE, macmode);
3648 }
3649
3650 /* HW Generic timers configuration */
3651
3652 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3653 {
3654         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3655         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3656         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3657         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3658         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3659         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3660         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3661         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3662         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3663         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3664                                 AR_NDP2_TIMER_MODE, 0x0002},
3665         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3666                                 AR_NDP2_TIMER_MODE, 0x0004},
3667         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3668                                 AR_NDP2_TIMER_MODE, 0x0008},
3669         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3670                                 AR_NDP2_TIMER_MODE, 0x0010},
3671         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3672                                 AR_NDP2_TIMER_MODE, 0x0020},
3673         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3674                                 AR_NDP2_TIMER_MODE, 0x0040},
3675         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3676                                 AR_NDP2_TIMER_MODE, 0x0080}
3677 };
3678
3679 /* HW generic timer primitives */
3680
3681 /* compute and clear index of rightmost 1 */
3682 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3683 {
3684         u32 b;
3685
3686         b = *mask;
3687         b &= (0-b);
3688         *mask &= ~b;
3689         b *= debruijn32;
3690         b >>= 27;
3691
3692         return timer_table->gen_timer_index[b];
3693 }
3694
3695 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3696 {
3697         return REG_READ(ah, AR_TSF_L32);
3698 }
3699 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3700
3701 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3702                                           void (*trigger)(void *),
3703                                           void (*overflow)(void *),
3704                                           void *arg,
3705                                           u8 timer_index)
3706 {
3707         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3708         struct ath_gen_timer *timer;
3709
3710         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3711
3712         if (timer == NULL) {
3713                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3714                           "Failed to allocate memory"
3715                           "for hw timer[%d]\n", timer_index);
3716                 return NULL;
3717         }
3718
3719         /* allocate a hardware generic timer slot */
3720         timer_table->timers[timer_index] = timer;
3721         timer->index = timer_index;
3722         timer->trigger = trigger;
3723         timer->overflow = overflow;
3724         timer->arg = arg;
3725
3726         return timer;
3727 }
3728 EXPORT_SYMBOL(ath_gen_timer_alloc);
3729
3730 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3731                               struct ath_gen_timer *timer,
3732                               u32 timer_next,
3733                               u32 timer_period)
3734 {
3735         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3736         u32 tsf;
3737
3738         BUG_ON(!timer_period);
3739
3740         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3741
3742         tsf = ath9k_hw_gettsf32(ah);
3743
3744         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3745                   "curent tsf %x period %x"
3746                   "timer_next %x\n", tsf, timer_period, timer_next);
3747
3748         /*
3749          * Pull timer_next forward if the current TSF already passed it
3750          * because of software latency
3751          */
3752         if (timer_next < tsf)
3753                 timer_next = tsf + timer_period;
3754
3755         /*
3756          * Program generic timer registers
3757          */
3758         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3759                  timer_next);
3760         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3761                   timer_period);
3762         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3763                     gen_tmr_configuration[timer->index].mode_mask);
3764
3765         /* Enable both trigger and thresh interrupt masks */
3766         REG_SET_BIT(ah, AR_IMR_S5,
3767                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3768                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3769 }
3770 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3771
3772 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3773 {
3774         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3775
3776         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3777                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3778                 return;
3779         }
3780
3781         /* Clear generic timer enable bits. */
3782         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3783                         gen_tmr_configuration[timer->index].mode_mask);
3784
3785         /* Disable both trigger and thresh interrupt masks */
3786         REG_CLR_BIT(ah, AR_IMR_S5,
3787                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3788                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3789
3790         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3791 }
3792 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3793
3794 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3795 {
3796         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3797
3798         /* free the hardware generic timer slot */
3799         timer_table->timers[timer->index] = NULL;
3800         kfree(timer);
3801 }
3802 EXPORT_SYMBOL(ath_gen_timer_free);
3803
3804 /*
3805  * Generic Timer Interrupts handling
3806  */
3807 void ath_gen_timer_isr(struct ath_hw *ah)
3808 {
3809         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3810         struct ath_gen_timer *timer;
3811         struct ath_common *common = ath9k_hw_common(ah);
3812         u32 trigger_mask, thresh_mask, index;
3813
3814         /* get hardware generic timer interrupt status */
3815         trigger_mask = ah->intr_gen_timer_trigger;
3816         thresh_mask = ah->intr_gen_timer_thresh;
3817         trigger_mask &= timer_table->timer_mask.val;
3818         thresh_mask &= timer_table->timer_mask.val;
3819
3820         trigger_mask &= ~thresh_mask;
3821
3822         while (thresh_mask) {
3823                 index = rightmost_index(timer_table, &thresh_mask);
3824                 timer = timer_table->timers[index];
3825                 BUG_ON(!timer);
3826                 ath_print(common, ATH_DBG_HWTIMER,
3827                           "TSF overflow for Gen timer %d\n", index);
3828                 timer->overflow(timer->arg);
3829         }
3830
3831         while (trigger_mask) {
3832                 index = rightmost_index(timer_table, &trigger_mask);
3833                 timer = timer_table->timers[index];
3834                 BUG_ON(!timer);
3835                 ath_print(common, ATH_DBG_HWTIMER,
3836                           "Gen timer[%d] trigger\n", index);
3837                 timer->trigger(timer->arg);
3838         }
3839 }
3840 EXPORT_SYMBOL(ath_gen_timer_isr);
3841
3842 static struct {
3843         u32 version;
3844         const char * name;
3845 } ath_mac_bb_names[] = {
3846         /* Devices with external radios */
3847         { AR_SREV_VERSION_5416_PCI,     "5416" },
3848         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3849         { AR_SREV_VERSION_9100,         "9100" },
3850         { AR_SREV_VERSION_9160,         "9160" },
3851         /* Single-chip solutions */
3852         { AR_SREV_VERSION_9280,         "9280" },
3853         { AR_SREV_VERSION_9285,         "9285" },
3854         { AR_SREV_VERSION_9287,         "9287" },
3855         { AR_SREV_VERSION_9271,         "9271" },
3856 };
3857
3858 /* For devices with external radios */
3859 static struct {
3860         u16 version;
3861         const char * name;
3862 } ath_rf_names[] = {
3863         { 0,                            "5133" },
3864         { AR_RAD5133_SREV_MAJOR,        "5133" },
3865         { AR_RAD5122_SREV_MAJOR,        "5122" },
3866         { AR_RAD2133_SREV_MAJOR,        "2133" },
3867         { AR_RAD2122_SREV_MAJOR,        "2122" }
3868 };
3869
3870 /*
3871  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3872  */
3873 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3874 {
3875         int i;
3876
3877         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3878                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3879                         return ath_mac_bb_names[i].name;
3880                 }
3881         }
3882
3883         return "????";
3884 }
3885
3886 /*
3887  * Return the RF name. "????" is returned if the RF is unknown.
3888  * Used for devices with external radios.
3889  */
3890 static const char *ath9k_hw_rf_name(u16 rf_version)
3891 {
3892         int i;
3893
3894         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3895                 if (ath_rf_names[i].version == rf_version) {
3896                         return ath_rf_names[i].name;
3897                 }
3898         }
3899
3900         return "????";
3901 }
3902
3903 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3904 {
3905         int used;
3906
3907         /* chipsets >= AR9280 are single-chip */
3908         if (AR_SREV_9280_10_OR_LATER(ah)) {
3909                 used = snprintf(hw_name, len,
3910                                "Atheros AR%s Rev:%x",
3911                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3912                                ah->hw_version.macRev);
3913         }
3914         else {
3915                 used = snprintf(hw_name, len,
3916                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3917                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3918                                ah->hw_version.macRev,
3919                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3920                                                 AR_RADIO_SREV_MAJOR)),
3921                                ah->hw_version.phyRev);
3922         }
3923
3924         hw_name[used] = '\0';
3925 }
3926 EXPORT_SYMBOL(ath9k_hw_name);