2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "ar9003_phy.h"
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
38 static int __init ath9k_init(void)
42 module_init(ath9k_init);
44 static void __exit ath9k_exit(void)
48 module_exit(ath9k_exit);
50 /* Private hardware callbacks */
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 #ifdef CONFIG_ATH9K_DEBUGFS
86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
88 struct ath_softc *sc = common->priv;
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
131 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
134 struct ath_common *common = ath9k_hw_common(ah);
135 unsigned int clockrate;
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
140 else if (!ah->curchan) /* should really check for CCK instead */
141 clockrate = ATH9K_CLOCK_RATE_CCK;
142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ)
143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
149 if (conf_is_ht40(conf))
153 if (IS_CHAN_HALF_RATE(ah->curchan))
155 if (IS_CHAN_QUARTER_RATE(ah->curchan))
159 common->clockrate = clockrate;
162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
164 struct ath_common *common = ath9k_hw_common(ah);
166 return usecs * common->clockrate;
169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
173 BUG_ON(timeout < AH_TIME_QUANTUM);
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
176 if ((REG_READ(ah, reg) & mask) == val)
179 udelay(AH_TIME_QUANTUM);
182 ath_dbg(ath9k_hw_common(ah), ANY,
183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
188 EXPORT_SYMBOL(ath9k_hw_wait);
190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
194 hw_delay = (4 * hw_delay) / 22;
198 if (IS_CHAN_HALF_RATE(chan))
200 else if (IS_CHAN_QUARTER_RATE(chan))
203 udelay(hw_delay + BASE_ACTIVATE_DELAY);
206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
207 int column, unsigned int *writecnt)
211 ENABLE_REGWRITE_BUFFER(ah);
212 for (r = 0; r < array->ia_rows; r++) {
213 REG_WRITE(ah, INI_RA(array, r, 0),
214 INI_RA(array, r, column));
217 REGWRITE_BUFFER_FLUSH(ah);
220 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225 for (i = 0, retval = 0; i < n; i++) {
226 retval = (retval << 1) | (val & 1);
232 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
234 u32 frameLen, u16 rateix,
237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
243 case WLAN_RC_PHY_CCK:
244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
247 numBits = frameLen << 3;
248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
250 case WLAN_RC_PHY_OFDM:
251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
253 numBits = OFDM_PLCP_BITS + (frameLen << 3);
254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
255 txTime = OFDM_SIFS_TIME_QUARTER
256 + OFDM_PREAMBLE_TIME_QUARTER
257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
258 } else if (ah->curchan &&
259 IS_CHAN_HALF_RATE(ah->curchan)) {
260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
261 numBits = OFDM_PLCP_BITS + (frameLen << 3);
262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
263 txTime = OFDM_SIFS_TIME_HALF +
264 OFDM_PREAMBLE_TIME_HALF
265 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
268 numBits = OFDM_PLCP_BITS + (frameLen << 3);
269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
271 + (numSymbols * OFDM_SYMBOL_TIME);
275 ath_err(ath9k_hw_common(ah),
276 "Unknown phy %u (rate ix %u)\n", phy, rateix);
283 EXPORT_SYMBOL(ath9k_hw_computetxtime);
285 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
286 struct ath9k_channel *chan,
287 struct chan_centers *centers)
291 if (!IS_CHAN_HT40(chan)) {
292 centers->ctl_center = centers->ext_center =
293 centers->synth_center = chan->channel;
297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
298 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
299 centers->synth_center =
300 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
303 centers->synth_center =
304 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
308 centers->ctl_center =
309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
310 /* 25 MHz spacing is supported by hw but not on upper layers */
311 centers->ext_center =
312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
319 static void ath9k_hw_read_revisions(struct ath_hw *ah)
323 switch (ah->hw_version.devid) {
324 case AR5416_AR9100_DEVID:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
327 case AR9300_DEVID_AR9330:
328 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
329 if (ah->get_mac_revision) {
330 ah->hw_version.macRev = ah->get_mac_revision();
332 val = REG_READ(ah, AR_SREV);
333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
336 case AR9300_DEVID_AR9340:
337 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
338 val = REG_READ(ah, AR_SREV);
339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
341 case AR9300_DEVID_QCA955X:
342 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
349 val = REG_READ(ah, AR_SREV);
350 ah->hw_version.macVersion =
351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
355 ah->is_pciexpress = true;
357 ah->is_pciexpress = (val &
358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
360 if (!AR_SREV_9100(ah))
361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
363 ah->hw_version.macRev = val & AR_SREV_REVISION;
365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
366 ah->is_pciexpress = true;
370 /************************************/
371 /* HW Attach, Detach, Init Routines */
372 /************************************/
374 static void ath9k_hw_disablepcie(struct ath_hw *ah)
376 if (!AR_SREV_5416(ah))
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
392 /* This should work for all families including legacy */
393 static bool ath9k_hw_chip_test(struct ath_hw *ah)
395 struct ath_common *common = ath9k_hw_common(ah);
396 u32 regAddr[2] = { AR_STA_ID0 };
398 static const u32 patternData[4] = {
399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
403 if (!AR_SREV_9300_20_OR_LATER(ah)) {
405 regAddr[1] = AR_PHY_BASE + (8 << 2);
409 for (i = 0; i < loop_max; i++) {
410 u32 addr = regAddr[i];
413 regHold[i] = REG_READ(ah, addr);
414 for (j = 0; j < 0x100; j++) {
415 wrData = (j << 16) | j;
416 REG_WRITE(ah, addr, wrData);
417 rdData = REG_READ(ah, addr);
418 if (rdData != wrData) {
420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
421 addr, wrData, rdData);
425 for (j = 0; j < 4; j++) {
426 wrData = patternData[j];
427 REG_WRITE(ah, addr, wrData);
428 rdData = REG_READ(ah, addr);
429 if (wrData != rdData) {
431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
432 addr, wrData, rdData);
436 REG_WRITE(ah, regAddr[i], regHold[i]);
443 static void ath9k_hw_init_config(struct ath_hw *ah)
447 ah->config.dma_beacon_response_time = 1;
448 ah->config.sw_beacon_response_time = 6;
449 ah->config.additional_swba_backoff = 0;
450 ah->config.ack_6mb = 0x0;
451 ah->config.cwm_ignore_extcca = 0;
452 ah->config.pcie_clock_req = 0;
453 ah->config.analog_shiftreg = 1;
455 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
456 ah->config.spurchans[i][0] = AR_NO_SPUR;
457 ah->config.spurchans[i][1] = AR_NO_SPUR;
460 ah->config.rx_intr_mitigation = true;
461 ah->config.pcieSerDesWrite = true;
464 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
465 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
466 * This means we use it for all AR5416 devices, and the few
467 * minor PCI AR9280 devices out there.
469 * Serialization is required because these devices do not handle
470 * well the case of two concurrent reads/writes due to the latency
471 * involved. During one read/write another read/write can be issued
472 * on another CPU while the previous read/write may still be working
473 * on our hardware, if we hit this case the hardware poops in a loop.
474 * We prevent this by serializing reads and writes.
476 * This issue is not present on PCI-Express devices or pre-AR5416
477 * devices (legacy, 802.11abg).
479 if (num_possible_cpus() > 1)
480 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
483 static void ath9k_hw_init_defaults(struct ath_hw *ah)
485 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
487 regulatory->country_code = CTRY_DEFAULT;
488 regulatory->power_limit = MAX_RATE_POWER;
490 ah->hw_version.magic = AR5416_MAGIC;
491 ah->hw_version.subvendorid = 0;
494 ah->sta_id1_defaults =
495 AR_STA_ID1_CRPT_MIC_ENABLE |
496 AR_STA_ID1_MCAST_KSRCH;
497 if (AR_SREV_9100(ah))
498 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
499 ah->slottime = ATH9K_SLOT_TIME_9;
500 ah->globaltxtimeout = (u32) -1;
501 ah->power_mode = ATH9K_PM_UNDEFINED;
502 ah->htc_reset_init = true;
505 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
507 struct ath_common *common = ath9k_hw_common(ah);
511 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
514 for (i = 0; i < 3; i++) {
515 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
517 common->macaddr[2 * i] = eeval >> 8;
518 common->macaddr[2 * i + 1] = eeval & 0xff;
520 if (sum == 0 || sum == 0xffff * 3)
521 return -EADDRNOTAVAIL;
526 static int ath9k_hw_post_init(struct ath_hw *ah)
528 struct ath_common *common = ath9k_hw_common(ah);
531 if (common->bus_ops->ath_bus_type != ATH_USB) {
532 if (!ath9k_hw_chip_test(ah))
536 if (!AR_SREV_9300_20_OR_LATER(ah)) {
537 ecode = ar9002_hw_rf_claim(ah);
542 ecode = ath9k_hw_eeprom_init(ah);
546 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
547 ah->eep_ops->get_eeprom_ver(ah),
548 ah->eep_ops->get_eeprom_rev(ah));
550 ath9k_hw_ani_init(ah);
553 * EEPROM needs to be initialized before we do this.
554 * This is required for regulatory compliance.
556 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
557 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
558 if ((regdmn & 0xF0) == CTL_FCC) {
559 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
560 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
567 static int ath9k_hw_attach_ops(struct ath_hw *ah)
569 if (!AR_SREV_9300_20_OR_LATER(ah))
570 return ar9002_hw_attach_ops(ah);
572 ar9003_hw_attach_ops(ah);
576 /* Called for all hardware families */
577 static int __ath9k_hw_init(struct ath_hw *ah)
579 struct ath_common *common = ath9k_hw_common(ah);
582 ath9k_hw_read_revisions(ah);
585 * Read back AR_WA into a permanent copy and set bits 14 and 17.
586 * We need to do this to avoid RMW of this register. We cannot
587 * read the reg when chip is asleep.
589 if (AR_SREV_9300_20_OR_LATER(ah)) {
590 ah->WARegVal = REG_READ(ah, AR_WA);
591 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
592 AR_WA_ASPM_TIMER_BASED_DISABLE);
595 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
596 ath_err(common, "Couldn't reset chip\n");
600 if (AR_SREV_9565(ah)) {
601 ah->WARegVal |= AR_WA_BIT22;
602 REG_WRITE(ah, AR_WA, ah->WARegVal);
605 ath9k_hw_init_defaults(ah);
606 ath9k_hw_init_config(ah);
608 r = ath9k_hw_attach_ops(ah);
612 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
613 ath_err(common, "Couldn't wakeup chip\n");
617 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
618 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
619 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
620 !ah->is_pciexpress)) {
621 ah->config.serialize_regmode =
624 ah->config.serialize_regmode =
629 ath_dbg(common, RESET, "serialize_regmode is %d\n",
630 ah->config.serialize_regmode);
632 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
633 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
635 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
637 switch (ah->hw_version.macVersion) {
638 case AR_SREV_VERSION_5416_PCI:
639 case AR_SREV_VERSION_5416_PCIE:
640 case AR_SREV_VERSION_9160:
641 case AR_SREV_VERSION_9100:
642 case AR_SREV_VERSION_9280:
643 case AR_SREV_VERSION_9285:
644 case AR_SREV_VERSION_9287:
645 case AR_SREV_VERSION_9271:
646 case AR_SREV_VERSION_9300:
647 case AR_SREV_VERSION_9330:
648 case AR_SREV_VERSION_9485:
649 case AR_SREV_VERSION_9340:
650 case AR_SREV_VERSION_9462:
651 case AR_SREV_VERSION_9550:
652 case AR_SREV_VERSION_9565:
656 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
657 ah->hw_version.macVersion, ah->hw_version.macRev);
661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
662 AR_SREV_9330(ah) || AR_SREV_9550(ah))
663 ah->is_pciexpress = false;
665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
666 ath9k_hw_init_cal_settings(ah);
668 ah->ani_function = ATH9K_ANI_ALL;
669 if (!AR_SREV_9300_20_OR_LATER(ah))
670 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
672 if (!ah->is_pciexpress)
673 ath9k_hw_disablepcie(ah);
675 r = ath9k_hw_post_init(ah);
679 ath9k_hw_init_mode_gain_regs(ah);
680 r = ath9k_hw_fill_cap_info(ah);
684 r = ath9k_hw_init_macaddr(ah);
686 ath_err(common, "Failed to initialize MAC address\n");
690 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
691 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
693 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
695 if (AR_SREV_9330(ah))
696 ah->bb_watchdog_timeout_ms = 85;
698 ah->bb_watchdog_timeout_ms = 25;
700 common->state = ATH_HW_INITIALIZED;
705 int ath9k_hw_init(struct ath_hw *ah)
708 struct ath_common *common = ath9k_hw_common(ah);
710 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
711 switch (ah->hw_version.devid) {
712 case AR5416_DEVID_PCI:
713 case AR5416_DEVID_PCIE:
714 case AR5416_AR9100_DEVID:
715 case AR9160_DEVID_PCI:
716 case AR9280_DEVID_PCI:
717 case AR9280_DEVID_PCIE:
718 case AR9285_DEVID_PCIE:
719 case AR9287_DEVID_PCI:
720 case AR9287_DEVID_PCIE:
721 case AR2427_DEVID_PCIE:
722 case AR9300_DEVID_PCIE:
723 case AR9300_DEVID_AR9485_PCIE:
724 case AR9300_DEVID_AR9330:
725 case AR9300_DEVID_AR9340:
726 case AR9300_DEVID_QCA955X:
727 case AR9300_DEVID_AR9580:
728 case AR9300_DEVID_AR9462:
729 case AR9485_DEVID_AR1111:
730 case AR9300_DEVID_AR9565:
733 if (common->bus_ops->ath_bus_type == ATH_USB)
735 ath_err(common, "Hardware device ID 0x%04x not supported\n",
736 ah->hw_version.devid);
740 ret = __ath9k_hw_init(ah);
743 "Unable to initialize hardware; initialization status: %d\n",
750 EXPORT_SYMBOL(ath9k_hw_init);
752 static void ath9k_hw_init_qos(struct ath_hw *ah)
754 ENABLE_REGWRITE_BUFFER(ah);
756 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
757 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
759 REG_WRITE(ah, AR_QOS_NO_ACK,
760 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
761 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
762 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
764 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
765 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
766 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
767 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
768 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
770 REGWRITE_BUFFER_FLUSH(ah);
773 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
775 struct ath_common *common = ath9k_hw_common(ah);
778 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
780 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
782 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
786 if (WARN_ON_ONCE(i >= 100)) {
787 ath_err(common, "PLL4 meaurement not done\n");
794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
796 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
798 static void ath9k_hw_init_pll(struct ath_hw *ah,
799 struct ath9k_channel *chan)
803 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
804 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
806 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
808 AR_CH0_DPLL2_KD, 0x40);
809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
810 AR_CH0_DPLL2_KI, 0x4);
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
813 AR_CH0_BB_DPLL1_REFDIV, 0x5);
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
815 AR_CH0_BB_DPLL1_NINI, 0x58);
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
817 AR_CH0_BB_DPLL1_NFRAC, 0x0);
819 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
820 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
822 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
824 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
826 /* program BB PLL phase_shift to 0x6 */
827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
828 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
831 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
833 } else if (AR_SREV_9330(ah)) {
834 u32 ddr_dpll2, pll_control2, kd;
836 if (ah->is_clk_25mhz) {
837 ddr_dpll2 = 0x18e82f01;
838 pll_control2 = 0xe04a3d;
841 ddr_dpll2 = 0x19e82f01;
842 pll_control2 = 0x886666;
846 /* program DDR PLL ki and kd value */
847 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
849 /* program DDR PLL phase_shift */
850 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
851 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
853 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
856 /* program refdiv, nint, frac to RTC register */
857 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
859 /* program BB PLL kd and ki value */
860 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
863 /* program BB PLL phase_shift */
864 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
865 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
866 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
867 u32 regval, pll2_divint, pll2_divfrac, refdiv;
869 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
872 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
875 if (ah->is_clk_25mhz) {
877 pll2_divfrac = 0x1eb85;
880 if (AR_SREV_9340(ah)) {
886 pll2_divfrac = 0x26666;
891 regval = REG_READ(ah, AR_PHY_PLL_MODE);
892 regval |= (0x1 << 16);
893 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
896 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
897 (pll2_divint << 18) | pll2_divfrac);
900 regval = REG_READ(ah, AR_PHY_PLL_MODE);
901 if (AR_SREV_9340(ah))
902 regval = (regval & 0x80071fff) | (0x1 << 30) |
903 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
905 regval = (regval & 0x80071fff) | (0x3 << 30) |
906 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
907 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
908 REG_WRITE(ah, AR_PHY_PLL_MODE,
909 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
913 pll = ath9k_hw_compute_pll_control(ah, chan);
914 if (AR_SREV_9565(ah))
916 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
918 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
922 /* Switch the core clock for ar9271 to 117Mhz */
923 if (AR_SREV_9271(ah)) {
925 REG_WRITE(ah, 0x50040, 0x304);
928 udelay(RTC_PLL_SETTLE_DELAY);
930 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
932 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
933 if (ah->is_clk_25mhz) {
934 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
935 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
936 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
938 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
939 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
940 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
946 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
947 enum nl80211_iftype opmode)
949 u32 sync_default = AR_INTR_SYNC_DEFAULT;
950 u32 imr_reg = AR_IMR_TXERR |
956 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
957 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
959 if (AR_SREV_9300_20_OR_LATER(ah)) {
960 imr_reg |= AR_IMR_RXOK_HP;
961 if (ah->config.rx_intr_mitigation)
962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
964 imr_reg |= AR_IMR_RXOK_LP;
967 if (ah->config.rx_intr_mitigation)
968 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
970 imr_reg |= AR_IMR_RXOK;
973 if (ah->config.tx_intr_mitigation)
974 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
976 imr_reg |= AR_IMR_TXOK;
978 ENABLE_REGWRITE_BUFFER(ah);
980 REG_WRITE(ah, AR_IMR, imr_reg);
981 ah->imrs2_reg |= AR_IMR_S2_GTT;
982 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
984 if (!AR_SREV_9100(ah)) {
985 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
986 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
987 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
990 REGWRITE_BUFFER_FLUSH(ah);
992 if (AR_SREV_9300_20_OR_LATER(ah)) {
993 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
994 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
995 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
996 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
1000 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1002 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1003 val = min(val, (u32) 0xFFFF);
1004 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1007 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1009 u32 val = ath9k_hw_mac_to_clks(ah, us);
1010 val = min(val, (u32) 0xFFFF);
1011 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1014 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1016 u32 val = ath9k_hw_mac_to_clks(ah, us);
1017 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1018 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1021 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1023 u32 val = ath9k_hw_mac_to_clks(ah, us);
1024 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1025 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1028 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1031 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1033 ah->globaltxtimeout = (u32) -1;
1036 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1037 ah->globaltxtimeout = tu;
1042 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1044 struct ath_common *common = ath9k_hw_common(ah);
1045 struct ieee80211_conf *conf = &common->hw->conf;
1046 const struct ath9k_channel *chan = ah->curchan;
1047 int acktimeout, ctstimeout, ack_offset = 0;
1050 int rx_lat = 0, tx_lat = 0, eifs = 0;
1053 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1059 if (ah->misc_mode != 0)
1060 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1062 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1068 if (IS_CHAN_5GHZ(chan))
1073 if (IS_CHAN_HALF_RATE(chan)) {
1077 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1083 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1085 rx_lat = (rx_lat * 4) - 1;
1087 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1094 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1095 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1096 reg = AR_USEC_ASYNC_FIFO;
1098 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1100 reg = REG_READ(ah, AR_USEC);
1102 rx_lat = MS(reg, AR_USEC_RX_LAT);
1103 tx_lat = MS(reg, AR_USEC_TX_LAT);
1105 slottime = ah->slottime;
1108 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1109 slottime += 3 * ah->coverage_class;
1110 acktimeout = slottime + sifstime + ack_offset;
1111 ctstimeout = acktimeout;
1114 * Workaround for early ACK timeouts, add an offset to match the
1115 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1116 * This was initially only meant to work around an issue with delayed
1117 * BA frames in some implementations, but it has been found to fix ACK
1118 * timeout issues in other cases as well.
1120 if (conf->chandef.chan &&
1121 conf->chandef.chan->band == IEEE80211_BAND_2GHZ &&
1122 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1123 acktimeout += 64 - sifstime - ah->slottime;
1124 ctstimeout += 48 - sifstime - ah->slottime;
1127 ath9k_hw_set_sifs_time(ah, sifstime);
1128 ath9k_hw_setslottime(ah, slottime);
1129 ath9k_hw_set_ack_timeout(ah, acktimeout);
1130 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1131 if (ah->globaltxtimeout != (u32) -1)
1132 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1134 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1135 REG_RMW(ah, AR_USEC,
1136 (common->clockrate - 1) |
1137 SM(rx_lat, AR_USEC_RX_LAT) |
1138 SM(tx_lat, AR_USEC_TX_LAT),
1139 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1142 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1144 void ath9k_hw_deinit(struct ath_hw *ah)
1146 struct ath_common *common = ath9k_hw_common(ah);
1148 if (common->state < ATH_HW_INITIALIZED)
1151 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153 EXPORT_SYMBOL(ath9k_hw_deinit);
1159 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1161 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1163 if (IS_CHAN_B(chan))
1165 else if (IS_CHAN_G(chan))
1173 /****************************************/
1174 /* Reset and Channel Switching Routines */
1175 /****************************************/
1177 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1179 struct ath_common *common = ath9k_hw_common(ah);
1182 ENABLE_REGWRITE_BUFFER(ah);
1185 * set AHB_MODE not to do cacheline prefetches
1187 if (!AR_SREV_9300_20_OR_LATER(ah))
1188 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1191 * let mac dma reads be in 128 byte chunks
1193 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1195 REGWRITE_BUFFER_FLUSH(ah);
1198 * Restore TX Trigger Level to its pre-reset value.
1199 * The initial value depends on whether aggregation is enabled, and is
1200 * adjusted whenever underruns are detected.
1202 if (!AR_SREV_9300_20_OR_LATER(ah))
1203 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1205 ENABLE_REGWRITE_BUFFER(ah);
1208 * let mac dma writes be in 128 byte chunks
1210 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1213 * Setup receive FIFO threshold to hold off TX activities
1215 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1217 if (AR_SREV_9300_20_OR_LATER(ah)) {
1218 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1219 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1221 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1222 ah->caps.rx_status_len);
1226 * reduce the number of usable entries in PCU TXBUF to avoid
1227 * wrap around issues.
1229 if (AR_SREV_9285(ah)) {
1230 /* For AR9285 the number of Fifos are reduced to half.
1231 * So set the usable tx buf size also to half to
1232 * avoid data/delimiter underruns
1234 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1235 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1236 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1237 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1239 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1242 if (!AR_SREV_9271(ah))
1243 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1245 REGWRITE_BUFFER_FLUSH(ah);
1247 if (AR_SREV_9300_20_OR_LATER(ah))
1248 ath9k_hw_reset_txstatus_ring(ah);
1251 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1253 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1254 u32 set = AR_STA_ID1_KSRCH_MODE;
1257 case NL80211_IFTYPE_ADHOC:
1258 set |= AR_STA_ID1_ADHOC;
1259 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1261 case NL80211_IFTYPE_MESH_POINT:
1262 case NL80211_IFTYPE_AP:
1263 set |= AR_STA_ID1_STA_AP;
1265 case NL80211_IFTYPE_STATION:
1266 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1269 if (!ah->is_monitoring)
1273 REG_RMW(ah, AR_STA_ID1, set, mask);
1276 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1277 u32 *coef_mantissa, u32 *coef_exponent)
1279 u32 coef_exp, coef_man;
1281 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1282 if ((coef_scaled >> coef_exp) & 0x1)
1285 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1287 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1289 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1290 *coef_exponent = coef_exp - 16;
1293 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1298 if (AR_SREV_9100(ah)) {
1299 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1300 AR_RTC_DERIVED_CLK_PERIOD, 1);
1301 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1304 ENABLE_REGWRITE_BUFFER(ah);
1306 if (AR_SREV_9300_20_OR_LATER(ah)) {
1307 REG_WRITE(ah, AR_WA, ah->WARegVal);
1311 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1312 AR_RTC_FORCE_WAKE_ON_INT);
1314 if (AR_SREV_9100(ah)) {
1315 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1316 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1318 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1319 if (AR_SREV_9340(ah))
1320 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1322 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1323 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1327 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1330 if (!AR_SREV_9300_20_OR_LATER(ah))
1332 REG_WRITE(ah, AR_RC, val);
1334 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1335 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1337 rst_flags = AR_RTC_RC_MAC_WARM;
1338 if (type == ATH9K_RESET_COLD)
1339 rst_flags |= AR_RTC_RC_MAC_COLD;
1342 if (AR_SREV_9330(ah)) {
1347 * call external reset function to reset WMAC if:
1348 * - doing a cold reset
1349 * - we have pending frames in the TX queues
1352 for (i = 0; i < AR_NUM_QCU; i++) {
1353 npend = ath9k_hw_numtxpending(ah, i);
1358 if (ah->external_reset &&
1359 (npend || type == ATH9K_RESET_COLD)) {
1362 ath_dbg(ath9k_hw_common(ah), RESET,
1363 "reset MAC via external reset\n");
1365 reset_err = ah->external_reset();
1367 ath_err(ath9k_hw_common(ah),
1368 "External reset failed, err=%d\n",
1373 REG_WRITE(ah, AR_RTC_RESET, 1);
1377 if (ath9k_hw_mci_is_enabled(ah))
1378 ar9003_mci_check_gpm_offset(ah);
1380 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1382 REGWRITE_BUFFER_FLUSH(ah);
1386 REG_WRITE(ah, AR_RTC_RC, 0);
1387 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1388 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1392 if (!AR_SREV_9100(ah))
1393 REG_WRITE(ah, AR_RC, 0);
1395 if (AR_SREV_9100(ah))
1401 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1403 ENABLE_REGWRITE_BUFFER(ah);
1405 if (AR_SREV_9300_20_OR_LATER(ah)) {
1406 REG_WRITE(ah, AR_WA, ah->WARegVal);
1410 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1411 AR_RTC_FORCE_WAKE_ON_INT);
1413 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1414 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1416 REG_WRITE(ah, AR_RTC_RESET, 0);
1418 REGWRITE_BUFFER_FLUSH(ah);
1420 if (!AR_SREV_9300_20_OR_LATER(ah))
1423 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1424 REG_WRITE(ah, AR_RC, 0);
1426 REG_WRITE(ah, AR_RTC_RESET, 1);
1428 if (!ath9k_hw_wait(ah,
1433 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1437 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1440 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1444 if (AR_SREV_9300_20_OR_LATER(ah)) {
1445 REG_WRITE(ah, AR_WA, ah->WARegVal);
1449 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1450 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1452 if (!ah->reset_power_on)
1453 type = ATH9K_RESET_POWER_ON;
1456 case ATH9K_RESET_POWER_ON:
1457 ret = ath9k_hw_set_reset_power_on(ah);
1459 ah->reset_power_on = true;
1461 case ATH9K_RESET_WARM:
1462 case ATH9K_RESET_COLD:
1463 ret = ath9k_hw_set_reset(ah, type);
1472 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1473 struct ath9k_channel *chan)
1475 int reset_type = ATH9K_RESET_WARM;
1477 if (AR_SREV_9280(ah)) {
1478 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1479 reset_type = ATH9K_RESET_POWER_ON;
1481 reset_type = ATH9K_RESET_COLD;
1482 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1483 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1484 reset_type = ATH9K_RESET_COLD;
1486 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1489 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1492 ah->chip_fullsleep = false;
1494 if (AR_SREV_9330(ah))
1495 ar9003_hw_internal_regulator_apply(ah);
1496 ath9k_hw_init_pll(ah, chan);
1497 ath9k_hw_set_rfmode(ah, chan);
1502 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1503 struct ath9k_channel *chan)
1505 struct ath_common *common = ath9k_hw_common(ah);
1506 struct ath9k_hw_capabilities *pCap = &ah->caps;
1507 bool band_switch = false, mode_diff = false;
1508 u8 ini_reloaded = 0;
1512 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1513 u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ);
1514 u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ);
1515 band_switch = (cur != new);
1516 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1519 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1520 if (ath9k_hw_numtxpending(ah, qnum)) {
1521 ath_dbg(common, QUEUE,
1522 "Transmit frames pending on queue %d\n", qnum);
1527 if (!ath9k_hw_rfbus_req(ah)) {
1528 ath_err(common, "Could not kill baseband RX\n");
1532 if (band_switch || mode_diff) {
1533 ath9k_hw_mark_phy_inactive(ah);
1537 ath9k_hw_init_pll(ah, chan);
1539 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1540 ath_err(common, "Failed to do fast channel change\n");
1545 ath9k_hw_set_channel_regs(ah, chan);
1547 r = ath9k_hw_rf_set_freq(ah, chan);
1549 ath_err(common, "Failed to set channel\n");
1552 ath9k_hw_set_clockrate(ah);
1553 ath9k_hw_apply_txpower(ah, chan, false);
1555 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1556 ath9k_hw_set_delta_slope(ah, chan);
1558 ath9k_hw_spur_mitigate_freq(ah, chan);
1560 if (band_switch || ini_reloaded)
1561 ah->eep_ops->set_board_values(ah, chan);
1563 ath9k_hw_init_bb(ah, chan);
1564 ath9k_hw_rfbus_done(ah);
1566 if (band_switch || ini_reloaded) {
1567 ah->ah_flags |= AH_FASTCC;
1568 ath9k_hw_init_cal(ah, chan);
1569 ah->ah_flags &= ~AH_FASTCC;
1575 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1577 u32 gpio_mask = ah->gpio_mask;
1580 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1581 if (!(gpio_mask & 1))
1584 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1585 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1589 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1590 int *hang_state, int *hang_pos)
1592 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1593 u32 chain_state, dcs_pos, i;
1595 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1596 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1597 for (i = 0; i < 3; i++) {
1598 if (chain_state == dcu_chain_state[i]) {
1599 *hang_state = chain_state;
1600 *hang_pos = dcs_pos;
1608 #define DCU_COMPLETE_STATE 1
1609 #define DCU_COMPLETE_STATE_MASK 0x3
1610 #define NUM_STATUS_READS 50
1611 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1613 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1614 u32 i, hang_pos, hang_state, num_state = 6;
1616 comp_state = REG_READ(ah, AR_DMADBG_6);
1618 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1619 ath_dbg(ath9k_hw_common(ah), RESET,
1620 "MAC Hang signature not found at DCU complete\n");
1624 chain_state = REG_READ(ah, dcs_reg);
1625 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1626 goto hang_check_iter;
1628 dcs_reg = AR_DMADBG_5;
1630 chain_state = REG_READ(ah, dcs_reg);
1631 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1632 goto hang_check_iter;
1634 ath_dbg(ath9k_hw_common(ah), RESET,
1635 "MAC Hang signature 1 not found\n");
1639 ath_dbg(ath9k_hw_common(ah), RESET,
1640 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1641 chain_state, comp_state, hang_state, hang_pos);
1643 for (i = 0; i < NUM_STATUS_READS; i++) {
1644 chain_state = REG_READ(ah, dcs_reg);
1645 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1646 comp_state = REG_READ(ah, AR_DMADBG_6);
1648 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1649 DCU_COMPLETE_STATE) ||
1650 (chain_state != hang_state))
1654 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1659 void ath9k_hw_check_nav(struct ath_hw *ah)
1661 struct ath_common *common = ath9k_hw_common(ah);
1664 val = REG_READ(ah, AR_NAV);
1665 if (val != 0xdeadbeef && val > 0x7fff) {
1666 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1667 REG_WRITE(ah, AR_NAV, 0);
1670 EXPORT_SYMBOL(ath9k_hw_check_nav);
1672 bool ath9k_hw_check_alive(struct ath_hw *ah)
1677 if (AR_SREV_9300(ah))
1678 return !ath9k_hw_detect_mac_hang(ah);
1680 if (AR_SREV_9285_12_OR_LATER(ah))
1684 reg = REG_READ(ah, AR_OBS_BUS_1);
1686 if ((reg & 0x7E7FFFEF) == 0x00702400)
1689 switch (reg & 0x7E000B00) {
1697 } while (count-- > 0);
1701 EXPORT_SYMBOL(ath9k_hw_check_alive);
1703 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1705 /* Setup MFP options for CCMP */
1706 if (AR_SREV_9280_20_OR_LATER(ah)) {
1707 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1708 * frames when constructing CCMP AAD. */
1709 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1711 ah->sw_mgmt_crypto = false;
1712 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1713 /* Disable hardware crypto for management frames */
1714 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1715 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1716 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1717 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1718 ah->sw_mgmt_crypto = true;
1720 ah->sw_mgmt_crypto = true;
1724 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1725 u32 macStaId1, u32 saveDefAntenna)
1727 struct ath_common *common = ath9k_hw_common(ah);
1729 ENABLE_REGWRITE_BUFFER(ah);
1731 REG_RMW(ah, AR_STA_ID1, macStaId1
1732 | AR_STA_ID1_RTS_USE_DEF
1733 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1734 | ah->sta_id1_defaults,
1735 ~AR_STA_ID1_SADH_MASK);
1736 ath_hw_setbssidmask(common);
1737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1738 ath9k_hw_write_associd(ah);
1739 REG_WRITE(ah, AR_ISR, ~0);
1740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1742 REGWRITE_BUFFER_FLUSH(ah);
1744 ath9k_hw_set_operating_mode(ah, ah->opmode);
1747 static void ath9k_hw_init_queues(struct ath_hw *ah)
1751 ENABLE_REGWRITE_BUFFER(ah);
1753 for (i = 0; i < AR_NUM_DCU; i++)
1754 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1756 REGWRITE_BUFFER_FLUSH(ah);
1759 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1760 ath9k_hw_resettxqueue(ah, i);
1764 * For big endian systems turn on swapping for descriptors
1766 static void ath9k_hw_init_desc(struct ath_hw *ah)
1768 struct ath_common *common = ath9k_hw_common(ah);
1770 if (AR_SREV_9100(ah)) {
1772 mask = REG_READ(ah, AR_CFG);
1773 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1774 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1777 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1778 REG_WRITE(ah, AR_CFG, mask);
1779 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1780 REG_READ(ah, AR_CFG));
1783 if (common->bus_ops->ath_bus_type == ATH_USB) {
1784 /* Configure AR9271 target WLAN */
1785 if (AR_SREV_9271(ah))
1786 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1788 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1791 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1793 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1795 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1801 * Fast channel change:
1802 * (Change synthesizer based on channel freq without resetting chip)
1804 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1806 struct ath_common *common = ath9k_hw_common(ah);
1807 struct ath9k_hw_capabilities *pCap = &ah->caps;
1810 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1813 if (ah->chip_fullsleep)
1819 if (chan->channel == ah->curchan->channel)
1822 if ((ah->curchan->channelFlags | chan->channelFlags) &
1823 (CHANNEL_HALF | CHANNEL_QUARTER))
1827 * If cross-band fcc is not supoprted, bail out if
1828 * either channelFlags or chanmode differ.
1830 * chanmode will be different if the HT operating mode
1831 * changes because of CSA.
1833 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH)) {
1834 if ((chan->channelFlags & CHANNEL_ALL) !=
1835 (ah->curchan->channelFlags & CHANNEL_ALL))
1838 if (chan->chanmode != ah->curchan->chanmode)
1842 if (!ath9k_hw_check_alive(ah))
1846 * For AR9462, make sure that calibration data for
1847 * re-using are present.
1849 if (AR_SREV_9462(ah) && (ah->caldata &&
1850 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1851 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1852 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1855 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1856 ah->curchan->channel, chan->channel);
1858 ret = ath9k_hw_channel_change(ah, chan);
1862 if (ath9k_hw_mci_is_enabled(ah))
1863 ar9003_mci_2g5g_switch(ah, false);
1865 ath9k_hw_loadnf(ah, ah->curchan);
1866 ath9k_hw_start_nfcal(ah, true);
1868 if (AR_SREV_9271(ah))
1869 ar9002_hw_load_ani_reg(ah, chan);
1876 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1877 struct ath9k_hw_cal_data *caldata, bool fastcc)
1879 struct ath_common *common = ath9k_hw_common(ah);
1885 bool start_mci_reset = false;
1886 bool save_fullsleep = ah->chip_fullsleep;
1888 if (ath9k_hw_mci_is_enabled(ah)) {
1889 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1890 if (start_mci_reset)
1894 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1897 if (ah->curchan && !ah->chip_fullsleep)
1898 ath9k_hw_getnf(ah, ah->curchan);
1900 ah->caldata = caldata;
1901 if (caldata && (chan->channel != caldata->channel ||
1902 chan->channelFlags != caldata->channelFlags ||
1903 chan->chanmode != caldata->chanmode)) {
1904 /* Operating channel changed, reset channel calibration data */
1905 memset(caldata, 0, sizeof(*caldata));
1906 ath9k_init_nfcal_hist_buffer(ah, chan);
1907 } else if (caldata) {
1908 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1910 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1913 r = ath9k_hw_do_fastcc(ah, chan);
1918 if (ath9k_hw_mci_is_enabled(ah))
1919 ar9003_mci_stop_bt(ah, save_fullsleep);
1921 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1922 if (saveDefAntenna == 0)
1925 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1927 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1928 if (AR_SREV_9100(ah) ||
1929 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1930 tsf = ath9k_hw_gettsf64(ah);
1932 saveLedState = REG_READ(ah, AR_CFG_LED) &
1933 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1934 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1936 ath9k_hw_mark_phy_inactive(ah);
1938 ah->paprd_table_write_done = false;
1940 /* Only required on the first reset */
1941 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1943 AR9271_RESET_POWER_DOWN_CONTROL,
1944 AR9271_RADIO_RF_RST);
1948 if (!ath9k_hw_chip_reset(ah, chan)) {
1949 ath_err(common, "Chip reset failed\n");
1953 /* Only required on the first reset */
1954 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1955 ah->htc_reset_init = false;
1957 AR9271_RESET_POWER_DOWN_CONTROL,
1958 AR9271_GATE_MAC_CTL);
1964 ath9k_hw_settsf64(ah, tsf);
1966 if (AR_SREV_9280_20_OR_LATER(ah))
1967 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1969 if (!AR_SREV_9300_20_OR_LATER(ah))
1970 ar9002_hw_enable_async_fifo(ah);
1972 r = ath9k_hw_process_ini(ah, chan);
1976 if (ath9k_hw_mci_is_enabled(ah))
1977 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1980 * Some AR91xx SoC devices frequently fail to accept TSF writes
1981 * right after the chip reset. When that happens, write a new
1982 * value after the initvals have been applied, with an offset
1983 * based on measured time difference
1985 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1987 ath9k_hw_settsf64(ah, tsf);
1990 ath9k_hw_init_mfp(ah);
1992 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1993 ath9k_hw_set_delta_slope(ah, chan);
1995 ath9k_hw_spur_mitigate_freq(ah, chan);
1996 ah->eep_ops->set_board_values(ah, chan);
1998 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
2000 r = ath9k_hw_rf_set_freq(ah, chan);
2004 ath9k_hw_set_clockrate(ah);
2006 ath9k_hw_init_queues(ah);
2007 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2008 ath9k_hw_ani_cache_ini_regs(ah);
2009 ath9k_hw_init_qos(ah);
2011 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2012 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2014 ath9k_hw_init_global_settings(ah);
2016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
2017 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2018 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2019 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2020 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2021 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2022 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2025 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2027 ath9k_hw_set_dma(ah);
2029 if (!ath9k_hw_mci_is_enabled(ah))
2030 REG_WRITE(ah, AR_OBS, 8);
2032 if (ah->config.rx_intr_mitigation) {
2033 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2034 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2037 if (ah->config.tx_intr_mitigation) {
2038 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2039 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2042 ath9k_hw_init_bb(ah, chan);
2045 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2046 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2048 if (!ath9k_hw_init_cal(ah, chan))
2051 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2054 ENABLE_REGWRITE_BUFFER(ah);
2056 ath9k_hw_restore_chainmask(ah);
2057 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2059 REGWRITE_BUFFER_FLUSH(ah);
2061 ath9k_hw_init_desc(ah);
2063 if (ath9k_hw_btcoex_is_enabled(ah))
2064 ath9k_hw_btcoex_enable(ah);
2066 if (ath9k_hw_mci_is_enabled(ah))
2067 ar9003_mci_check_bt(ah);
2069 ath9k_hw_loadnf(ah, chan);
2070 ath9k_hw_start_nfcal(ah, true);
2072 if (AR_SREV_9300_20_OR_LATER(ah)) {
2073 ar9003_hw_bb_watchdog_config(ah);
2074 ar9003_hw_disable_phy_restart(ah);
2077 ath9k_hw_apply_gpio_override(ah);
2079 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2080 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2084 EXPORT_SYMBOL(ath9k_hw_reset);
2086 /******************************/
2087 /* Power Management (Chipset) */
2088 /******************************/
2091 * Notify Power Mgt is disabled in self-generated frames.
2092 * If requested, force chip to sleep.
2094 static void ath9k_set_power_sleep(struct ath_hw *ah)
2096 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2098 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2099 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2100 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2101 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2102 /* xxx Required for WLAN only case ? */
2103 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2108 * Clear the RTC force wake bit to allow the
2109 * mac to go to sleep.
2111 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2113 if (ath9k_hw_mci_is_enabled(ah))
2116 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2117 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2119 /* Shutdown chip. Active low */
2120 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2121 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2125 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2126 if (AR_SREV_9300_20_OR_LATER(ah))
2127 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2131 * Notify Power Management is enabled in self-generating
2132 * frames. If request, set power mode of chip to
2133 * auto/normal. Duration in units of 128us (1/8 TU).
2135 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2137 struct ath9k_hw_capabilities *pCap = &ah->caps;
2139 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2141 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2142 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2143 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2144 AR_RTC_FORCE_WAKE_ON_INT);
2147 /* When chip goes into network sleep, it could be waken
2148 * up by MCI_INT interrupt caused by BT's HW messages
2149 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2150 * rate (~100us). This will cause chip to leave and
2151 * re-enter network sleep mode frequently, which in
2152 * consequence will have WLAN MCI HW to generate lots of
2153 * SYS_WAKING and SYS_SLEEPING messages which will make
2154 * BT CPU to busy to process.
2156 if (ath9k_hw_mci_is_enabled(ah))
2157 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2158 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2160 * Clear the RTC force wake bit to allow the
2161 * mac to go to sleep.
2163 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2165 if (ath9k_hw_mci_is_enabled(ah))
2169 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2170 if (AR_SREV_9300_20_OR_LATER(ah))
2171 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2174 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2179 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2180 if (AR_SREV_9300_20_OR_LATER(ah)) {
2181 REG_WRITE(ah, AR_WA, ah->WARegVal);
2185 if ((REG_READ(ah, AR_RTC_STATUS) &
2186 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2187 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2190 if (!AR_SREV_9300_20_OR_LATER(ah))
2191 ath9k_hw_init_pll(ah, NULL);
2193 if (AR_SREV_9100(ah))
2194 REG_SET_BIT(ah, AR_RTC_RESET,
2197 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2198 AR_RTC_FORCE_WAKE_EN);
2201 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2202 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2203 if (val == AR_RTC_STATUS_ON)
2206 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2207 AR_RTC_FORCE_WAKE_EN);
2210 ath_err(ath9k_hw_common(ah),
2211 "Failed to wakeup in %uus\n",
2212 POWER_UP_TIME / 20);
2216 if (ath9k_hw_mci_is_enabled(ah))
2217 ar9003_mci_set_power_awake(ah);
2219 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2224 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2226 struct ath_common *common = ath9k_hw_common(ah);
2228 static const char *modes[] = {
2235 if (ah->power_mode == mode)
2238 ath_dbg(common, RESET, "%s -> %s\n",
2239 modes[ah->power_mode], modes[mode]);
2242 case ATH9K_PM_AWAKE:
2243 status = ath9k_hw_set_power_awake(ah);
2245 case ATH9K_PM_FULL_SLEEP:
2246 if (ath9k_hw_mci_is_enabled(ah))
2247 ar9003_mci_set_full_sleep(ah);
2249 ath9k_set_power_sleep(ah);
2250 ah->chip_fullsleep = true;
2252 case ATH9K_PM_NETWORK_SLEEP:
2253 ath9k_set_power_network_sleep(ah);
2256 ath_err(common, "Unknown power mode %u\n", mode);
2259 ah->power_mode = mode;
2262 * XXX: If this warning never comes up after a while then
2263 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2264 * ath9k_hw_setpower() return type void.
2267 if (!(ah->ah_flags & AH_UNPLUGGED))
2268 ATH_DBG_WARN_ON_ONCE(!status);
2272 EXPORT_SYMBOL(ath9k_hw_setpower);
2274 /*******************/
2275 /* Beacon Handling */
2276 /*******************/
2278 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2282 ENABLE_REGWRITE_BUFFER(ah);
2284 switch (ah->opmode) {
2285 case NL80211_IFTYPE_ADHOC:
2286 REG_SET_BIT(ah, AR_TXCFG,
2287 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2288 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2289 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2290 flags |= AR_NDP_TIMER_EN;
2291 case NL80211_IFTYPE_MESH_POINT:
2292 case NL80211_IFTYPE_AP:
2293 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2294 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2295 TU_TO_USEC(ah->config.dma_beacon_response_time));
2296 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2297 TU_TO_USEC(ah->config.sw_beacon_response_time));
2299 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2302 ath_dbg(ath9k_hw_common(ah), BEACON,
2303 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2308 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2309 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2310 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2311 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2313 REGWRITE_BUFFER_FLUSH(ah);
2315 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2317 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2319 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2320 const struct ath9k_beacon_state *bs)
2322 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2323 struct ath9k_hw_capabilities *pCap = &ah->caps;
2324 struct ath_common *common = ath9k_hw_common(ah);
2326 ENABLE_REGWRITE_BUFFER(ah);
2328 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2330 REG_WRITE(ah, AR_BEACON_PERIOD,
2331 TU_TO_USEC(bs->bs_intval));
2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2333 TU_TO_USEC(bs->bs_intval));
2335 REGWRITE_BUFFER_FLUSH(ah);
2337 REG_RMW_FIELD(ah, AR_RSSI_THR,
2338 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2340 beaconintval = bs->bs_intval;
2342 if (bs->bs_sleepduration > beaconintval)
2343 beaconintval = bs->bs_sleepduration;
2345 dtimperiod = bs->bs_dtimperiod;
2346 if (bs->bs_sleepduration > dtimperiod)
2347 dtimperiod = bs->bs_sleepduration;
2349 if (beaconintval == dtimperiod)
2350 nextTbtt = bs->bs_nextdtim;
2352 nextTbtt = bs->bs_nexttbtt;
2354 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2355 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2356 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2357 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2359 ENABLE_REGWRITE_BUFFER(ah);
2361 REG_WRITE(ah, AR_NEXT_DTIM,
2362 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2363 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2365 REG_WRITE(ah, AR_SLEEP1,
2366 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2367 | AR_SLEEP1_ASSUME_DTIM);
2369 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2370 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2372 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2374 REG_WRITE(ah, AR_SLEEP2,
2375 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2377 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2378 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2380 REGWRITE_BUFFER_FLUSH(ah);
2382 REG_SET_BIT(ah, AR_TIMER_MODE,
2383 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2386 /* TSF Out of Range Threshold */
2387 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2389 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2391 /*******************/
2392 /* HW Capabilities */
2393 /*******************/
2395 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2397 eeprom_chainmask &= chip_chainmask;
2398 if (eeprom_chainmask)
2399 return eeprom_chainmask;
2401 return chip_chainmask;
2405 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2406 * @ah: the atheros hardware data structure
2408 * We enable DFS support upstream on chipsets which have passed a series
2409 * of tests. The testing requirements are going to be documented. Desired
2410 * test requirements are documented at:
2412 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2414 * Once a new chipset gets properly tested an individual commit can be used
2415 * to document the testing for DFS for that chipset.
2417 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2420 switch (ah->hw_version.macVersion) {
2421 /* for temporary testing DFS with 9280 */
2422 case AR_SREV_VERSION_9280:
2423 /* AR9580 will likely be our first target to get testing on */
2424 case AR_SREV_VERSION_9580:
2431 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2433 struct ath9k_hw_capabilities *pCap = &ah->caps;
2434 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2435 struct ath_common *common = ath9k_hw_common(ah);
2436 unsigned int chip_chainmask;
2439 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2441 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2442 regulatory->current_rd = eeval;
2444 if (ah->opmode != NL80211_IFTYPE_AP &&
2445 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2446 if (regulatory->current_rd == 0x64 ||
2447 regulatory->current_rd == 0x65)
2448 regulatory->current_rd += 5;
2449 else if (regulatory->current_rd == 0x41)
2450 regulatory->current_rd = 0x43;
2451 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2452 regulatory->current_rd);
2455 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2456 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2458 "no band has been marked as supported in EEPROM\n");
2462 if (eeval & AR5416_OPFLAGS_11A)
2463 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2465 if (eeval & AR5416_OPFLAGS_11G)
2466 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2468 if (AR_SREV_9485(ah) ||
2473 else if (AR_SREV_9462(ah))
2475 else if (!AR_SREV_9280_20_OR_LATER(ah))
2477 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2482 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2484 * For AR9271 we will temporarilly uses the rx chainmax as read from
2487 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2488 !(eeval & AR5416_OPFLAGS_11A) &&
2489 !(AR_SREV_9271(ah)))
2490 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2491 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2492 else if (AR_SREV_9100(ah))
2493 pCap->rx_chainmask = 0x7;
2495 /* Use rx_chainmask from EEPROM. */
2496 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2498 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2499 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2500 ah->txchainmask = pCap->tx_chainmask;
2501 ah->rxchainmask = pCap->rx_chainmask;
2503 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2505 /* enable key search for every frame in an aggregate */
2506 if (AR_SREV_9300_20_OR_LATER(ah))
2507 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2509 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2511 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2512 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2514 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2516 if (AR_SREV_9271(ah))
2517 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2518 else if (AR_DEVID_7010(ah))
2519 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2520 else if (AR_SREV_9300_20_OR_LATER(ah))
2521 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2522 else if (AR_SREV_9287_11_OR_LATER(ah))
2523 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2524 else if (AR_SREV_9285_12_OR_LATER(ah))
2525 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2526 else if (AR_SREV_9280_20_OR_LATER(ah))
2527 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2529 pCap->num_gpio_pins = AR_NUM_GPIO;
2531 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2532 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2534 pCap->rts_aggr_limit = (8 * 1024);
2536 #ifdef CONFIG_ATH9K_RFKILL
2537 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2538 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2540 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2541 ah->rfkill_polarity =
2542 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2544 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2547 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2548 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2550 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2552 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2553 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2555 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2557 if (AR_SREV_9300_20_OR_LATER(ah)) {
2558 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2559 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2560 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2562 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2563 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2564 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2565 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2566 pCap->txs_len = sizeof(struct ar9003_txs);
2568 pCap->tx_desc_len = sizeof(struct ath_desc);
2569 if (AR_SREV_9280_20(ah))
2570 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2573 if (AR_SREV_9300_20_OR_LATER(ah))
2574 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2576 if (AR_SREV_9300_20_OR_LATER(ah))
2577 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2579 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2580 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2582 if (AR_SREV_9285(ah)) {
2583 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2585 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2586 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2587 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2588 ath_info(common, "Enable LNA combining\n");
2593 if (AR_SREV_9300_20_OR_LATER(ah)) {
2594 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2595 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2598 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2599 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2600 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2601 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2602 ath_info(common, "Enable LNA combining\n");
2606 if (ath9k_hw_dfs_tested(ah))
2607 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2609 tx_chainmask = pCap->tx_chainmask;
2610 rx_chainmask = pCap->rx_chainmask;
2611 while (tx_chainmask || rx_chainmask) {
2612 if (tx_chainmask & BIT(0))
2613 pCap->max_txchains++;
2614 if (rx_chainmask & BIT(0))
2615 pCap->max_rxchains++;
2621 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2622 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2623 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2625 if (AR_SREV_9462_20_OR_LATER(ah))
2626 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2629 if (AR_SREV_9462(ah))
2630 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2632 if (AR_SREV_9300_20_OR_LATER(ah) &&
2633 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2634 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2637 * Fast channel change across bands is available
2638 * only for AR9462 and AR9565.
2640 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2641 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2646 /****************************/
2647 /* GPIO / RFKILL / Antennae */
2648 /****************************/
2650 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2654 u32 gpio_shift, tmp;
2657 addr = AR_GPIO_OUTPUT_MUX3;
2659 addr = AR_GPIO_OUTPUT_MUX2;
2661 addr = AR_GPIO_OUTPUT_MUX1;
2663 gpio_shift = (gpio % 6) * 5;
2665 if (AR_SREV_9280_20_OR_LATER(ah)
2666 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2667 REG_RMW(ah, addr, (type << gpio_shift),
2668 (0x1f << gpio_shift));
2670 tmp = REG_READ(ah, addr);
2671 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2672 tmp &= ~(0x1f << gpio_shift);
2673 tmp |= (type << gpio_shift);
2674 REG_WRITE(ah, addr, tmp);
2678 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2682 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2684 if (AR_DEVID_7010(ah)) {
2686 REG_RMW(ah, AR7010_GPIO_OE,
2687 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2688 (AR7010_GPIO_OE_MASK << gpio_shift));
2692 gpio_shift = gpio << 1;
2695 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2696 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2698 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2700 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2702 #define MS_REG_READ(x, y) \
2703 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2705 if (gpio >= ah->caps.num_gpio_pins)
2708 if (AR_DEVID_7010(ah)) {
2710 val = REG_READ(ah, AR7010_GPIO_IN);
2711 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2712 } else if (AR_SREV_9300_20_OR_LATER(ah))
2713 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2714 AR_GPIO_BIT(gpio)) != 0;
2715 else if (AR_SREV_9271(ah))
2716 return MS_REG_READ(AR9271, gpio) != 0;
2717 else if (AR_SREV_9287_11_OR_LATER(ah))
2718 return MS_REG_READ(AR9287, gpio) != 0;
2719 else if (AR_SREV_9285_12_OR_LATER(ah))
2720 return MS_REG_READ(AR9285, gpio) != 0;
2721 else if (AR_SREV_9280_20_OR_LATER(ah))
2722 return MS_REG_READ(AR928X, gpio) != 0;
2724 return MS_REG_READ(AR, gpio) != 0;
2726 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2728 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2733 if (AR_DEVID_7010(ah)) {
2735 REG_RMW(ah, AR7010_GPIO_OE,
2736 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2737 (AR7010_GPIO_OE_MASK << gpio_shift));
2741 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2742 gpio_shift = 2 * gpio;
2745 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2746 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2748 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2750 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2752 if (AR_DEVID_7010(ah)) {
2754 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2759 if (AR_SREV_9271(ah))
2762 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2765 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2767 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2769 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2771 EXPORT_SYMBOL(ath9k_hw_setantenna);
2773 /*********************/
2774 /* General Operation */
2775 /*********************/
2777 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2779 u32 bits = REG_READ(ah, AR_RX_FILTER);
2780 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2782 if (phybits & AR_PHY_ERR_RADAR)
2783 bits |= ATH9K_RX_FILTER_PHYRADAR;
2784 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2785 bits |= ATH9K_RX_FILTER_PHYERR;
2789 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2791 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2795 ENABLE_REGWRITE_BUFFER(ah);
2797 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2798 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2800 REG_WRITE(ah, AR_RX_FILTER, bits);
2803 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2804 phybits |= AR_PHY_ERR_RADAR;
2805 if (bits & ATH9K_RX_FILTER_PHYERR)
2806 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2807 REG_WRITE(ah, AR_PHY_ERR, phybits);
2810 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2812 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2814 REGWRITE_BUFFER_FLUSH(ah);
2816 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2818 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2820 if (ath9k_hw_mci_is_enabled(ah))
2821 ar9003_mci_bt_gain_ctrl(ah);
2823 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2826 ath9k_hw_init_pll(ah, NULL);
2827 ah->htc_reset_init = true;
2830 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2832 bool ath9k_hw_disable(struct ath_hw *ah)
2834 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2837 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2840 ath9k_hw_init_pll(ah, NULL);
2843 EXPORT_SYMBOL(ath9k_hw_disable);
2845 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2847 enum eeprom_param gain_param;
2849 if (IS_CHAN_2GHZ(chan))
2850 gain_param = EEP_ANTENNA_GAIN_2G;
2852 gain_param = EEP_ANTENNA_GAIN_5G;
2854 return ah->eep_ops->get_eeprom(ah, gain_param);
2857 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2860 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2861 struct ieee80211_channel *channel;
2862 int chan_pwr, new_pwr, max_gain;
2863 int ant_gain, ant_reduction = 0;
2868 channel = chan->chan;
2869 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2870 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2871 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2873 ant_gain = get_antenna_gain(ah, chan);
2874 if (ant_gain > max_gain)
2875 ant_reduction = ant_gain - max_gain;
2877 ah->eep_ops->set_txpower(ah, chan,
2878 ath9k_regd_get_ctl(reg, chan),
2879 ant_reduction, new_pwr, test);
2882 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2884 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2885 struct ath9k_channel *chan = ah->curchan;
2886 struct ieee80211_channel *channel = chan->chan;
2888 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2890 channel->max_power = MAX_RATE_POWER / 2;
2892 ath9k_hw_apply_txpower(ah, chan, test);
2895 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2897 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2899 void ath9k_hw_setopmode(struct ath_hw *ah)
2901 ath9k_hw_set_operating_mode(ah, ah->opmode);
2903 EXPORT_SYMBOL(ath9k_hw_setopmode);
2905 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2907 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2908 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2910 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2912 void ath9k_hw_write_associd(struct ath_hw *ah)
2914 struct ath_common *common = ath9k_hw_common(ah);
2916 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2917 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2918 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2920 EXPORT_SYMBOL(ath9k_hw_write_associd);
2922 #define ATH9K_MAX_TSF_READ 10
2924 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2926 u32 tsf_lower, tsf_upper1, tsf_upper2;
2929 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2930 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2931 tsf_lower = REG_READ(ah, AR_TSF_L32);
2932 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2933 if (tsf_upper2 == tsf_upper1)
2935 tsf_upper1 = tsf_upper2;
2938 WARN_ON( i == ATH9K_MAX_TSF_READ );
2940 return (((u64)tsf_upper1 << 32) | tsf_lower);
2942 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2944 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2946 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2947 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2949 EXPORT_SYMBOL(ath9k_hw_settsf64);
2951 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2953 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2954 AH_TSF_WRITE_TIMEOUT))
2955 ath_dbg(ath9k_hw_common(ah), RESET,
2956 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2958 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2960 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2962 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2965 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2967 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2969 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2971 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2973 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2976 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2977 macmode = AR_2040_JOINED_RX_CLEAR;
2981 REG_WRITE(ah, AR_2040_MODE, macmode);
2984 /* HW Generic timers configuration */
2986 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2988 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2989 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2990 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2991 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2992 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2993 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2994 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2995 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2996 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2997 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2998 AR_NDP2_TIMER_MODE, 0x0002},
2999 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3000 AR_NDP2_TIMER_MODE, 0x0004},
3001 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3002 AR_NDP2_TIMER_MODE, 0x0008},
3003 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3004 AR_NDP2_TIMER_MODE, 0x0010},
3005 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3006 AR_NDP2_TIMER_MODE, 0x0020},
3007 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3008 AR_NDP2_TIMER_MODE, 0x0040},
3009 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3010 AR_NDP2_TIMER_MODE, 0x0080}
3013 /* HW generic timer primitives */
3015 /* compute and clear index of rightmost 1 */
3016 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3026 return timer_table->gen_timer_index[b];
3029 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3031 return REG_READ(ah, AR_TSF_L32);
3033 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3035 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3036 void (*trigger)(void *),
3037 void (*overflow)(void *),
3041 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3042 struct ath_gen_timer *timer;
3044 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3048 /* allocate a hardware generic timer slot */
3049 timer_table->timers[timer_index] = timer;
3050 timer->index = timer_index;
3051 timer->trigger = trigger;
3052 timer->overflow = overflow;
3057 EXPORT_SYMBOL(ath_gen_timer_alloc);
3059 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3060 struct ath_gen_timer *timer,
3064 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3065 u32 tsf, timer_next;
3067 BUG_ON(!timer_period);
3069 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3071 tsf = ath9k_hw_gettsf32(ah);
3073 timer_next = tsf + trig_timeout;
3075 ath_dbg(ath9k_hw_common(ah), BTCOEX,
3076 "current tsf %x period %x timer_next %x\n",
3077 tsf, timer_period, timer_next);
3080 * Program generic timer registers
3082 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3084 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3086 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3087 gen_tmr_configuration[timer->index].mode_mask);
3089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3091 * Starting from AR9462, each generic timer can select which tsf
3092 * to use. But we still follow the old rule, 0 - 7 use tsf and
3095 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3096 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3097 (1 << timer->index));
3099 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3100 (1 << timer->index));
3103 /* Enable both trigger and thresh interrupt masks */
3104 REG_SET_BIT(ah, AR_IMR_S5,
3105 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3106 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3108 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3110 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3112 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3114 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3115 (timer->index >= ATH_MAX_GEN_TIMER)) {
3119 /* Clear generic timer enable bits. */
3120 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3121 gen_tmr_configuration[timer->index].mode_mask);
3123 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3125 * Need to switch back to TSF if it was using TSF2.
3127 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3128 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3129 (1 << timer->index));
3133 /* Disable both trigger and thresh interrupt masks */
3134 REG_CLR_BIT(ah, AR_IMR_S5,
3135 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3136 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3138 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3140 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3142 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3144 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3146 /* free the hardware generic timer slot */
3147 timer_table->timers[timer->index] = NULL;
3150 EXPORT_SYMBOL(ath_gen_timer_free);
3153 * Generic Timer Interrupts handling
3155 void ath_gen_timer_isr(struct ath_hw *ah)
3157 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3158 struct ath_gen_timer *timer;
3159 struct ath_common *common = ath9k_hw_common(ah);
3160 u32 trigger_mask, thresh_mask, index;
3162 /* get hardware generic timer interrupt status */
3163 trigger_mask = ah->intr_gen_timer_trigger;
3164 thresh_mask = ah->intr_gen_timer_thresh;
3165 trigger_mask &= timer_table->timer_mask.val;
3166 thresh_mask &= timer_table->timer_mask.val;
3168 trigger_mask &= ~thresh_mask;
3170 while (thresh_mask) {
3171 index = rightmost_index(timer_table, &thresh_mask);
3172 timer = timer_table->timers[index];
3174 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
3176 timer->overflow(timer->arg);
3179 while (trigger_mask) {
3180 index = rightmost_index(timer_table, &trigger_mask);
3181 timer = timer_table->timers[index];
3183 ath_dbg(common, BTCOEX,
3184 "Gen timer[%d] trigger\n", index);
3185 timer->trigger(timer->arg);
3188 EXPORT_SYMBOL(ath_gen_timer_isr);
3197 } ath_mac_bb_names[] = {
3198 /* Devices with external radios */
3199 { AR_SREV_VERSION_5416_PCI, "5416" },
3200 { AR_SREV_VERSION_5416_PCIE, "5418" },
3201 { AR_SREV_VERSION_9100, "9100" },
3202 { AR_SREV_VERSION_9160, "9160" },
3203 /* Single-chip solutions */
3204 { AR_SREV_VERSION_9280, "9280" },
3205 { AR_SREV_VERSION_9285, "9285" },
3206 { AR_SREV_VERSION_9287, "9287" },
3207 { AR_SREV_VERSION_9271, "9271" },
3208 { AR_SREV_VERSION_9300, "9300" },
3209 { AR_SREV_VERSION_9330, "9330" },
3210 { AR_SREV_VERSION_9340, "9340" },
3211 { AR_SREV_VERSION_9485, "9485" },
3212 { AR_SREV_VERSION_9462, "9462" },
3213 { AR_SREV_VERSION_9550, "9550" },
3214 { AR_SREV_VERSION_9565, "9565" },
3217 /* For devices with external radios */
3221 } ath_rf_names[] = {
3223 { AR_RAD5133_SREV_MAJOR, "5133" },
3224 { AR_RAD5122_SREV_MAJOR, "5122" },
3225 { AR_RAD2133_SREV_MAJOR, "2133" },
3226 { AR_RAD2122_SREV_MAJOR, "2122" }
3230 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3232 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3236 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3237 if (ath_mac_bb_names[i].version == mac_bb_version) {
3238 return ath_mac_bb_names[i].name;
3246 * Return the RF name. "????" is returned if the RF is unknown.
3247 * Used for devices with external radios.
3249 static const char *ath9k_hw_rf_name(u16 rf_version)
3253 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3254 if (ath_rf_names[i].version == rf_version) {
3255 return ath_rf_names[i].name;
3262 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3266 /* chipsets >= AR9280 are single-chip */
3267 if (AR_SREV_9280_20_OR_LATER(ah)) {
3268 used = scnprintf(hw_name, len,
3269 "Atheros AR%s Rev:%x",
3270 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3271 ah->hw_version.macRev);
3274 used = scnprintf(hw_name, len,
3275 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3276 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3277 ah->hw_version.macRev,
3278 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3279 & AR_RADIO_SREV_MAJOR)),
3280 ah->hw_version.phyRev);
3283 hw_name[used] = '\0';
3285 EXPORT_SYMBOL(ath9k_hw_name);