2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
44 #define AR5416_AR9100_DEVID 0x000b
46 #define AR9271_USB 0x9271
48 #define AR_SUBVENDOR_ID_NOG 0x0e11
49 #define AR_SUBVENDOR_ID_NEW_A 0x7065
50 #define AR5416_MAGIC 0x19641014
52 #define AR5416_DEVID_AR9287_PCI 0x002D
53 #define AR5416_DEVID_AR9287_PCIE 0x002E
55 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
56 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
59 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
61 #define ATH_DEFAULT_NOISE_FLOOR -95
63 #define ATH9K_RSSI_BAD 0x80
65 /* Register read/write primitives */
66 #define REG_WRITE(_ah, _reg, _val) \
67 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69 #define REG_READ(_ah, _reg) \
70 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
72 #define SM(_v, _f) (((_v) << _f##_S) & _f)
73 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
74 #define REG_RMW(_a, _r, _set, _clr) \
75 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
76 #define REG_RMW_FIELD(_a, _r, _f, _v) \
78 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
79 #define REG_SET_BIT(_a, _r, _f) \
80 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
81 #define REG_CLR_BIT(_a, _r, _f) \
82 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
84 #define DO_DELAY(x) do { \
85 if ((++(x) % 64) == 0) \
89 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
91 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
92 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
93 INI_RA((iniarray), r, (column))); \
98 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
100 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
101 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
102 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
104 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
106 #define AR_GPIOD_MASK 0x00001FFF
107 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
109 #define BASE_ACTIVATE_DELAY 100
110 #define RTC_PLL_SETTLE_DELAY 100
111 #define COEF_SCALE_S 24
112 #define HT40_CHANNEL_CENTER_SHIFT 10
114 #define ATH9K_ANTENNA0_CHAINMASK 0x1
115 #define ATH9K_ANTENNA1_CHAINMASK 0x2
117 #define ATH9K_NUM_DMA_DEBUG_REGS 8
118 #define ATH9K_NUM_QUEUES 10
120 #define MAX_RATE_POWER 63
121 #define AH_WAIT_TIMEOUT 100000 /* (us) */
122 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
123 #define AH_TIME_QUANTUM 10
124 #define AR_KEYTABLE_SIZE 128
125 #define POWER_UP_TIME 10000
126 #define SPUR_RSSI_THRESH 40
128 #define CAB_TIMEOUT_VAL 10
129 #define BEACON_TIMEOUT_VAL 10
130 #define MIN_BEACON_TIMEOUT_VAL 1
133 #define INIT_CONFIG_STATUS 0x00000000
134 #define INIT_RSSI_THR 0x00000700
135 #define INIT_BCON_CNTRL_REG 0x00000000
137 #define TU_TO_USEC(_tu) ((_tu) << 10)
142 ATH9K_MODE_11NA_HT20,
143 ATH9K_MODE_11NG_HT20,
144 ATH9K_MODE_11NA_HT40PLUS,
145 ATH9K_MODE_11NA_HT40MINUS,
146 ATH9K_MODE_11NG_HT40PLUS,
147 ATH9K_MODE_11NG_HT40MINUS,
152 * ath9k_ant_setting - transmit antenna settings
154 * Configures the antenna setting to use for transmit.
156 * @ATH9K_ANT_VARIABLE: this means transmit on all active antennas
157 * @ATH9K_ANT_FIXED_A: this means transmit on the first antenna only
158 * @ATH9K_ANT_FIXED_B: this means transmit on the second antenna only
160 enum ath9k_ant_setting {
161 ATH9K_ANT_VARIABLE = 0,
167 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
168 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
169 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
170 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
171 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
172 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
173 ATH9K_HW_CAP_VEOL = BIT(6),
174 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
175 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
176 ATH9K_HW_CAP_HT = BIT(9),
177 ATH9K_HW_CAP_GTT = BIT(10),
178 ATH9K_HW_CAP_FASTCC = BIT(11),
179 ATH9K_HW_CAP_RFSILENT = BIT(12),
180 ATH9K_HW_CAP_CST = BIT(13),
181 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
182 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
183 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
186 enum ath9k_capability_type {
187 ATH9K_CAP_CIPHER = 0,
189 ATH9K_CAP_TKIP_SPLIT,
192 ATH9K_CAP_MCAST_KEYSRCH,
196 struct ath9k_hw_capabilities {
197 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
198 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
201 u16 low_5ghz_chan, high_5ghz_chan;
202 u16 low_2ghz_chan, high_2ghz_chan;
206 u16 tx_triglevel_max;
213 struct ath9k_ops_config {
214 int dma_beacon_response_time;
215 int sw_beacon_response_time;
216 int additional_swba_backoff;
218 int cwm_ignore_extcca;
219 u8 pcie_powersave_enable;
229 enum ath9k_ant_setting diversity_control;
230 u16 antenna_switch_swap;
231 int serialize_regmode;
232 bool intr_mitigation;
233 #define SPUR_DISABLE 0
234 #define SPUR_ENABLE_IOCTL 1
235 #define SPUR_ENABLE_EEPROM 2
236 #define AR_EEPROM_MODAL_SPURS 5
237 #define AR_SPUR_5413_1 1640
238 #define AR_SPUR_5413_2 1200
239 #define AR_NO_SPUR 0x8000
240 #define AR_BASE_FREQ_2GHZ 2300
241 #define AR_BASE_FREQ_5GHZ 4900
242 #define AR_SPUR_FEEQ_BOUND_HT40 19
243 #define AR_SPUR_FEEQ_BOUND_HT20 10
245 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
249 ATH9K_INT_RX = 0x00000001,
250 ATH9K_INT_RXDESC = 0x00000002,
251 ATH9K_INT_RXNOFRM = 0x00000008,
252 ATH9K_INT_RXEOL = 0x00000010,
253 ATH9K_INT_RXORN = 0x00000020,
254 ATH9K_INT_TX = 0x00000040,
255 ATH9K_INT_TXDESC = 0x00000080,
256 ATH9K_INT_TIM_TIMER = 0x00000100,
257 ATH9K_INT_TXURN = 0x00000800,
258 ATH9K_INT_MIB = 0x00001000,
259 ATH9K_INT_RXPHY = 0x00004000,
260 ATH9K_INT_RXKCM = 0x00008000,
261 ATH9K_INT_SWBA = 0x00010000,
262 ATH9K_INT_BMISS = 0x00040000,
263 ATH9K_INT_BNR = 0x00100000,
264 ATH9K_INT_TIM = 0x00200000,
265 ATH9K_INT_DTIM = 0x00400000,
266 ATH9K_INT_DTIMSYNC = 0x00800000,
267 ATH9K_INT_GPIO = 0x01000000,
268 ATH9K_INT_CABEND = 0x02000000,
269 ATH9K_INT_TSFOOR = 0x04000000,
270 ATH9K_INT_GENTIMER = 0x08000000,
271 ATH9K_INT_CST = 0x10000000,
272 ATH9K_INT_GTT = 0x20000000,
273 ATH9K_INT_FATAL = 0x40000000,
274 ATH9K_INT_GLOBAL = 0x80000000,
275 ATH9K_INT_BMISC = ATH9K_INT_TIM |
280 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
292 ATH9K_INT_NOCARD = 0xffffffff
295 #define CHANNEL_CW_INT 0x00002
296 #define CHANNEL_CCK 0x00020
297 #define CHANNEL_OFDM 0x00040
298 #define CHANNEL_2GHZ 0x00080
299 #define CHANNEL_5GHZ 0x00100
300 #define CHANNEL_PASSIVE 0x00200
301 #define CHANNEL_DYN 0x00400
302 #define CHANNEL_HALF 0x04000
303 #define CHANNEL_QUARTER 0x08000
304 #define CHANNEL_HT20 0x10000
305 #define CHANNEL_HT40PLUS 0x20000
306 #define CHANNEL_HT40MINUS 0x40000
308 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
309 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
310 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
311 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
312 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
313 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
314 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
315 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
316 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
317 #define CHANNEL_ALL \
326 struct ath9k_channel {
327 struct ieee80211_channel *chan;
332 bool oneTimeCalsDone;
335 int16_t rawNoiseFloor;
338 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
339 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
340 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
341 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
342 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
343 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
344 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
345 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
346 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
347 #define IS_CHAN_A_5MHZ_SPACED(_c) \
348 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
349 (((_c)->channel % 20) != 0) && \
350 (((_c)->channel % 10) != 0))
352 /* These macros check chanmode and not channelFlags */
353 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
354 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
355 ((_c)->chanmode == CHANNEL_G_HT20))
356 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
357 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
358 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
359 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
360 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
362 enum ath9k_power_mode {
365 ATH9K_PM_NETWORK_SLEEP,
369 enum ath9k_tp_scale {
370 ATH9K_TP_SCALE_MAX = 0,
378 SER_REG_MODE_OFF = 0,
380 SER_REG_MODE_AUTO = 2,
383 struct ath9k_beacon_state {
387 #define ATH9K_BEACON_PERIOD 0x0000ffff
388 #define ATH9K_BEACON_ENA 0x00800000
389 #define ATH9K_BEACON_RESET_TSF 0x01000000
390 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
393 u16 bs_cfpmaxduration;
396 u16 bs_bmissthreshold;
397 u32 bs_sleepduration;
398 u32 bs_tsfoor_threshold;
401 struct chan_centers {
408 ATH9K_RESET_POWER_ON,
413 struct ath9k_hw_version {
425 /* Generic TSF timer definitions */
427 #define ATH_MAX_GEN_TIMER 16
429 #define AR_GENTMR_BIT(_index) (1 << (_index))
432 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
433 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
435 #define debruijn32 0x077CB531UL
437 struct ath_gen_timer_configuration {
444 struct ath_gen_timer {
445 void (*trigger)(void *arg);
446 void (*overflow)(void *arg);
451 struct ath_gen_timer_table {
452 u32 gen_timer_index[32];
453 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
455 unsigned long timer_bits;
461 struct ieee80211_hw *hw;
462 struct ath_common common;
463 struct ath9k_hw_version hw_version;
464 struct ath9k_ops_config config;
465 struct ath9k_hw_capabilities caps;
466 struct ath9k_channel channels[38];
467 struct ath9k_channel *curchan;
470 struct ar5416_eeprom_def def;
471 struct ar5416_eeprom_4k map4k;
472 struct ar9287_eeprom map9287;
474 const struct eeprom_ops *eep_ops;
475 enum ath9k_eep_map eep_map;
487 enum nl80211_iftype opmode;
488 enum ath9k_power_mode power_mode;
490 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
491 struct ath9k_pacal_info pacal_info;
492 struct ar5416Stats stats;
493 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
495 int16_t curchan_rad_index;
497 u32 txok_interrupt_mask;
498 u32 txerr_interrupt_mask;
499 u32 txdesc_interrupt_mask;
500 u32 txeol_interrupt_mask;
501 u32 txurn_interrupt_mask;
506 enum ath9k_cal_types supp_cals;
507 struct ath9k_cal_list iq_caldata;
508 struct ath9k_cal_list adcgain_caldata;
509 struct ath9k_cal_list adcdc_calinitdata;
510 struct ath9k_cal_list adcdc_caldata;
511 struct ath9k_cal_list *cal_list;
512 struct ath9k_cal_list *cal_list_last;
513 struct ath9k_cal_list *cal_list_curr;
514 #define totalPowerMeasI meas0.unsign
515 #define totalPowerMeasQ meas1.unsign
516 #define totalIqCorrMeas meas2.sign
517 #define totalAdcIOddPhase meas0.unsign
518 #define totalAdcIEvenPhase meas1.unsign
519 #define totalAdcQOddPhase meas2.unsign
520 #define totalAdcQEvenPhase meas3.unsign
521 #define totalAdcDcOffsetIOddPhase meas0.sign
522 #define totalAdcDcOffsetIEvenPhase meas1.sign
523 #define totalAdcDcOffsetQOddPhase meas2.sign
524 #define totalAdcDcOffsetQEvenPhase meas3.sign
526 u32 unsign[AR5416_MAX_CHAINS];
527 int32_t sign[AR5416_MAX_CHAINS];
530 u32 unsign[AR5416_MAX_CHAINS];
531 int32_t sign[AR5416_MAX_CHAINS];
534 u32 unsign[AR5416_MAX_CHAINS];
535 int32_t sign[AR5416_MAX_CHAINS];
538 u32 unsign[AR5416_MAX_CHAINS];
539 int32_t sign[AR5416_MAX_CHAINS];
543 u32 sta_id1_defaults;
549 } enable_32kHz_clock;
551 /* Callback for radio frequency change */
552 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
554 /* Callback for baseband spur frequency */
555 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
556 struct ath9k_channel *chan);
558 /* Used to program the radio on non single-chip devices */
559 u32 *analogBank0Data;
560 u32 *analogBank1Data;
561 u32 *analogBank2Data;
562 u32 *analogBank3Data;
563 u32 *analogBank6Data;
564 u32 *analogBank6TPCData;
565 u32 *analogBank7Data;
569 int16_t txpower_indexoffset;
580 struct ar5416AniState *curani;
581 struct ar5416AniState ani[255];
582 int totalSizeDesired[5];
586 enum ath9k_ani_cmd ani_function;
588 /* Bluetooth coexistance */
589 struct ath_btcoex_hw btcoex_hw;
595 u32 originalGain[22];
600 struct ar5416IniArray iniModes;
601 struct ar5416IniArray iniCommon;
602 struct ar5416IniArray iniBank0;
603 struct ar5416IniArray iniBB_RfGain;
604 struct ar5416IniArray iniBank1;
605 struct ar5416IniArray iniBank2;
606 struct ar5416IniArray iniBank3;
607 struct ar5416IniArray iniBank6;
608 struct ar5416IniArray iniBank6TPC;
609 struct ar5416IniArray iniBank7;
610 struct ar5416IniArray iniAddac;
611 struct ar5416IniArray iniPcieSerdes;
612 struct ar5416IniArray iniModesAdditional;
613 struct ar5416IniArray iniModesRxGain;
614 struct ar5416IniArray iniModesTxGain;
615 struct ar5416IniArray iniModes_9271_1_0_only;
616 struct ar5416IniArray iniCckfirNormal;
617 struct ar5416IniArray iniCckfirJapan2484;
619 u32 intr_gen_timer_trigger;
620 u32 intr_gen_timer_thresh;
621 struct ath_gen_timer_table hw_gen_timers;
624 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
629 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
631 return &(ath9k_hw_common(ah)->regulatory);
634 /* Initialization, Detach, Reset */
635 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
636 void ath9k_hw_detach(struct ath_hw *ah);
637 int ath9k_hw_init(struct ath_hw *ah);
638 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
639 bool bChannelChange);
640 void ath9k_hw_fill_cap_info(struct ath_hw *ah);
641 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
642 u32 capability, u32 *result);
643 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
644 u32 capability, u32 setting, int *status);
646 /* Key Cache Management */
647 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
648 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
649 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
650 const struct ath9k_keyval *k,
652 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
654 /* GPIO / RFKILL / Antennae */
655 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
656 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
657 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
659 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
660 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
661 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
662 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
663 enum ath9k_ant_setting settings,
664 struct ath9k_channel *chan,
665 u8 *tx_chainmask, u8 *rx_chainmask,
668 /* General Operation */
669 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
670 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
671 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
672 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
673 const struct ath_rate_table *rates,
674 u32 frameLen, u16 rateix, bool shortPreamble);
675 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
676 struct ath9k_channel *chan,
677 struct chan_centers *centers);
678 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
679 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
680 bool ath9k_hw_phy_disable(struct ath_hw *ah);
681 bool ath9k_hw_disable(struct ath_hw *ah);
682 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
683 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
684 void ath9k_hw_setopmode(struct ath_hw *ah);
685 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
686 void ath9k_hw_setbssidmask(struct ath_hw *ah);
687 void ath9k_hw_write_associd(struct ath_hw *ah);
688 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
689 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
690 void ath9k_hw_reset_tsf(struct ath_hw *ah);
691 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
692 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
693 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
694 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
695 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
696 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
697 const struct ath9k_beacon_state *bs);
699 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
701 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
703 /* Interrupt Handling */
704 bool ath9k_hw_intrpend(struct ath_hw *ah);
705 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
706 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
708 /* Generic hw timer primitives */
709 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
710 void (*trigger)(void *),
711 void (*overflow)(void *),
714 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
715 struct ath_gen_timer *timer,
718 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
720 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
721 void ath_gen_timer_isr(struct ath_hw *hw);
722 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
724 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
726 #define ATH_PCIE_CAP_LINK_CTRL 0x70
727 #define ATH_PCIE_CAP_LINK_L0S 1
728 #define ATH_PCIE_CAP_LINK_L1 2