2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR5416_AR9100_DEVID 0x000b
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 #define ATH9K_NUM_CHANNELS 38
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 (_ah)->reg_ops.write((_ah), (_val), (_reg))
70 #define REG_READ(_ah, _reg) \
71 (_ah)->reg_ops.read((_ah), (_reg))
73 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
74 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
76 #define REG_RMW(_ah, _reg, _set, _clr) \
77 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
79 #define ENABLE_REGWRITE_BUFFER(_ah) \
81 if ((_ah)->reg_ops.enable_write_buffer) \
82 (_ah)->reg_ops.enable_write_buffer((_ah)); \
85 #define REGWRITE_BUFFER_FLUSH(_ah) \
87 if ((_ah)->reg_ops.write_flush) \
88 (_ah)->reg_ops.write_flush((_ah)); \
91 #define SM(_v, _f) (((_v) << _f##_S) & _f)
92 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
93 #define REG_RMW_FIELD(_a, _r, _f, _v) \
94 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
95 #define REG_READ_FIELD(_a, _r, _f) \
96 (((REG_READ(_a, _r) & _f) >> _f##_S))
97 #define REG_SET_BIT(_a, _r, _f) \
98 REG_RMW(_a, _r, (_f), 0)
99 #define REG_CLR_BIT(_a, _r, _f) \
100 REG_RMW(_a, _r, 0, (_f))
102 #define DO_DELAY(x) do { \
103 if (((++(x) % 64) == 0) && \
104 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
109 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
110 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
112 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
113 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
114 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
115 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
116 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
117 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
118 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
120 #define AR_GPIOD_MASK 0x00001FFF
121 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
123 #define BASE_ACTIVATE_DELAY 100
124 #define RTC_PLL_SETTLE_DELAY 100
125 #define COEF_SCALE_S 24
126 #define HT40_CHANNEL_CENTER_SHIFT 10
128 #define ATH9K_ANTENNA0_CHAINMASK 0x1
129 #define ATH9K_ANTENNA1_CHAINMASK 0x2
131 #define ATH9K_NUM_DMA_DEBUG_REGS 8
132 #define ATH9K_NUM_QUEUES 10
134 #define MAX_RATE_POWER 63
135 #define AH_WAIT_TIMEOUT 100000 /* (us) */
136 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
137 #define AH_TIME_QUANTUM 10
138 #define AR_KEYTABLE_SIZE 128
139 #define POWER_UP_TIME 10000
140 #define SPUR_RSSI_THRESH 40
142 #define CAB_TIMEOUT_VAL 10
143 #define BEACON_TIMEOUT_VAL 10
144 #define MIN_BEACON_TIMEOUT_VAL 1
147 #define INIT_CONFIG_STATUS 0x00000000
148 #define INIT_RSSI_THR 0x00000700
149 #define INIT_BCON_CNTRL_REG 0x00000000
151 #define TU_TO_USEC(_tu) ((_tu) << 10)
153 #define ATH9K_HW_RX_HP_QDEPTH 16
154 #define ATH9K_HW_RX_LP_QDEPTH 128
156 #define PAPRD_GAIN_TABLE_ENTRIES 32
157 #define PAPRD_TABLE_SZ 24
159 enum ath_hw_txq_subtype {
166 enum ath_ini_subsys {
174 ATH9K_HW_CAP_HT = BIT(0),
175 ATH9K_HW_CAP_RFSILENT = BIT(1),
176 ATH9K_HW_CAP_CST = BIT(2),
177 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
178 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
179 ATH9K_HW_CAP_EDMA = BIT(6),
180 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
181 ATH9K_HW_CAP_LDPC = BIT(8),
182 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
183 ATH9K_HW_CAP_SGI_20 = BIT(10),
184 ATH9K_HW_CAP_PAPRD = BIT(11),
185 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
186 ATH9K_HW_CAP_2GHZ = BIT(13),
187 ATH9K_HW_CAP_5GHZ = BIT(14),
188 ATH9K_HW_CAP_APM = BIT(15),
191 struct ath9k_hw_capabilities {
192 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
205 bool pcie_lcr_extsync_en;
208 struct ath9k_ops_config {
209 int dma_beacon_response_time;
210 int sw_beacon_response_time;
211 int additional_swba_backoff;
213 u32 cwm_ignore_extcca;
214 u8 pcie_powersave_enable;
215 bool pcieSerDesWrite;
225 int serialize_regmode;
226 bool rx_intr_mitigation;
227 bool tx_intr_mitigation;
228 #define SPUR_DISABLE 0
229 #define SPUR_ENABLE_IOCTL 1
230 #define SPUR_ENABLE_EEPROM 2
231 #define AR_SPUR_5413_1 1640
232 #define AR_SPUR_5413_2 1200
233 #define AR_NO_SPUR 0x8000
234 #define AR_BASE_FREQ_2GHZ 2300
235 #define AR_BASE_FREQ_5GHZ 4900
236 #define AR_SPUR_FEEQ_BOUND_HT40 19
237 #define AR_SPUR_FEEQ_BOUND_HT20 10
239 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
241 u16 ani_poll_interval; /* ANI poll interval in ms */
245 ATH9K_INT_RX = 0x00000001,
246 ATH9K_INT_RXDESC = 0x00000002,
247 ATH9K_INT_RXHP = 0x00000001,
248 ATH9K_INT_RXLP = 0x00000002,
249 ATH9K_INT_RXNOFRM = 0x00000008,
250 ATH9K_INT_RXEOL = 0x00000010,
251 ATH9K_INT_RXORN = 0x00000020,
252 ATH9K_INT_TX = 0x00000040,
253 ATH9K_INT_TXDESC = 0x00000080,
254 ATH9K_INT_TIM_TIMER = 0x00000100,
255 ATH9K_INT_BB_WATCHDOG = 0x00000400,
256 ATH9K_INT_TXURN = 0x00000800,
257 ATH9K_INT_MIB = 0x00001000,
258 ATH9K_INT_RXPHY = 0x00004000,
259 ATH9K_INT_RXKCM = 0x00008000,
260 ATH9K_INT_SWBA = 0x00010000,
261 ATH9K_INT_BMISS = 0x00040000,
262 ATH9K_INT_BNR = 0x00100000,
263 ATH9K_INT_TIM = 0x00200000,
264 ATH9K_INT_DTIM = 0x00400000,
265 ATH9K_INT_DTIMSYNC = 0x00800000,
266 ATH9K_INT_GPIO = 0x01000000,
267 ATH9K_INT_CABEND = 0x02000000,
268 ATH9K_INT_TSFOOR = 0x04000000,
269 ATH9K_INT_GENTIMER = 0x08000000,
270 ATH9K_INT_CST = 0x10000000,
271 ATH9K_INT_GTT = 0x20000000,
272 ATH9K_INT_FATAL = 0x40000000,
273 ATH9K_INT_GLOBAL = 0x80000000,
274 ATH9K_INT_BMISC = ATH9K_INT_TIM |
279 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
291 ATH9K_INT_NOCARD = 0xffffffff
294 #define CHANNEL_CW_INT 0x00002
295 #define CHANNEL_CCK 0x00020
296 #define CHANNEL_OFDM 0x00040
297 #define CHANNEL_2GHZ 0x00080
298 #define CHANNEL_5GHZ 0x00100
299 #define CHANNEL_PASSIVE 0x00200
300 #define CHANNEL_DYN 0x00400
301 #define CHANNEL_HALF 0x04000
302 #define CHANNEL_QUARTER 0x08000
303 #define CHANNEL_HT20 0x10000
304 #define CHANNEL_HT40PLUS 0x20000
305 #define CHANNEL_HT40MINUS 0x40000
307 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
308 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
309 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
310 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
311 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
312 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
313 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
314 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
315 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
316 #define CHANNEL_ALL \
325 struct ath9k_hw_cal_data {
333 bool nfcal_interference;
334 u16 small_signal_gain[AR9300_MAX_CHAINS];
335 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
336 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
339 struct ath9k_channel {
340 struct ieee80211_channel *chan;
341 struct ar5416AniState ani;
348 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
349 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
350 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
351 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
352 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
353 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
354 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
355 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
356 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
357 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
358 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
359 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
361 /* These macros check chanmode and not channelFlags */
362 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
363 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
364 ((_c)->chanmode == CHANNEL_G_HT20))
365 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
366 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
367 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
368 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
369 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
371 enum ath9k_power_mode {
374 ATH9K_PM_NETWORK_SLEEP,
378 enum ath9k_tp_scale {
379 ATH9K_TP_SCALE_MAX = 0,
387 SER_REG_MODE_OFF = 0,
389 SER_REG_MODE_AUTO = 2,
392 enum ath9k_rx_qtype {
398 struct ath9k_beacon_state {
402 #define ATH9K_BEACON_PERIOD 0x0000ffff
403 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
406 u16 bs_cfpmaxduration;
409 u16 bs_bmissthreshold;
410 u32 bs_sleepduration;
411 u32 bs_tsfoor_threshold;
414 struct chan_centers {
421 ATH9K_RESET_POWER_ON,
426 struct ath9k_hw_version {
436 enum ath_usb_dev usbdev;
439 /* Generic TSF timer definitions */
441 #define ATH_MAX_GEN_TIMER 16
443 #define AR_GENTMR_BIT(_index) (1 << (_index))
446 * Using de Bruijin sequence to look up 1's index in a 32 bit number
447 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
449 #define debruijn32 0x077CB531U
451 struct ath_gen_timer_configuration {
458 struct ath_gen_timer {
459 void (*trigger)(void *arg);
460 void (*overflow)(void *arg);
465 struct ath_gen_timer_table {
466 u32 gen_timer_index[32];
467 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
469 unsigned long timer_bits;
474 struct ath_hw_antcomb_conf {
481 * struct ath_hw_radar_conf - radar detection initialization parameters
483 * @pulse_inband: threshold for checking the ratio of in-band power
484 * to total power for short radar pulses (half dB steps)
485 * @pulse_inband_step: threshold for checking an in-band power to total
486 * power ratio increase for short radar pulses (half dB steps)
487 * @pulse_height: threshold for detecting the beginning of a short
488 * radar pulse (dB step)
489 * @pulse_rssi: threshold for detecting if a short radar pulse is
491 * @pulse_maxlen: maximum pulse length (0.8 us steps)
493 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
494 * @radar_inband: threshold for checking the ratio of in-band power
495 * to total power for long radar pulses (half dB steps)
496 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
498 * @ext_channel: enable extension channel radar detection
500 struct ath_hw_radar_conf {
501 unsigned int pulse_inband;
502 unsigned int pulse_inband_step;
503 unsigned int pulse_height;
504 unsigned int pulse_rssi;
505 unsigned int pulse_maxlen;
507 unsigned int radar_rssi;
508 unsigned int radar_inband;
515 * struct ath_hw_private_ops - callbacks used internally by hardware code
517 * This structure contains private callbacks designed to only be used internally
518 * by the hardware core.
520 * @init_cal_settings: setup types of calibrations supported
521 * @init_cal: starts actual calibration
523 * @init_mode_regs: Initializes mode registers
524 * @init_mode_gain_regs: Initialize TX/RX gain registers
526 * @rf_set_freq: change frequency
527 * @spur_mitigate_freq: spur mitigation
528 * @rf_alloc_ext_banks:
529 * @rf_free_ext_banks:
531 * @compute_pll_control: compute the PLL control value to use for
532 * AR_RTC_PLL_CONTROL for a given channel
533 * @setup_calibration: set up calibration
534 * @iscal_supported: used to query if a type of calibration is supported
536 * @ani_cache_ini_regs: cache the values for ANI from the initial
537 * register settings through the register initialization.
539 struct ath_hw_private_ops {
540 /* Calibration ops */
541 void (*init_cal_settings)(struct ath_hw *ah);
542 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
544 void (*init_mode_regs)(struct ath_hw *ah);
545 void (*init_mode_gain_regs)(struct ath_hw *ah);
546 void (*setup_calibration)(struct ath_hw *ah,
547 struct ath9k_cal_list *currCal);
550 int (*rf_set_freq)(struct ath_hw *ah,
551 struct ath9k_channel *chan);
552 void (*spur_mitigate_freq)(struct ath_hw *ah,
553 struct ath9k_channel *chan);
554 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
555 void (*rf_free_ext_banks)(struct ath_hw *ah);
556 bool (*set_rf_regs)(struct ath_hw *ah,
557 struct ath9k_channel *chan,
559 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
560 void (*init_bb)(struct ath_hw *ah,
561 struct ath9k_channel *chan);
562 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
563 void (*olc_init)(struct ath_hw *ah);
564 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
565 void (*mark_phy_inactive)(struct ath_hw *ah);
566 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
567 bool (*rfbus_req)(struct ath_hw *ah);
568 void (*rfbus_done)(struct ath_hw *ah);
569 void (*restore_chainmask)(struct ath_hw *ah);
570 void (*set_diversity)(struct ath_hw *ah, bool value);
571 u32 (*compute_pll_control)(struct ath_hw *ah,
572 struct ath9k_channel *chan);
573 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
575 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
576 void (*set_radar_params)(struct ath_hw *ah,
577 struct ath_hw_radar_conf *conf);
580 void (*ani_cache_ini_regs)(struct ath_hw *ah);
584 * struct ath_hw_ops - callbacks used by hardware code and driver code
586 * This structure contains callbacks designed to to be used internally by
587 * hardware code and also by the lower level driver.
589 * @config_pci_powersave:
590 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
593 void (*config_pci_powersave)(struct ath_hw *ah,
596 void (*rx_enable)(struct ath_hw *ah);
597 void (*set_desc_link)(void *ds, u32 link);
598 void (*get_desc_link)(void *ds, u32 **link);
599 bool (*calibrate)(struct ath_hw *ah,
600 struct ath9k_channel *chan,
603 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
604 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
605 bool is_firstseg, bool is_is_lastseg,
606 const void *ds0, dma_addr_t buf_addr,
608 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
609 struct ath_tx_status *ts);
610 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
611 u32 pktLen, enum ath9k_pkt_type type,
612 u32 txPower, u32 keyIx,
613 enum ath9k_key_type keyType,
615 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
617 u32 durUpdateEn, u32 rtsctsRate,
619 struct ath9k_11n_rate_series series[],
620 u32 nseries, u32 flags);
621 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
623 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
625 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
626 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
627 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
631 struct ath_nf_limits {
638 #define AH_USE_EEPROM 0x1
639 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
642 struct ath_ops reg_ops;
644 struct ieee80211_hw *hw;
645 struct ath_common common;
646 struct ath9k_hw_version hw_version;
647 struct ath9k_ops_config config;
648 struct ath9k_hw_capabilities caps;
649 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
650 struct ath9k_channel *curchan;
653 struct ar5416_eeprom_def def;
654 struct ar5416_eeprom_4k map4k;
655 struct ar9287_eeprom map9287;
656 struct ar9300_eeprom ar9300_eep;
658 const struct eeprom_ops *eep_ops;
663 bool need_an_top2_fixup;
667 struct ath_nf_limits nf_2g;
668 struct ath_nf_limits nf_5g;
676 enum nl80211_iftype opmode;
677 enum ath9k_power_mode power_mode;
679 struct ath9k_hw_cal_data *caldata;
680 struct ath9k_pacal_info pacal_info;
681 struct ar5416Stats stats;
682 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
684 int16_t curchan_rad_index;
685 enum ath9k_int imask;
687 u32 txok_interrupt_mask;
688 u32 txerr_interrupt_mask;
689 u32 txdesc_interrupt_mask;
690 u32 txeol_interrupt_mask;
691 u32 txurn_interrupt_mask;
697 struct ath9k_cal_list iq_caldata;
698 struct ath9k_cal_list adcgain_caldata;
699 struct ath9k_cal_list adcdc_caldata;
700 struct ath9k_cal_list tempCompCalData;
701 struct ath9k_cal_list *cal_list;
702 struct ath9k_cal_list *cal_list_last;
703 struct ath9k_cal_list *cal_list_curr;
704 #define totalPowerMeasI meas0.unsign
705 #define totalPowerMeasQ meas1.unsign
706 #define totalIqCorrMeas meas2.sign
707 #define totalAdcIOddPhase meas0.unsign
708 #define totalAdcIEvenPhase meas1.unsign
709 #define totalAdcQOddPhase meas2.unsign
710 #define totalAdcQEvenPhase meas3.unsign
711 #define totalAdcDcOffsetIOddPhase meas0.sign
712 #define totalAdcDcOffsetIEvenPhase meas1.sign
713 #define totalAdcDcOffsetQOddPhase meas2.sign
714 #define totalAdcDcOffsetQEvenPhase meas3.sign
716 u32 unsign[AR5416_MAX_CHAINS];
717 int32_t sign[AR5416_MAX_CHAINS];
720 u32 unsign[AR5416_MAX_CHAINS];
721 int32_t sign[AR5416_MAX_CHAINS];
724 u32 unsign[AR5416_MAX_CHAINS];
725 int32_t sign[AR5416_MAX_CHAINS];
728 u32 unsign[AR5416_MAX_CHAINS];
729 int32_t sign[AR5416_MAX_CHAINS];
733 u32 sta_id1_defaults;
739 } enable_32kHz_clock;
741 /* Private to hardware code */
742 struct ath_hw_private_ops private_ops;
743 /* Accessed by the lower level driver */
744 struct ath_hw_ops ops;
746 /* Used to program the radio on non single-chip devices */
747 u32 *analogBank0Data;
748 u32 *analogBank1Data;
749 u32 *analogBank2Data;
750 u32 *analogBank3Data;
751 u32 *analogBank6Data;
752 u32 *analogBank6TPCData;
753 u32 *analogBank7Data;
765 int totalSizeDesired[5];
769 enum ath9k_ani_cmd ani_function;
771 /* Bluetooth coexistance */
772 struct ath_btcoex_hw btcoex_hw;
778 struct ath_hw_radar_conf radar_conf;
780 u32 originalGain[22];
787 struct ar5416IniArray iniModes;
788 struct ar5416IniArray iniCommon;
789 struct ar5416IniArray iniBank0;
790 struct ar5416IniArray iniBB_RfGain;
791 struct ar5416IniArray iniBank1;
792 struct ar5416IniArray iniBank2;
793 struct ar5416IniArray iniBank3;
794 struct ar5416IniArray iniBank6;
795 struct ar5416IniArray iniBank6TPC;
796 struct ar5416IniArray iniBank7;
797 struct ar5416IniArray iniAddac;
798 struct ar5416IniArray iniPcieSerdes;
799 struct ar5416IniArray iniPcieSerdesLowPower;
800 struct ar5416IniArray iniModesAdditional;
801 struct ar5416IniArray iniModesRxGain;
802 struct ar5416IniArray iniModesTxGain;
803 struct ar5416IniArray iniModes_9271_1_0_only;
804 struct ar5416IniArray iniCckfirNormal;
805 struct ar5416IniArray iniCckfirJapan2484;
806 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
807 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
808 struct ar5416IniArray iniModes_9271_ANI_reg;
809 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
810 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
812 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
813 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
814 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
815 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
817 u32 intr_gen_timer_trigger;
818 u32 intr_gen_timer_thresh;
819 struct ath_gen_timer_table hw_gen_timers;
821 struct ar9003_txs *ts_ring;
828 u32 bb_watchdog_last_status;
829 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
831 unsigned int paprd_target_power;
832 unsigned int paprd_training_power;
833 unsigned int paprd_ratemask;
834 unsigned int paprd_ratemask_ht40;
835 bool paprd_table_write_done;
836 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
837 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
839 * Store the permanent value of Reg 0x4004in WARegVal
840 * so we dont have to R/M/W. We should not be reading
841 * this register when in sleep states.
845 /* Enterprise mode cap */
849 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
854 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
856 return &(ath9k_hw_common(ah)->regulatory);
859 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
861 return &ah->private_ops;
864 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
869 static inline u8 get_streams(int mask)
871 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
874 /* Initialization, Detach, Reset */
875 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
876 void ath9k_hw_deinit(struct ath_hw *ah);
877 int ath9k_hw_init(struct ath_hw *ah);
878 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
879 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
880 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
881 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
883 /* GPIO / RFKILL / Antennae */
884 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
885 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
886 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
888 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
889 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
890 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
891 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
892 struct ath_hw_antcomb_conf *antconf);
893 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
894 struct ath_hw_antcomb_conf *antconf);
896 /* General Operation */
897 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
898 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
899 int column, unsigned int *writecnt);
900 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
901 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
903 u32 frameLen, u16 rateix, bool shortPreamble);
904 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
905 struct ath9k_channel *chan,
906 struct chan_centers *centers);
907 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
908 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
909 bool ath9k_hw_phy_disable(struct ath_hw *ah);
910 bool ath9k_hw_disable(struct ath_hw *ah);
911 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
912 void ath9k_hw_setopmode(struct ath_hw *ah);
913 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
914 void ath9k_hw_setbssidmask(struct ath_hw *ah);
915 void ath9k_hw_write_associd(struct ath_hw *ah);
916 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
917 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
918 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
919 void ath9k_hw_reset_tsf(struct ath_hw *ah);
920 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
921 void ath9k_hw_init_global_settings(struct ath_hw *ah);
922 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
923 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
924 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
925 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
926 const struct ath9k_beacon_state *bs);
927 bool ath9k_hw_check_alive(struct ath_hw *ah);
929 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
931 /* Generic hw timer primitives */
932 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
933 void (*trigger)(void *),
934 void (*overflow)(void *),
937 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
938 struct ath_gen_timer *timer,
941 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
943 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
944 void ath_gen_timer_isr(struct ath_hw *hw);
946 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
949 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
952 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
953 u32 *coef_mantissa, u32 *coef_exponent);
956 * Code Specific to AR5008, AR9001 or AR9002,
957 * we stuff these here to avoid callbacks for AR9003.
959 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
960 int ar9002_hw_rf_claim(struct ath_hw *ah);
961 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
962 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
963 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
966 * Code specific to AR9003, we stuff these here to avoid callbacks
969 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
970 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
971 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
972 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
973 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
974 struct ath9k_hw_cal_data *caldata,
976 int ar9003_paprd_create_curve(struct ath_hw *ah,
977 struct ath9k_hw_cal_data *caldata, int chain);
978 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
979 int ar9003_paprd_init_table(struct ath_hw *ah);
980 bool ar9003_paprd_is_done(struct ath_hw *ah);
981 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
983 /* Hardware family op attach helpers */
984 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
985 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
986 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
988 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
989 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
991 void ar9002_hw_attach_ops(struct ath_hw *ah);
992 void ar9003_hw_attach_ops(struct ath_hw *ah);
994 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
996 * ANI work can be shared between all families but a next
997 * generation implementation of ANI will be used only for AR9003 only
998 * for now as the other families still need to be tested with the same
999 * next generation ANI. Feel free to start testing it though for the
1000 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1002 extern int modparam_force_new_ani;
1003 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1004 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1005 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1007 #define ATH_PCIE_CAP_LINK_CTRL 0x70
1008 #define ATH_PCIE_CAP_LINK_L0S 1
1009 #define ATH_PCIE_CAP_LINK_L1 2
1011 #define ATH9K_CLOCK_RATE_CCK 22
1012 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1013 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1014 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44