2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
48 #define AR5416_AR9100_DEVID 0x000b
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 #define ATH9K_NUM_CHANNELS 38
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
70 #define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
73 #define ENABLE_REGWRITE_BUFFER(_ah) \
75 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
76 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
79 #define REGWRITE_BUFFER_FLUSH(_ah) \
81 if (ath9k_hw_common(_ah)->ops->write_flush) \
82 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
85 #define SM(_v, _f) (((_v) << _f##_S) & _f)
86 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
87 #define REG_RMW(_a, _r, _set, _clr) \
88 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
89 #define REG_RMW_FIELD(_a, _r, _f, _v) \
91 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
92 #define REG_READ_FIELD(_a, _r, _f) \
93 (((REG_READ(_a, _r) & _f) >> _f##_S))
94 #define REG_SET_BIT(_a, _r, _f) \
95 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
96 #define REG_CLR_BIT(_a, _r, _f) \
97 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
99 #define DO_DELAY(x) do { \
100 if ((++(x) % 64) == 0) \
104 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
106 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
107 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
108 INI_RA((iniarray), r, (column))); \
113 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
114 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
115 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
116 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
117 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
118 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
119 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
121 #define AR_GPIOD_MASK 0x00001FFF
122 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
124 #define BASE_ACTIVATE_DELAY 100
125 #define RTC_PLL_SETTLE_DELAY 100
126 #define COEF_SCALE_S 24
127 #define HT40_CHANNEL_CENTER_SHIFT 10
129 #define ATH9K_ANTENNA0_CHAINMASK 0x1
130 #define ATH9K_ANTENNA1_CHAINMASK 0x2
132 #define ATH9K_NUM_DMA_DEBUG_REGS 8
133 #define ATH9K_NUM_QUEUES 10
135 #define MAX_RATE_POWER 63
136 #define AH_WAIT_TIMEOUT 100000 /* (us) */
137 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
138 #define AH_TIME_QUANTUM 10
139 #define AR_KEYTABLE_SIZE 128
140 #define POWER_UP_TIME 10000
141 #define SPUR_RSSI_THRESH 40
143 #define CAB_TIMEOUT_VAL 10
144 #define BEACON_TIMEOUT_VAL 10
145 #define MIN_BEACON_TIMEOUT_VAL 1
148 #define INIT_CONFIG_STATUS 0x00000000
149 #define INIT_RSSI_THR 0x00000700
150 #define INIT_BCON_CNTRL_REG 0x00000000
152 #define TU_TO_USEC(_tu) ((_tu) << 10)
154 #define ATH9K_HW_RX_HP_QDEPTH 16
155 #define ATH9K_HW_RX_LP_QDEPTH 128
157 #define PAPRD_GAIN_TABLE_ENTRIES 32
158 #define PAPRD_TABLE_SZ 24
160 enum ath_ini_subsys {
168 ATH9K_HW_CAP_HT = BIT(0),
169 ATH9K_HW_CAP_RFSILENT = BIT(1),
170 ATH9K_HW_CAP_CST = BIT(2),
171 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
172 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
173 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
174 ATH9K_HW_CAP_EDMA = BIT(6),
175 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
176 ATH9K_HW_CAP_LDPC = BIT(8),
177 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
178 ATH9K_HW_CAP_SGI_20 = BIT(10),
179 ATH9K_HW_CAP_PAPRD = BIT(11),
180 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
181 ATH9K_HW_CAP_2GHZ = BIT(13),
182 ATH9K_HW_CAP_5GHZ = BIT(14),
185 struct ath9k_hw_capabilities {
186 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
189 u16 low_5ghz_chan, high_5ghz_chan;
190 u16 low_2ghz_chan, high_2ghz_chan;
194 u16 tx_triglevel_max;
206 struct ath9k_ops_config {
207 int dma_beacon_response_time;
208 int sw_beacon_response_time;
209 int additional_swba_backoff;
211 u32 cwm_ignore_extcca;
212 u8 pcie_powersave_enable;
213 bool pcieSerDesWrite;
223 int serialize_regmode;
224 bool rx_intr_mitigation;
225 bool tx_intr_mitigation;
226 #define SPUR_DISABLE 0
227 #define SPUR_ENABLE_IOCTL 1
228 #define SPUR_ENABLE_EEPROM 2
229 #define AR_EEPROM_MODAL_SPURS 5
230 #define AR_SPUR_5413_1 1640
231 #define AR_SPUR_5413_2 1200
232 #define AR_NO_SPUR 0x8000
233 #define AR_BASE_FREQ_2GHZ 2300
234 #define AR_BASE_FREQ_5GHZ 4900
235 #define AR_SPUR_FEEQ_BOUND_HT40 19
236 #define AR_SPUR_FEEQ_BOUND_HT20 10
238 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
240 u16 ani_poll_interval; /* ANI poll interval in ms */
244 ATH9K_INT_RX = 0x00000001,
245 ATH9K_INT_RXDESC = 0x00000002,
246 ATH9K_INT_RXHP = 0x00000001,
247 ATH9K_INT_RXLP = 0x00000002,
248 ATH9K_INT_RXNOFRM = 0x00000008,
249 ATH9K_INT_RXEOL = 0x00000010,
250 ATH9K_INT_RXORN = 0x00000020,
251 ATH9K_INT_TX = 0x00000040,
252 ATH9K_INT_TXDESC = 0x00000080,
253 ATH9K_INT_TIM_TIMER = 0x00000100,
254 ATH9K_INT_BB_WATCHDOG = 0x00000400,
255 ATH9K_INT_TXURN = 0x00000800,
256 ATH9K_INT_MIB = 0x00001000,
257 ATH9K_INT_RXPHY = 0x00004000,
258 ATH9K_INT_RXKCM = 0x00008000,
259 ATH9K_INT_SWBA = 0x00010000,
260 ATH9K_INT_BMISS = 0x00040000,
261 ATH9K_INT_BNR = 0x00100000,
262 ATH9K_INT_TIM = 0x00200000,
263 ATH9K_INT_DTIM = 0x00400000,
264 ATH9K_INT_DTIMSYNC = 0x00800000,
265 ATH9K_INT_GPIO = 0x01000000,
266 ATH9K_INT_CABEND = 0x02000000,
267 ATH9K_INT_TSFOOR = 0x04000000,
268 ATH9K_INT_GENTIMER = 0x08000000,
269 ATH9K_INT_CST = 0x10000000,
270 ATH9K_INT_GTT = 0x20000000,
271 ATH9K_INT_FATAL = 0x40000000,
272 ATH9K_INT_GLOBAL = 0x80000000,
273 ATH9K_INT_BMISC = ATH9K_INT_TIM |
278 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
290 ATH9K_INT_NOCARD = 0xffffffff
293 #define CHANNEL_CW_INT 0x00002
294 #define CHANNEL_CCK 0x00020
295 #define CHANNEL_OFDM 0x00040
296 #define CHANNEL_2GHZ 0x00080
297 #define CHANNEL_5GHZ 0x00100
298 #define CHANNEL_PASSIVE 0x00200
299 #define CHANNEL_DYN 0x00400
300 #define CHANNEL_HALF 0x04000
301 #define CHANNEL_QUARTER 0x08000
302 #define CHANNEL_HT20 0x10000
303 #define CHANNEL_HT40PLUS 0x20000
304 #define CHANNEL_HT40MINUS 0x40000
306 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
307 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
308 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
309 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
310 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
311 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
312 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
313 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
314 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
315 #define CHANNEL_ALL \
324 struct ath9k_hw_cal_data {
332 bool nfcal_interference;
333 u16 small_signal_gain[AR9300_MAX_CHAINS];
334 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
335 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
338 struct ath9k_channel {
339 struct ieee80211_channel *chan;
340 struct ar5416AniState ani;
347 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
348 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
349 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
350 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
351 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
352 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
353 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
354 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
355 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
356 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
357 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
358 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
360 /* These macros check chanmode and not channelFlags */
361 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
362 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
363 ((_c)->chanmode == CHANNEL_G_HT20))
364 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
365 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
366 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
367 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
368 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
370 enum ath9k_power_mode {
373 ATH9K_PM_NETWORK_SLEEP,
377 enum ath9k_tp_scale {
378 ATH9K_TP_SCALE_MAX = 0,
386 SER_REG_MODE_OFF = 0,
388 SER_REG_MODE_AUTO = 2,
391 enum ath9k_rx_qtype {
397 struct ath9k_beacon_state {
401 #define ATH9K_BEACON_PERIOD 0x0000ffff
402 #define ATH9K_BEACON_ENA 0x00800000
403 #define ATH9K_BEACON_RESET_TSF 0x01000000
404 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
407 u16 bs_cfpmaxduration;
410 u16 bs_bmissthreshold;
411 u32 bs_sleepduration;
412 u32 bs_tsfoor_threshold;
415 struct chan_centers {
422 ATH9K_RESET_POWER_ON,
427 struct ath9k_hw_version {
439 /* Generic TSF timer definitions */
441 #define ATH_MAX_GEN_TIMER 16
443 #define AR_GENTMR_BIT(_index) (1 << (_index))
446 * Using de Bruijin sequence to look up 1's index in a 32 bit number
447 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
449 #define debruijn32 0x077CB531U
451 struct ath_gen_timer_configuration {
458 struct ath_gen_timer {
459 void (*trigger)(void *arg);
460 void (*overflow)(void *arg);
465 struct ath_gen_timer_table {
466 u32 gen_timer_index[32];
467 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
469 unsigned long timer_bits;
474 struct ath_hw_antcomb_conf {
481 * struct ath_hw_private_ops - callbacks used internally by hardware code
483 * This structure contains private callbacks designed to only be used internally
484 * by the hardware core.
486 * @init_cal_settings: setup types of calibrations supported
487 * @init_cal: starts actual calibration
489 * @init_mode_regs: Initializes mode registers
490 * @init_mode_gain_regs: Initialize TX/RX gain registers
491 * @macversion_supported: If this specific mac revision is supported
493 * @rf_set_freq: change frequency
494 * @spur_mitigate_freq: spur mitigation
495 * @rf_alloc_ext_banks:
496 * @rf_free_ext_banks:
498 * @compute_pll_control: compute the PLL control value to use for
499 * AR_RTC_PLL_CONTROL for a given channel
500 * @setup_calibration: set up calibration
501 * @iscal_supported: used to query if a type of calibration is supported
503 * @ani_cache_ini_regs: cache the values for ANI from the initial
504 * register settings through the register initialization.
506 struct ath_hw_private_ops {
507 /* Calibration ops */
508 void (*init_cal_settings)(struct ath_hw *ah);
509 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
511 void (*init_mode_regs)(struct ath_hw *ah);
512 void (*init_mode_gain_regs)(struct ath_hw *ah);
513 bool (*macversion_supported)(u32 macversion);
514 void (*setup_calibration)(struct ath_hw *ah,
515 struct ath9k_cal_list *currCal);
518 int (*rf_set_freq)(struct ath_hw *ah,
519 struct ath9k_channel *chan);
520 void (*spur_mitigate_freq)(struct ath_hw *ah,
521 struct ath9k_channel *chan);
522 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
523 void (*rf_free_ext_banks)(struct ath_hw *ah);
524 bool (*set_rf_regs)(struct ath_hw *ah,
525 struct ath9k_channel *chan,
527 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
528 void (*init_bb)(struct ath_hw *ah,
529 struct ath9k_channel *chan);
530 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
531 void (*olc_init)(struct ath_hw *ah);
532 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
533 void (*mark_phy_inactive)(struct ath_hw *ah);
534 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
535 bool (*rfbus_req)(struct ath_hw *ah);
536 void (*rfbus_done)(struct ath_hw *ah);
537 void (*enable_rfkill)(struct ath_hw *ah);
538 void (*restore_chainmask)(struct ath_hw *ah);
539 void (*set_diversity)(struct ath_hw *ah, bool value);
540 u32 (*compute_pll_control)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
544 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
547 void (*ani_cache_ini_regs)(struct ath_hw *ah);
551 * struct ath_hw_ops - callbacks used by hardware code and driver code
553 * This structure contains callbacks designed to to be used internally by
554 * hardware code and also by the lower level driver.
556 * @config_pci_powersave:
557 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
560 void (*config_pci_powersave)(struct ath_hw *ah,
563 void (*rx_enable)(struct ath_hw *ah);
564 void (*set_desc_link)(void *ds, u32 link);
565 void (*get_desc_link)(void *ds, u32 **link);
566 bool (*calibrate)(struct ath_hw *ah,
567 struct ath9k_channel *chan,
570 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
571 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
572 bool is_firstseg, bool is_is_lastseg,
573 const void *ds0, dma_addr_t buf_addr,
575 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
576 struct ath_tx_status *ts);
577 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
578 u32 pktLen, enum ath9k_pkt_type type,
579 u32 txPower, u32 keyIx,
580 enum ath9k_key_type keyType,
582 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
584 u32 durUpdateEn, u32 rtsctsRate,
586 struct ath9k_11n_rate_series series[],
587 u32 nseries, u32 flags);
588 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
590 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
592 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
593 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
594 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
596 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
600 struct ath_nf_limits {
607 struct ieee80211_hw *hw;
608 struct ath_common common;
609 struct ath9k_hw_version hw_version;
610 struct ath9k_ops_config config;
611 struct ath9k_hw_capabilities caps;
612 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
613 struct ath9k_channel *curchan;
616 struct ar5416_eeprom_def def;
617 struct ar5416_eeprom_4k map4k;
618 struct ar9287_eeprom map9287;
619 struct ar9300_eeprom ar9300_eep;
621 const struct eeprom_ops *eep_ops;
626 bool need_an_top2_fixup;
630 struct ath_nf_limits nf_2g;
631 struct ath_nf_limits nf_5g;
639 enum nl80211_iftype opmode;
640 enum ath9k_power_mode power_mode;
642 struct ath9k_hw_cal_data *caldata;
643 struct ath9k_pacal_info pacal_info;
644 struct ar5416Stats stats;
645 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
647 int16_t curchan_rad_index;
648 enum ath9k_int imask;
650 u32 txok_interrupt_mask;
651 u32 txerr_interrupt_mask;
652 u32 txdesc_interrupt_mask;
653 u32 txeol_interrupt_mask;
654 u32 txurn_interrupt_mask;
660 struct ath9k_cal_list iq_caldata;
661 struct ath9k_cal_list adcgain_caldata;
662 struct ath9k_cal_list adcdc_caldata;
663 struct ath9k_cal_list tempCompCalData;
664 struct ath9k_cal_list *cal_list;
665 struct ath9k_cal_list *cal_list_last;
666 struct ath9k_cal_list *cal_list_curr;
667 #define totalPowerMeasI meas0.unsign
668 #define totalPowerMeasQ meas1.unsign
669 #define totalIqCorrMeas meas2.sign
670 #define totalAdcIOddPhase meas0.unsign
671 #define totalAdcIEvenPhase meas1.unsign
672 #define totalAdcQOddPhase meas2.unsign
673 #define totalAdcQEvenPhase meas3.unsign
674 #define totalAdcDcOffsetIOddPhase meas0.sign
675 #define totalAdcDcOffsetIEvenPhase meas1.sign
676 #define totalAdcDcOffsetQOddPhase meas2.sign
677 #define totalAdcDcOffsetQEvenPhase meas3.sign
679 u32 unsign[AR5416_MAX_CHAINS];
680 int32_t sign[AR5416_MAX_CHAINS];
683 u32 unsign[AR5416_MAX_CHAINS];
684 int32_t sign[AR5416_MAX_CHAINS];
687 u32 unsign[AR5416_MAX_CHAINS];
688 int32_t sign[AR5416_MAX_CHAINS];
691 u32 unsign[AR5416_MAX_CHAINS];
692 int32_t sign[AR5416_MAX_CHAINS];
696 u32 sta_id1_defaults;
702 } enable_32kHz_clock;
704 /* Private to hardware code */
705 struct ath_hw_private_ops private_ops;
706 /* Accessed by the lower level driver */
707 struct ath_hw_ops ops;
709 /* Used to program the radio on non single-chip devices */
710 u32 *analogBank0Data;
711 u32 *analogBank1Data;
712 u32 *analogBank2Data;
713 u32 *analogBank3Data;
714 u32 *analogBank6Data;
715 u32 *analogBank6TPCData;
716 u32 *analogBank7Data;
721 int16_t txpower_indexoffset;
730 int totalSizeDesired[5];
734 enum ath9k_ani_cmd ani_function;
736 /* Bluetooth coexistance */
737 struct ath_btcoex_hw btcoex_hw;
743 u32 originalGain[22];
748 struct ar5416IniArray iniModes;
749 struct ar5416IniArray iniCommon;
750 struct ar5416IniArray iniBank0;
751 struct ar5416IniArray iniBB_RfGain;
752 struct ar5416IniArray iniBank1;
753 struct ar5416IniArray iniBank2;
754 struct ar5416IniArray iniBank3;
755 struct ar5416IniArray iniBank6;
756 struct ar5416IniArray iniBank6TPC;
757 struct ar5416IniArray iniBank7;
758 struct ar5416IniArray iniAddac;
759 struct ar5416IniArray iniPcieSerdes;
760 struct ar5416IniArray iniPcieSerdesLowPower;
761 struct ar5416IniArray iniModesAdditional;
762 struct ar5416IniArray iniModesRxGain;
763 struct ar5416IniArray iniModesTxGain;
764 struct ar5416IniArray iniModes_9271_1_0_only;
765 struct ar5416IniArray iniCckfirNormal;
766 struct ar5416IniArray iniCckfirJapan2484;
767 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
768 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
769 struct ar5416IniArray iniModes_9271_ANI_reg;
770 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
771 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
773 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
774 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
775 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
776 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
778 u32 intr_gen_timer_trigger;
779 u32 intr_gen_timer_thresh;
780 struct ath_gen_timer_table hw_gen_timers;
782 struct ar9003_txs *ts_ring;
789 u32 bb_watchdog_last_status;
790 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
792 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
793 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
795 * Store the permanent value of Reg 0x4004in WARegVal
796 * so we dont have to R/M/W. We should not be reading
797 * this register when in sleep states.
802 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
807 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
809 return &(ath9k_hw_common(ah)->regulatory);
812 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
814 return &ah->private_ops;
817 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
822 static inline int sign_extend(int val, const int nbits)
824 int order = BIT(nbits-1);
825 return (val ^ order) - order;
828 /* Initialization, Detach, Reset */
829 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
830 void ath9k_hw_deinit(struct ath_hw *ah);
831 int ath9k_hw_init(struct ath_hw *ah);
832 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
833 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
834 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
835 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
837 /* GPIO / RFKILL / Antennae */
838 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
839 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
840 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
842 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
843 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
844 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
845 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
846 struct ath_hw_antcomb_conf *antconf);
847 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
848 struct ath_hw_antcomb_conf *antconf);
850 /* General Operation */
851 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
852 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
853 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
854 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
856 u32 frameLen, u16 rateix, bool shortPreamble);
857 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
858 struct ath9k_channel *chan,
859 struct chan_centers *centers);
860 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
861 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
862 bool ath9k_hw_phy_disable(struct ath_hw *ah);
863 bool ath9k_hw_disable(struct ath_hw *ah);
864 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
865 void ath9k_hw_setopmode(struct ath_hw *ah);
866 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
867 void ath9k_hw_setbssidmask(struct ath_hw *ah);
868 void ath9k_hw_write_associd(struct ath_hw *ah);
869 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
870 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
871 void ath9k_hw_reset_tsf(struct ath_hw *ah);
872 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
873 void ath9k_hw_init_global_settings(struct ath_hw *ah);
874 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
875 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
876 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
877 const struct ath9k_beacon_state *bs);
878 bool ath9k_hw_check_alive(struct ath_hw *ah);
880 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
882 /* Generic hw timer primitives */
883 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
884 void (*trigger)(void *),
885 void (*overflow)(void *),
888 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
889 struct ath_gen_timer *timer,
892 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
894 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
895 void ath_gen_timer_isr(struct ath_hw *hw);
896 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
898 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
901 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
904 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
905 u32 *coef_mantissa, u32 *coef_exponent);
908 * Code Specific to AR5008, AR9001 or AR9002,
909 * we stuff these here to avoid callbacks for AR9003.
911 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
912 int ar9002_hw_rf_claim(struct ath_hw *ah);
913 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
914 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
915 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
918 * Code specific to AR9003, we stuff these here to avoid callbacks
921 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
922 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
923 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
924 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
925 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
926 struct ath9k_hw_cal_data *caldata,
928 int ar9003_paprd_create_curve(struct ath_hw *ah,
929 struct ath9k_hw_cal_data *caldata, int chain);
930 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
931 int ar9003_paprd_init_table(struct ath_hw *ah);
932 bool ar9003_paprd_is_done(struct ath_hw *ah);
933 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
935 /* Hardware family op attach helpers */
936 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
937 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
938 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
940 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
941 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
943 void ar9002_hw_attach_ops(struct ath_hw *ah);
944 void ar9003_hw_attach_ops(struct ath_hw *ah);
946 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
948 * ANI work can be shared between all families but a next
949 * generation implementation of ANI will be used only for AR9003 only
950 * for now as the other families still need to be tested with the same
951 * next generation ANI. Feel free to start testing it though for the
952 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
954 extern int modparam_force_new_ani;
955 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
956 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
957 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
959 #define ATH_PCIE_CAP_LINK_CTRL 0x70
960 #define ATH_PCIE_CAP_LINK_L0S 1
961 #define ATH_PCIE_CAP_LINK_L1 2
963 #define ATH9K_CLOCK_RATE_CCK 22
964 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
965 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
966 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44