2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
33 static char *dev_info = "ath9k";
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49 module_param_named(blink, ath9k_led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
52 static int ath9k_led_active_high = -1;
53 module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
54 MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
56 static int ath9k_btcoex_enable;
57 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
58 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
60 static int ath9k_bt_ant_diversity;
61 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
62 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
64 static int ath9k_ps_enable;
65 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
66 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
68 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
70 int ath9k_use_chanctx;
71 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
72 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
74 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
76 bool is_ath9k_unloaded;
78 #ifdef CONFIG_MAC80211_LEDS
79 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
80 { .throughput = 0 * 1024, .blink_time = 334 },
81 { .throughput = 1 * 1024, .blink_time = 260 },
82 { .throughput = 5 * 1024, .blink_time = 220 },
83 { .throughput = 10 * 1024, .blink_time = 190 },
84 { .throughput = 20 * 1024, .blink_time = 170 },
85 { .throughput = 50 * 1024, .blink_time = 150 },
86 { .throughput = 70 * 1024, .blink_time = 130 },
87 { .throughput = 100 * 1024, .blink_time = 110 },
88 { .throughput = 200 * 1024, .blink_time = 80 },
89 { .throughput = 300 * 1024, .blink_time = 50 },
93 static void ath9k_deinit_softc(struct ath_softc *sc);
95 static void ath9k_op_ps_wakeup(struct ath_common *common)
97 ath9k_ps_wakeup((struct ath_softc *) common->priv);
100 static void ath9k_op_ps_restore(struct ath_common *common)
102 ath9k_ps_restore((struct ath_softc *) common->priv);
105 static struct ath_ps_ops ath9k_ps_ops = {
106 .wakeup = ath9k_op_ps_wakeup,
107 .restore = ath9k_op_ps_restore,
111 * Read and write, they both share the same lock. We do this to serialize
112 * reads and writes on Atheros 802.11n PCI devices only. This is required
113 * as the FIFO on these devices can only accept sanely 2 requests.
116 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
118 struct ath_hw *ah = (struct ath_hw *) hw_priv;
119 struct ath_common *common = ath9k_hw_common(ah);
120 struct ath_softc *sc = (struct ath_softc *) common->priv;
122 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
124 spin_lock_irqsave(&sc->sc_serial_rw, flags);
125 iowrite32(val, sc->mem + reg_offset);
126 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
128 iowrite32(val, sc->mem + reg_offset);
131 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
133 struct ath_hw *ah = (struct ath_hw *) hw_priv;
134 struct ath_common *common = ath9k_hw_common(ah);
135 struct ath_softc *sc = (struct ath_softc *) common->priv;
138 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
140 spin_lock_irqsave(&sc->sc_serial_rw, flags);
141 val = ioread32(sc->mem + reg_offset);
142 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
144 val = ioread32(sc->mem + reg_offset);
148 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
153 for (i = 0; i < count; i++)
154 val[i] = ath9k_ioread32(hw_priv, addr[i]);
158 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
163 val = ioread32(sc->mem + reg_offset);
166 iowrite32(val, sc->mem + reg_offset);
171 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
173 struct ath_hw *ah = (struct ath_hw *) hw_priv;
174 struct ath_common *common = ath9k_hw_common(ah);
175 struct ath_softc *sc = (struct ath_softc *) common->priv;
176 unsigned long uninitialized_var(flags);
179 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
180 spin_lock_irqsave(&sc->sc_serial_rw, flags);
181 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
182 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
184 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
189 /**************************/
191 /**************************/
193 static void ath9k_reg_notifier(struct wiphy *wiphy,
194 struct regulatory_request *request)
196 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
197 struct ath_softc *sc = hw->priv;
198 struct ath_hw *ah = sc->sc_ah;
199 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
201 ath_reg_notifier_apply(wiphy, request, reg);
207 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
209 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
210 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
211 sc->cur_chan->txpower,
212 &sc->cur_chan->cur_txpower);
213 /* synchronize DFS detector if regulatory domain changed */
214 if (sc->dfs_detector != NULL)
215 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
216 request->dfs_region);
217 ath9k_ps_restore(sc);
221 * This function will allocate both the DMA descriptor structure, and the
222 * buffers it contains. These are used to contain the descriptors used
225 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
226 struct list_head *head, const char *name,
227 int nbuf, int ndesc, bool is_tx)
229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
231 int i, bsize, desc_len;
233 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
236 INIT_LIST_HEAD(head);
239 desc_len = sc->sc_ah->caps.tx_desc_len;
241 desc_len = sizeof(struct ath_desc);
243 /* ath_desc must be a multiple of DWORDs */
244 if ((desc_len % 4) != 0) {
245 ath_err(common, "ath_desc not DWORD aligned\n");
246 BUG_ON((desc_len % 4) != 0);
250 dd->dd_desc_len = desc_len * nbuf * ndesc;
253 * Need additional DMA memory because we can't use
254 * descriptors that cross the 4K page boundary. Assume
255 * one skipped descriptor per 4K page.
257 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
259 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
262 while (ndesc_skipped) {
263 dma_len = ndesc_skipped * desc_len;
264 dd->dd_desc_len += dma_len;
266 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
270 /* allocate descriptors */
271 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
272 &dd->dd_desc_paddr, GFP_KERNEL);
276 ds = (u8 *) dd->dd_desc;
277 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
278 name, ds, (u32) dd->dd_desc_len,
279 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
281 /* allocate buffers */
285 bsize = sizeof(struct ath_buf) * nbuf;
286 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
290 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
292 bf->bf_daddr = DS2PHYS(dd, ds);
294 if (!(sc->sc_ah->caps.hw_caps &
295 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
297 * Skip descriptor addresses which can cause 4KB
298 * boundary crossing (addr + length) with a 32 dword
301 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
302 BUG_ON((caddr_t) bf->bf_desc >=
303 ((caddr_t) dd->dd_desc +
306 ds += (desc_len * ndesc);
308 bf->bf_daddr = DS2PHYS(dd, ds);
311 list_add_tail(&bf->list, head);
314 struct ath_rxbuf *bf;
316 bsize = sizeof(struct ath_rxbuf) * nbuf;
317 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
321 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
323 bf->bf_daddr = DS2PHYS(dd, ds);
325 if (!(sc->sc_ah->caps.hw_caps &
326 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
328 * Skip descriptor addresses which can cause 4KB
329 * boundary crossing (addr + length) with a 32 dword
332 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
333 BUG_ON((caddr_t) bf->bf_desc >=
334 ((caddr_t) dd->dd_desc +
337 ds += (desc_len * ndesc);
339 bf->bf_daddr = DS2PHYS(dd, ds);
342 list_add_tail(&bf->list, head);
348 static int ath9k_init_queues(struct ath_softc *sc)
352 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
353 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
356 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
358 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
359 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
360 sc->tx.txq_map[i]->mac80211_qnum = i;
361 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
366 static void ath9k_init_misc(struct ath_softc *sc)
368 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
371 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
373 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
374 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
375 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
377 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
378 sc->beacon.bslot[i] = NULL;
380 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
381 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
383 sc->spec_priv.ah = sc->sc_ah;
384 sc->spec_priv.spec_config.enabled = 0;
385 sc->spec_priv.spec_config.short_repeat = true;
386 sc->spec_priv.spec_config.count = 8;
387 sc->spec_priv.spec_config.endless = false;
388 sc->spec_priv.spec_config.period = 0xFF;
389 sc->spec_priv.spec_config.fft_period = 0xF;
392 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
394 struct ath_hw *ah = sc->sc_ah;
395 struct ath9k_hw_capabilities *pCap = &ah->caps;
396 struct ath_common *common = ath9k_hw_common(ah);
398 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
401 if (common->bus_ops->ath_bus_type != ATH_PCI)
404 if (sc->driver_data & (ATH9K_PCI_CUS198 |
406 ah->config.xlna_gpio = 9;
407 ah->config.xatten_margin_cfg = true;
408 ah->config.alt_mingainidx = true;
409 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
410 sc->ant_comb.low_rssi_thresh = 20;
411 sc->ant_comb.fast_div_bias = 3;
413 ath_info(common, "Set parameters for %s\n",
414 (sc->driver_data & ATH9K_PCI_CUS198) ?
415 "CUS198" : "CUS230");
418 if (sc->driver_data & ATH9K_PCI_CUS217)
419 ath_info(common, "CUS217 card detected\n");
421 if (sc->driver_data & ATH9K_PCI_CUS252)
422 ath_info(common, "CUS252 card detected\n");
424 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
425 ath_info(common, "WB335 1-ANT card detected\n");
427 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
428 ath_info(common, "WB335 2-ANT card detected\n");
430 if (sc->driver_data & ATH9K_PCI_KILLER)
431 ath_info(common, "Killer Wireless card detected\n");
434 * Some WB335 cards do not support antenna diversity. Since
435 * we use a hardcoded value for AR9565 instead of using the
436 * EEPROM/OTP data, remove the combining feature from
437 * the HW capabilities bitmap.
439 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
440 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
441 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
444 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
445 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
446 ath_info(common, "Set BT/WLAN RX diversity capability\n");
449 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
450 ah->config.pcie_waen = 0x0040473b;
451 ath_info(common, "Enable WAR for ASPM D3/L1\n");
455 * The default value of pll_pwrsave is 1.
456 * For certain AR9485 cards, it is set to 0.
457 * For AR9462, AR9565 it's set to 7.
459 ah->config.pll_pwrsave = 1;
461 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
462 ah->config.pll_pwrsave = 0;
463 ath_info(common, "Disable PLL PowerSave\n");
466 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
467 ah->config.led_active_high = true;
470 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
473 struct ath9k_eeprom_ctx *ec = ctx;
476 ec->ah->eeprom_blob = eeprom_blob;
478 complete(&ec->complete);
481 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
483 struct ath9k_eeprom_ctx ec;
484 struct ath_hw *ah = sc->sc_ah;
487 /* try to load the EEPROM content asynchronously */
488 init_completion(&ec.complete);
491 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
492 &ec, ath9k_eeprom_request_cb);
494 ath_err(ath9k_hw_common(ah),
495 "EEPROM request failed\n");
499 wait_for_completion(&ec.complete);
501 if (!ah->eeprom_blob) {
502 ath_err(ath9k_hw_common(ah),
503 "Unable to load EEPROM file %s\n", name);
510 static void ath9k_eeprom_release(struct ath_softc *sc)
512 release_firmware(sc->sc_ah->eeprom_blob);
515 static int ath9k_init_soc_platform(struct ath_softc *sc)
517 struct ath9k_platform_data *pdata = sc->dev->platform_data;
518 struct ath_hw *ah = sc->sc_ah;
524 if (pdata->eeprom_name) {
525 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
530 if (pdata->led_active_high)
531 ah->config.led_active_high = true;
533 if (pdata->tx_gain_buffalo)
534 ah->config.tx_gain_buffalo = true;
539 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
540 const struct ath_bus_ops *bus_ops)
542 struct ath9k_platform_data *pdata = sc->dev->platform_data;
543 struct ath_hw *ah = NULL;
544 struct ath9k_hw_capabilities *pCap;
545 struct ath_common *common;
549 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
555 ah->hw_version.devid = devid;
556 ah->reg_ops.read = ath9k_ioread32;
557 ah->reg_ops.multi_read = ath9k_multi_ioread32;
558 ah->reg_ops.write = ath9k_iowrite32;
559 ah->reg_ops.rmw = ath9k_reg_rmw;
562 common = ath9k_hw_common(ah);
564 /* Will be cleared in ath9k_start() */
565 set_bit(ATH_OP_INVALID, &common->op_flags);
568 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
569 sc->tx99_power = MAX_RATE_POWER + 1;
570 init_waitqueue_head(&sc->tx_wait);
571 sc->cur_chan = &sc->chanctx[0];
572 if (!ath9k_is_chanctx_enabled())
573 sc->cur_chan->hw_queue_base = 0;
575 if (!pdata || pdata->use_eeprom) {
576 ah->ah_flags |= AH_USE_EEPROM;
577 sc->sc_ah->led_pin = -1;
579 sc->sc_ah->gpio_mask = pdata->gpio_mask;
580 sc->sc_ah->gpio_val = pdata->gpio_val;
581 sc->sc_ah->led_pin = pdata->led_pin;
582 ah->is_clk_25mhz = pdata->is_clk_25mhz;
583 ah->get_mac_revision = pdata->get_mac_revision;
584 ah->external_reset = pdata->external_reset;
585 ah->disable_2ghz = pdata->disable_2ghz;
586 ah->disable_5ghz = pdata->disable_5ghz;
587 if (!pdata->endian_check)
588 ah->ah_flags |= AH_NO_EEP_SWAP;
591 common->ops = &ah->reg_ops;
592 common->bus_ops = bus_ops;
593 common->ps_ops = &ath9k_ps_ops;
597 common->debug_mask = ath9k_debug;
598 common->btcoex_enabled = ath9k_btcoex_enable == 1;
599 common->disable_ani = false;
604 ath9k_init_pcoem_platform(sc);
606 ret = ath9k_init_soc_platform(sc);
610 if (ath9k_led_active_high != -1)
611 ah->config.led_active_high = ath9k_led_active_high == 1;
614 * Enable WLAN/BT RX Antenna diversity only when:
616 * - BTCOEX is disabled.
617 * - the user manually requests the feature.
618 * - the HW cap is set using the platform data.
620 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
621 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
622 common->bt_ant_diversity = 1;
624 spin_lock_init(&common->cc_lock);
625 spin_lock_init(&sc->sc_serial_rw);
626 spin_lock_init(&sc->sc_pm_lock);
627 spin_lock_init(&sc->chan_lock);
628 mutex_init(&sc->mutex);
629 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
630 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
633 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
634 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
635 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
636 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
638 ath9k_init_channel_context(sc);
641 * Cache line size is used to size and align various
642 * structures used to communicate with the hardware.
644 ath_read_cachesize(common, &csz);
645 common->cachelsz = csz << 2; /* convert to bytes */
647 /* Initializes the hardware for all supported chipsets */
648 ret = ath9k_hw_init(ah);
652 if (pdata && pdata->macaddr)
653 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
655 ret = ath9k_init_queues(sc);
659 ret = ath9k_init_btcoex(sc);
663 ret = ath9k_cmn_init_channels_rates(common);
667 ret = ath9k_init_p2p(sc);
671 ath9k_cmn_init_crypto(sc->sc_ah);
673 ath_chanctx_init(sc);
674 ath9k_offchannel_init(sc);
676 if (common->bus_ops->aspm_init)
677 common->bus_ops->aspm_init(common);
682 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
683 if (ATH_TXQ_SETUP(sc, i))
684 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
688 ath9k_eeprom_release(sc);
689 dev_kfree_skb_any(sc->tx99_skb);
693 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
695 struct ieee80211_supported_band *sband;
696 struct ieee80211_channel *chan;
697 struct ath_hw *ah = sc->sc_ah;
698 struct ath_common *common = ath9k_hw_common(ah);
699 struct cfg80211_chan_def chandef;
702 sband = &common->sbands[band];
703 for (i = 0; i < sband->n_channels; i++) {
704 chan = &sband->channels[i];
705 ah->curchan = &ah->channels[chan->hw_value];
706 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
707 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
708 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
712 static void ath9k_init_txpower_limits(struct ath_softc *sc)
714 struct ath_hw *ah = sc->sc_ah;
715 struct ath9k_channel *curchan = ah->curchan;
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
718 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
719 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
720 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
722 ah->curchan = curchan;
725 static const struct ieee80211_iface_limit if_limits[] = {
726 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
728 #ifdef CONFIG_MAC80211_MESH
729 BIT(NL80211_IFTYPE_MESH_POINT) |
731 BIT(NL80211_IFTYPE_AP) },
732 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
733 BIT(NL80211_IFTYPE_P2P_GO) },
736 static const struct ieee80211_iface_limit wds_limits[] = {
737 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
740 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
742 static const struct ieee80211_iface_limit if_limits_multi[] = {
743 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
744 BIT(NL80211_IFTYPE_AP) |
745 BIT(NL80211_IFTYPE_P2P_CLIENT) |
746 BIT(NL80211_IFTYPE_P2P_GO) },
747 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
748 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
751 static const struct ieee80211_iface_combination if_comb_multi[] = {
753 .limits = if_limits_multi,
754 .n_limits = ARRAY_SIZE(if_limits_multi),
756 .num_different_channels = 2,
757 .beacon_int_infra_match = true,
761 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
763 static const struct ieee80211_iface_combination if_comb[] = {
766 .n_limits = ARRAY_SIZE(if_limits),
767 .max_interfaces = 2048,
768 .num_different_channels = 1,
769 .beacon_int_infra_match = true,
770 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
771 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
772 BIT(NL80211_CHAN_WIDTH_20) |
773 BIT(NL80211_CHAN_WIDTH_40),
777 .limits = wds_limits,
778 .n_limits = ARRAY_SIZE(wds_limits),
779 .max_interfaces = 2048,
780 .num_different_channels = 1,
781 .beacon_int_infra_match = true,
785 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
786 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
788 struct ath_hw *ah = sc->sc_ah;
789 struct ath_common *common = ath9k_hw_common(ah);
791 if (!ath9k_is_chanctx_enabled())
794 ieee80211_hw_set(hw, QUEUE_CONTROL);
795 hw->queues = ATH9K_NUM_TX_QUEUES;
796 hw->offchannel_tx_hw_queue = hw->queues - 1;
797 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
798 hw->wiphy->iface_combinations = if_comb_multi;
799 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
800 hw->wiphy->max_scan_ssids = 255;
801 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
802 hw->wiphy->max_remain_on_channel_duration = 10000;
803 hw->chanctx_data_size = sizeof(void *);
804 hw->extra_beacon_tailroom =
805 sizeof(struct ieee80211_p2p_noa_attr) + 9;
807 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
809 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
811 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
813 struct ath_hw *ah = sc->sc_ah;
814 struct ath_common *common = ath9k_hw_common(ah);
816 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
817 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
818 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
819 ieee80211_hw_set(hw, SPECTRUM_MGMT);
820 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
821 ieee80211_hw_set(hw, SIGNAL_DBM);
822 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
823 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
824 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
825 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
828 ieee80211_hw_set(hw, SUPPORTS_PS);
830 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
831 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
833 if (AR_SREV_9280_20_OR_LATER(ah))
834 hw->radiotap_mcs_details |=
835 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
838 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
839 ieee80211_hw_set(hw, MFP_CAPABLE);
841 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
842 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
843 NL80211_FEATURE_P2P_GO_CTWIN;
845 if (!config_enabled(CONFIG_ATH9K_TX99)) {
846 hw->wiphy->interface_modes =
847 BIT(NL80211_IFTYPE_P2P_GO) |
848 BIT(NL80211_IFTYPE_P2P_CLIENT) |
849 BIT(NL80211_IFTYPE_AP) |
850 BIT(NL80211_IFTYPE_STATION) |
851 BIT(NL80211_IFTYPE_ADHOC) |
852 BIT(NL80211_IFTYPE_MESH_POINT) |
853 BIT(NL80211_IFTYPE_WDS) |
854 BIT(NL80211_IFTYPE_OCB);
856 if (ath9k_is_chanctx_enabled())
857 hw->wiphy->interface_modes |=
858 BIT(NL80211_IFTYPE_P2P_DEVICE);
860 hw->wiphy->iface_combinations = if_comb;
861 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
864 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
866 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
867 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
868 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
869 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
870 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
871 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
875 hw->max_listen_interval = 10;
876 hw->max_rate_tries = 10;
877 hw->sta_data_size = sizeof(struct ath_node);
878 hw->vif_data_size = sizeof(struct ath_vif);
879 hw->extra_tx_headroom = 4;
881 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
882 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
884 /* single chain devices with rx diversity */
885 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
886 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
888 sc->ant_rx = hw->wiphy->available_antennas_rx;
889 sc->ant_tx = hw->wiphy->available_antennas_tx;
891 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
892 hw->wiphy->bands[NL80211_BAND_2GHZ] =
893 &common->sbands[NL80211_BAND_2GHZ];
894 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
895 hw->wiphy->bands[NL80211_BAND_5GHZ] =
896 &common->sbands[NL80211_BAND_5GHZ];
898 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
899 ath9k_set_mcc_capab(sc, hw);
902 ath9k_cmn_reload_chainmask(ah);
904 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
907 int ath9k_init_device(u16 devid, struct ath_softc *sc,
908 const struct ath_bus_ops *bus_ops)
910 struct ieee80211_hw *hw = sc->hw;
911 struct ath_common *common;
914 struct ath_regulatory *reg;
916 /* Bring up device */
917 error = ath9k_init_softc(devid, sc, bus_ops);
922 common = ath9k_hw_common(ah);
923 ath9k_set_hw_capab(sc, hw);
925 /* Initialize regulatory */
926 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
931 reg = &common->regulatory;
934 error = ath_tx_init(sc, ATH_TXBUF);
939 error = ath_rx_init(sc, ATH_RXBUF);
943 ath9k_init_txpower_limits(sc);
945 #ifdef CONFIG_MAC80211_LEDS
946 /* must be initialized before ieee80211_register_hw */
947 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
948 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
949 ARRAY_SIZE(ath9k_tpt_blink));
952 /* Register with mac80211 */
953 error = ieee80211_register_hw(hw);
957 error = ath9k_init_debug(ah);
959 ath_err(common, "Unable to create debugfs files\n");
963 /* Handle world regulatory */
964 if (!ath_is_world_regd(reg)) {
965 error = regulatory_hint(hw->wiphy, reg->alpha2);
971 ath_start_rfkill_poll(sc);
976 ath9k_deinit_debug(sc);
978 ieee80211_unregister_hw(hw);
982 ath9k_deinit_softc(sc);
986 /*****************************/
987 /* De-Initialization */
988 /*****************************/
990 static void ath9k_deinit_softc(struct ath_softc *sc)
994 ath9k_deinit_p2p(sc);
995 ath9k_deinit_btcoex(sc);
997 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
998 if (ATH_TXQ_SETUP(sc, i))
999 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1001 del_timer_sync(&sc->sleep_timer);
1002 ath9k_hw_deinit(sc->sc_ah);
1003 if (sc->dfs_detector != NULL)
1004 sc->dfs_detector->exit(sc->dfs_detector);
1006 ath9k_eeprom_release(sc);
1009 void ath9k_deinit_device(struct ath_softc *sc)
1011 struct ieee80211_hw *hw = sc->hw;
1013 ath9k_ps_wakeup(sc);
1015 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1016 ath_deinit_leds(sc);
1018 ath9k_ps_restore(sc);
1020 ath9k_deinit_debug(sc);
1021 ath9k_deinit_wow(hw);
1022 ieee80211_unregister_hw(hw);
1024 ath9k_deinit_softc(sc);
1027 /************************/
1029 /************************/
1031 static int __init ath9k_init(void)
1035 error = ath_pci_init();
1037 pr_err("No PCI devices found, driver not installed\n");
1042 error = ath_ahb_init();
1055 module_init(ath9k_init);
1057 static void __exit ath9k_exit(void)
1059 is_ath9k_unloaded = true;
1062 pr_info("%s: Driver unloaded\n", dev_info);
1064 module_exit(ath9k_exit);