drivers/net/wireless/ath/ath9k/init.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/ath9k_platform.h>
  22 #include <linux/module.h>
  23 #include <linux/relay.h>
  24 #include <net/ieee80211_radiotap.h>
  25
  26 #include "ath9k.h"
  27
  28 struct ath9k_eeprom_ctx {
  29         struct completion complete;
  30         struct ath_hw *ah;
  31 };
  32
  33 static char *dev_info = "ath9k";
  34
  35 MODULE_AUTHOR("Atheros Communications");
  36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  38 MODULE_LICENSE("Dual BSD/GPL");
  39
  40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  41 module_param_named(debug, ath9k_debug, uint, 0);
  42 MODULE_PARM_DESC(debug, "Debugging mask");
  43
  44 int ath9k_modparam_nohwcrypt;
  45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  47
  48 int led_blink;
  49 module_param_named(blink, led_blink, int, 0444);
  50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  51
  52 static int ath9k_btcoex_enable;
  53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
  54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  55
  56 static int ath9k_bt_ant_diversity;
  57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
  58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
  59
  60 bool is_ath9k_unloaded;
  61 /* We use the hw_value as an index into our private channel structure */
  62
  63 #define CHAN2G(_freq, _idx)  { \
  64         .band = IEEE80211_BAND_2GHZ, \
  65         .center_freq = (_freq), \
  66         .hw_value = (_idx), \
  67         .max_power = 20, \
  68 }
  69
  70 #define CHAN5G(_freq, _idx) { \
  71         .band = IEEE80211_BAND_5GHZ, \
  72         .center_freq = (_freq), \
  73         .hw_value = (_idx), \
  74         .max_power = 20, \
  75 }
  76
  77 /* Some 2 GHz radios are actually tunable on 2312-2732
  78  * on 5 MHz steps, we support the channels which we know
  79  * we have calibration data for all cards though to make
  80  * this static */
  81 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
  82         CHAN2G(2412, 0), /* Channel 1 */
  83         CHAN2G(2417, 1), /* Channel 2 */
  84         CHAN2G(2422, 2), /* Channel 3 */
  85         CHAN2G(2427, 3), /* Channel 4 */
  86         CHAN2G(2432, 4), /* Channel 5 */
  87         CHAN2G(2437, 5), /* Channel 6 */
  88         CHAN2G(2442, 6), /* Channel 7 */
  89         CHAN2G(2447, 7), /* Channel 8 */
  90         CHAN2G(2452, 8), /* Channel 9 */
  91         CHAN2G(2457, 9), /* Channel 10 */
  92         CHAN2G(2462, 10), /* Channel 11 */
  93         CHAN2G(2467, 11), /* Channel 12 */
  94         CHAN2G(2472, 12), /* Channel 13 */
  95         CHAN2G(2484, 13), /* Channel 14 */
  96 };
  97
  98 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  99  * on 5 MHz steps, we support the channels which we know
 100  * we have calibration data for all cards though to make
 101  * this static */
 102 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
 103         /* _We_ call this UNII 1 */
 104         CHAN5G(5180, 14), /* Channel 36 */
 105         CHAN5G(5200, 15), /* Channel 40 */
 106         CHAN5G(5220, 16), /* Channel 44 */
 107         CHAN5G(5240, 17), /* Channel 48 */
 108         /* _We_ call this UNII 2 */
 109         CHAN5G(5260, 18), /* Channel 52 */
 110         CHAN5G(5280, 19), /* Channel 56 */
 111         CHAN5G(5300, 20), /* Channel 60 */
 112         CHAN5G(5320, 21), /* Channel 64 */
 113         /* _We_ call this "Middle band" */
 114         CHAN5G(5500, 22), /* Channel 100 */
 115         CHAN5G(5520, 23), /* Channel 104 */
 116         CHAN5G(5540, 24), /* Channel 108 */
 117         CHAN5G(5560, 25), /* Channel 112 */
 118         CHAN5G(5580, 26), /* Channel 116 */
 119         CHAN5G(5600, 27), /* Channel 120 */
 120         CHAN5G(5620, 28), /* Channel 124 */
 121         CHAN5G(5640, 29), /* Channel 128 */
 122         CHAN5G(5660, 30), /* Channel 132 */
 123         CHAN5G(5680, 31), /* Channel 136 */
 124         CHAN5G(5700, 32), /* Channel 140 */
 125         /* _We_ call this UNII 3 */
 126         CHAN5G(5745, 33), /* Channel 149 */
 127         CHAN5G(5765, 34), /* Channel 153 */
 128         CHAN5G(5785, 35), /* Channel 157 */
 129         CHAN5G(5805, 36), /* Channel 161 */
 130         CHAN5G(5825, 37), /* Channel 165 */
 131 };
 132
 133 /* Atheros hardware rate code addition for short premble */
 134 #define SHPCHECK(__hw_rate, __flags) \
 135         ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
 136
 137 #define RATE(_bitrate, _hw_rate, _flags) {              \
 138         .bitrate        = (_bitrate),                   \
 139         .flags          = (_flags),                     \
 140         .hw_value       = (_hw_rate),                   \
 141         .hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
 142 }
 143
 144 static struct ieee80211_rate ath9k_legacy_rates[] = {
 145         RATE(10, 0x1b, 0),
 146         RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
 147         RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
 148         RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
 149         RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ |
 150                         IEEE80211_RATE_SUPPORTS_10MHZ)),
 151         RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ |
 152                         IEEE80211_RATE_SUPPORTS_10MHZ)),
 153         RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ |
 154                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 155         RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ |
 156                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 157         RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ |
 158                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 159         RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ |
 160                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 161         RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ |
 162                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 163         RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ |
 164                          IEEE80211_RATE_SUPPORTS_10MHZ)),
 165 };
 166
 167 #ifdef CONFIG_MAC80211_LEDS
 168 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
 169         { .throughput = 0 * 1024, .blink_time = 334 },
 170         { .throughput = 1 * 1024, .blink_time = 260 },
 171         { .throughput = 5 * 1024, .blink_time = 220 },
 172         { .throughput = 10 * 1024, .blink_time = 190 },
 173         { .throughput = 20 * 1024, .blink_time = 170 },
 174         { .throughput = 50 * 1024, .blink_time = 150 },
 175         { .throughput = 70 * 1024, .blink_time = 130 },
 176         { .throughput = 100 * 1024, .blink_time = 110 },
 177         { .throughput = 200 * 1024, .blink_time = 80 },
 178         { .throughput = 300 * 1024, .blink_time = 50 },
 179 };
 180 #endif
 181
 182 static void ath9k_deinit_softc(struct ath_softc *sc);
 183
 184 /*
 185  * Read and write, they both share the same lock. We do this to serialize
 186  * reads and writes on Atheros 802.11n PCI devices only. This is required
 187  * as the FIFO on these devices can only accept sanely 2 requests.
 188  */
 189
 190 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
 191 {
 192         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 193         struct ath_common *common = ath9k_hw_common(ah);
 194         struct ath_softc *sc = (struct ath_softc *) common->priv;
 195
 196         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 197                 unsigned long flags;
 198                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 199                 iowrite32(val, sc->mem + reg_offset);
 200                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 201         } else
 202                 iowrite32(val, sc->mem + reg_offset);
 203 }
 204
 205 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
 206 {
 207         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 208         struct ath_common *common = ath9k_hw_common(ah);
 209         struct ath_softc *sc = (struct ath_softc *) common->priv;
 210         u32 val;
 211
 212         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 213                 unsigned long flags;
 214                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 215                 val = ioread32(sc->mem + reg_offset);
 216                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 217         } else
 218                 val = ioread32(sc->mem + reg_offset);
 219         return val;
 220 }
 221
 222 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
 223                                     u32 set, u32 clr)
 224 {
 225         u32 val;
 226
 227         val = ioread32(sc->mem + reg_offset);
 228         val &= ~clr;
 229         val |= set;
 230         iowrite32(val, sc->mem + reg_offset);
 231
 232         return val;
 233 }
 234
 235 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 236 {
 237         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 238         struct ath_common *common = ath9k_hw_common(ah);
 239         struct ath_softc *sc = (struct ath_softc *) common->priv;
 240         unsigned long uninitialized_var(flags);
 241         u32 val;
 242
 243         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 244                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 245                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 246                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 247         } else
 248                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 249
 250         return val;
 251 }
 252
 253 /**************************/
 254 /*     Initialization     */
 255 /**************************/
 256
 257 static void setup_ht_cap(struct ath_softc *sc,
 258                          struct ieee80211_sta_ht_cap *ht_info)
 259 {
 260         struct ath_hw *ah = sc->sc_ah;
 261         struct ath_common *common = ath9k_hw_common(ah);
 262         u8 tx_streams, rx_streams;
 263         int i, max_streams;
 264
 265         ht_info->ht_supported = true;
 266         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 267                        IEEE80211_HT_CAP_SM_PS |
 268                        IEEE80211_HT_CAP_SGI_40 |
 269                        IEEE80211_HT_CAP_DSSSCCK40;
 270
 271         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
 272                 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
 273
 274         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
 275                 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
 276
 277         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 278         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 279
 280         if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
 281                 max_streams = 1;
 282         else if (AR_SREV_9462(ah))
 283                 max_streams = 2;
 284         else if (AR_SREV_9300_20_OR_LATER(ah))
 285                 max_streams = 3;
 286         else
 287                 max_streams = 2;
 288
 289         if (AR_SREV_9280_20_OR_LATER(ah)) {
 290                 if (max_streams >= 2)
 291                         ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
 292                 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
 293         }
 294
 295         /* set up supported mcs set */
 296         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 297         tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
 298         rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
 299
 300         ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
 301                 tx_streams, rx_streams);
 302
 303         if (tx_streams != rx_streams) {
 304                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 305                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 306                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 307         }
 308
 309         for (i = 0; i < rx_streams; i++)
 310                 ht_info->mcs.rx_mask[i] = 0xff;
 311
 312         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 313 }
 314
 315 static void ath9k_reg_notifier(struct wiphy *wiphy,
 316                                struct regulatory_request *request)
 317 {
 318         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 319         struct ath_softc *sc = hw->priv;
 320         struct ath_hw *ah = sc->sc_ah;
 321         struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
 322
 323         ath_reg_notifier_apply(wiphy, request, reg);
 324
 325         /* Set tx power */
 326         if (ah->curchan) {
 327                 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
 328                 ath9k_ps_wakeup(sc);
 329                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
 330                 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
 331                 /* synchronize DFS detector if regulatory domain changed */
 332                 if (sc->dfs_detector != NULL)
 333                         sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
 334                                                          request->dfs_region);
 335                 ath9k_ps_restore(sc);
 336         }
 337 }
 338
 339 /*
 340  *  This function will allocate both the DMA descriptor structure, and the
 341  *  buffers it contains.  These are used to contain the descriptors used
 342  *  by the system.
 343 */
 344 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 345                       struct list_head *head, const char *name,
 346                       int nbuf, int ndesc, bool is_tx)
 347 {
 348         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 349         u8 *ds;
 350         int i, bsize, desc_len;
 351
 352         ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
 353                 name, nbuf, ndesc);
 354
 355         INIT_LIST_HEAD(head);
 356
 357         if (is_tx)
 358                 desc_len = sc->sc_ah->caps.tx_desc_len;
 359         else
 360                 desc_len = sizeof(struct ath_desc);
 361
 362         /* ath_desc must be a multiple of DWORDs */
 363         if ((desc_len % 4) != 0) {
 364                 ath_err(common, "ath_desc not DWORD aligned\n");
 365                 BUG_ON((desc_len % 4) != 0);
 366                 return -ENOMEM;
 367         }
 368
 369         dd->dd_desc_len = desc_len * nbuf * ndesc;
 370
 371         /*
 372          * Need additional DMA memory because we can't use
 373          * descriptors that cross the 4K page boundary. Assume
 374          * one skipped descriptor per 4K page.
 375          */
 376         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 377                 u32 ndesc_skipped =
 378                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
 379                 u32 dma_len;
 380
 381                 while (ndesc_skipped) {
 382                         dma_len = ndesc_skipped * desc_len;
 383                         dd->dd_desc_len += dma_len;
 384
 385                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
 386                 }
 387         }
 388
 389         /* allocate descriptors */
 390         dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
 391                                           &dd->dd_desc_paddr, GFP_KERNEL);
 392         if (!dd->dd_desc)
 393                 return -ENOMEM;
 394
 395         ds = (u8 *) dd->dd_desc;
 396         ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
 397                 name, ds, (u32) dd->dd_desc_len,
 398                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 399
 400         /* allocate buffers */
 401         if (is_tx) {
 402                 struct ath_buf *bf;
 403
 404                 bsize = sizeof(struct ath_buf) * nbuf;
 405                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 406                 if (!bf)
 407                         return -ENOMEM;
 408
 409                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 410                         bf->bf_desc = ds;
 411                         bf->bf_daddr = DS2PHYS(dd, ds);
 412
 413                         if (!(sc->sc_ah->caps.hw_caps &
 414                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 415                                 /*
 416                                  * Skip descriptor addresses which can cause 4KB
 417                                  * boundary crossing (addr + length) with a 32 dword
 418                                  * descriptor fetch.
 419                                  */
 420                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 421                                         BUG_ON((caddr_t) bf->bf_desc >=
 422                                                    ((caddr_t) dd->dd_desc +
 423                                                 dd->dd_desc_len));
 424
 425                                         ds += (desc_len * ndesc);
 426                                         bf->bf_desc = ds;
 427                                         bf->bf_daddr = DS2PHYS(dd, ds);
 428                                 }
 429                         }
 430                         list_add_tail(&bf->list, head);
 431                 }
 432         } else {
 433                 struct ath_rxbuf *bf;
 434
 435                 bsize = sizeof(struct ath_rxbuf) * nbuf;
 436                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 437                 if (!bf)
 438                         return -ENOMEM;
 439
 440                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 441                         bf->bf_desc = ds;
 442                         bf->bf_daddr = DS2PHYS(dd, ds);
 443
 444                         if (!(sc->sc_ah->caps.hw_caps &
 445                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 446                                 /*
 447                                  * Skip descriptor addresses which can cause 4KB
 448                                  * boundary crossing (addr + length) with a 32 dword
 449                                  * descriptor fetch.
 450                                  */
 451                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 452                                         BUG_ON((caddr_t) bf->bf_desc >=
 453                                                    ((caddr_t) dd->dd_desc +
 454                                                 dd->dd_desc_len));
 455
 456                                         ds += (desc_len * ndesc);
 457                                         bf->bf_desc = ds;
 458                                         bf->bf_daddr = DS2PHYS(dd, ds);
 459                                 }
 460                         }
 461                         list_add_tail(&bf->list, head);
 462                 }
 463         }
 464         return 0;
 465 }
 466
 467 static int ath9k_init_queues(struct ath_softc *sc)
 468 {
 469         int i = 0;
 470
 471         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
 472         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 473
 474         ath_cabq_update(sc);
 475
 476         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
 477
 478         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 479                 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
 480                 sc->tx.txq_map[i]->mac80211_qnum = i;
 481                 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
 482         }
 483         return 0;
 484 }
 485
 486 static int ath9k_init_channels_rates(struct ath_softc *sc)
 487 {
 488         void *channels;
 489
 490         BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
 491                      ARRAY_SIZE(ath9k_5ghz_chantable) !=
 492                      ATH9K_NUM_CHANNELS);
 493
 494         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
 495                 channels = devm_kzalloc(sc->dev,
 496                         sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
 497                 if (!channels)
 498                     return -ENOMEM;
 499
 500                 memcpy(channels, ath9k_2ghz_chantable,
 501                        sizeof(ath9k_2ghz_chantable));
 502                 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
 503                 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
 504                 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
 505                         ARRAY_SIZE(ath9k_2ghz_chantable);
 506                 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
 507                 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
 508                         ARRAY_SIZE(ath9k_legacy_rates);
 509         }
 510
 511         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
 512                 channels = devm_kzalloc(sc->dev,
 513                         sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
 514                 if (!channels)
 515                         return -ENOMEM;
 516
 517                 memcpy(channels, ath9k_5ghz_chantable,
 518                        sizeof(ath9k_5ghz_chantable));
 519                 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
 520                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
 521                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
 522                         ARRAY_SIZE(ath9k_5ghz_chantable);
 523                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
 524                         ath9k_legacy_rates + 4;
 525                 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
 526                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
 527         }
 528         return 0;
 529 }
 530
 531 static void ath9k_init_misc(struct ath_softc *sc)
 532 {
 533         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 534         int i = 0;
 535
 536         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
 537
 538         sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
 539         sc->config.txpowlimit = ATH_TXPOWER_MAX;
 540         memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 541         sc->beacon.slottime = ATH9K_SLOT_TIME_9;
 542
 543         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
 544                 sc->beacon.bslot[i] = NULL;
 545
 546         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 547                 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 548
 549         sc->spec_config.enabled = 0;
 550         sc->spec_config.short_repeat = true;
 551         sc->spec_config.count = 8;
 552         sc->spec_config.endless = false;
 553         sc->spec_config.period = 0xFF;
 554         sc->spec_config.fft_period = 0xF;
 555 }
 556
 557 static void ath9k_init_platform(struct ath_softc *sc)
 558 {
 559         struct ath_hw *ah = sc->sc_ah;
 560         struct ath9k_hw_capabilities *pCap = &ah->caps;
 561         struct ath_common *common = ath9k_hw_common(ah);
 562
 563         if (common->bus_ops->ath_bus_type != ATH_PCI)
 564                 return;
 565
 566         if (sc->driver_data & (ATH9K_PCI_CUS198 |
 567                                ATH9K_PCI_CUS230)) {
 568                 ah->config.xlna_gpio = 9;
 569                 ah->config.xatten_margin_cfg = true;
 570                 ah->config.alt_mingainidx = true;
 571                 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
 572                 sc->ant_comb.low_rssi_thresh = 20;
 573                 sc->ant_comb.fast_div_bias = 3;
 574
 575                 ath_info(common, "Set parameters for %s\n",
 576                          (sc->driver_data & ATH9K_PCI_CUS198) ?
 577                          "CUS198" : "CUS230");
 578         }
 579
 580         if (sc->driver_data & ATH9K_PCI_CUS217)
 581                 ath_info(common, "CUS217 card detected\n");
 582
 583         if (sc->driver_data & ATH9K_PCI_CUS252)
 584                 ath_info(common, "CUS252 card detected\n");
 585
 586         if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
 587                 ath_info(common, "WB335 1-ANT card detected\n");
 588
 589         if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
 590                 ath_info(common, "WB335 2-ANT card detected\n");
 591
 592         /*
 593          * Some WB335 cards do not support antenna diversity. Since
 594          * we use a hardcoded value for AR9565 instead of using the
 595          * EEPROM/OTP data, remove the combining feature from
 596          * the HW capabilities bitmap.
 597          */
 598         if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
 599                 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
 600                         pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
 601         }
 602
 603         if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
 604                 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
 605                 ath_info(common, "Set BT/WLAN RX diversity capability\n");
 606         }
 607
 608         if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
 609                 ah->config.pcie_waen = 0x0040473b;
 610                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
 611         }
 612 }
 613
 614 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
 615                                     void *ctx)
 616 {
 617         struct ath9k_eeprom_ctx *ec = ctx;
 618
 619         if (eeprom_blob)
 620                 ec->ah->eeprom_blob = eeprom_blob;
 621
 622         complete(&ec->complete);
 623 }
 624
 625 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
 626 {
 627         struct ath9k_eeprom_ctx ec;
 628         struct ath_hw *ah = ah = sc->sc_ah;
 629         int err;
 630
 631         /* try to load the EEPROM content asynchronously */
 632         init_completion(&ec.complete);
 633         ec.ah = sc->sc_ah;
 634
 635         err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
 636                                       &ec, ath9k_eeprom_request_cb);
 637         if (err < 0) {
 638                 ath_err(ath9k_hw_common(ah),
 639                         "EEPROM request failed\n");
 640                 return err;
 641         }
 642
 643         wait_for_completion(&ec.complete);
 644
 645         if (!ah->eeprom_blob) {
 646                 ath_err(ath9k_hw_common(ah),
 647                         "Unable to load EEPROM file %s\n", name);
 648                 return -EINVAL;
 649         }
 650
 651         return 0;
 652 }
 653
 654 static void ath9k_eeprom_release(struct ath_softc *sc)
 655 {
 656         release_firmware(sc->sc_ah->eeprom_blob);
 657 }
 658
 659 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
 660                             const struct ath_bus_ops *bus_ops)
 661 {
 662         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 663         struct ath_hw *ah = NULL;
 664         struct ath9k_hw_capabilities *pCap;
 665         struct ath_common *common;
 666         int ret = 0, i;
 667         int csz = 0;
 668
 669         ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
 670         if (!ah)
 671                 return -ENOMEM;
 672
 673         ah->dev = sc->dev;
 674         ah->hw = sc->hw;
 675         ah->hw_version.devid = devid;
 676         ah->reg_ops.read = ath9k_ioread32;
 677         ah->reg_ops.write = ath9k_iowrite32;
 678         ah->reg_ops.rmw = ath9k_reg_rmw;
 679         atomic_set(&ah->intr_ref_cnt, -1);
 680         sc->sc_ah = ah;
 681         pCap = &ah->caps;
 682
 683         sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET);
 684
 685         if (!pdata) {
 686                 ah->ah_flags |= AH_USE_EEPROM;
 687                 sc->sc_ah->led_pin = -1;
 688         } else {
 689                 sc->sc_ah->gpio_mask = pdata->gpio_mask;
 690                 sc->sc_ah->gpio_val = pdata->gpio_val;
 691                 sc->sc_ah->led_pin = pdata->led_pin;
 692                 ah->is_clk_25mhz = pdata->is_clk_25mhz;
 693                 ah->get_mac_revision = pdata->get_mac_revision;
 694                 ah->external_reset = pdata->external_reset;
 695         }
 696
 697         common = ath9k_hw_common(ah);
 698         common->ops = &ah->reg_ops;
 699         common->bus_ops = bus_ops;
 700         common->ah = ah;
 701         common->hw = sc->hw;
 702         common->priv = sc;
 703         common->debug_mask = ath9k_debug;
 704         common->btcoex_enabled = ath9k_btcoex_enable == 1;
 705         common->disable_ani = false;
 706
 707         /*
 708          * Platform quirks.
 709          */
 710         ath9k_init_platform(sc);
 711
 712         /*
 713          * Enable WLAN/BT RX Antenna diversity only when:
 714          *
 715          * - BTCOEX is disabled.
 716          * - the user manually requests the feature.
 717          * - the HW cap is set using the platform data.
 718          */
 719         if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
 720             (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
 721                 common->bt_ant_diversity = 1;
 722
 723         spin_lock_init(&common->cc_lock);
 724
 725         spin_lock_init(&sc->sc_serial_rw);
 726         spin_lock_init(&sc->sc_pm_lock);
 727         mutex_init(&sc->mutex);
 728         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
 729         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
 730                      (unsigned long)sc);
 731
 732         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
 733         INIT_WORK(&sc->hw_check_work, ath_hw_check);
 734         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
 735         INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
 736         setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
 737
 738         /*
 739          * Cache line size is used to size and align various
 740          * structures used to communicate with the hardware.
 741          */
 742         ath_read_cachesize(common, &csz);
 743         common->cachelsz = csz << 2; /* convert to bytes */
 744
 745         if (pdata && pdata->eeprom_name) {
 746                 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
 747                 if (ret)
 748                         return ret;
 749         }
 750
 751         /* Initializes the hardware for all supported chipsets */
 752         ret = ath9k_hw_init(ah);
 753         if (ret)
 754                 goto err_hw;
 755
 756         if (pdata && pdata->macaddr)
 757                 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
 758
 759         ret = ath9k_init_queues(sc);
 760         if (ret)
 761                 goto err_queues;
 762
 763         ret =  ath9k_init_btcoex(sc);
 764         if (ret)
 765                 goto err_btcoex;
 766
 767         ret = ath9k_init_channels_rates(sc);
 768         if (ret)
 769                 goto err_btcoex;
 770
 771         ath9k_cmn_init_crypto(sc->sc_ah);
 772         ath9k_init_misc(sc);
 773         ath_fill_led_pin(sc);
 774
 775         if (common->bus_ops->aspm_init)
 776                 common->bus_ops->aspm_init(common);
 777
 778         return 0;
 779
 780 err_btcoex:
 781         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 782                 if (ATH_TXQ_SETUP(sc, i))
 783                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 784 err_queues:
 785         ath9k_hw_deinit(ah);
 786 err_hw:
 787         ath9k_eeprom_release(sc);
 788         return ret;
 789 }
 790
 791 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
 792 {
 793         struct ieee80211_supported_band *sband;
 794         struct ieee80211_channel *chan;
 795         struct ath_hw *ah = sc->sc_ah;
 796         struct cfg80211_chan_def chandef;
 797         int i;
 798
 799         sband = &sc->sbands[band];
 800         for (i = 0; i < sband->n_channels; i++) {
 801                 chan = &sband->channels[i];
 802                 ah->curchan = &ah->channels[chan->hw_value];
 803                 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
 804                 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
 805                 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
 806         }
 807 }
 808
 809 static void ath9k_init_txpower_limits(struct ath_softc *sc)
 810 {
 811         struct ath_hw *ah = sc->sc_ah;
 812         struct ath9k_channel *curchan = ah->curchan;
 813
 814         if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 815                 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
 816         if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 817                 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
 818
 819         ah->curchan = curchan;
 820 }
 821
 822 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
 823 {
 824         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
 825                 return;
 826
 827         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 828                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
 829         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 830                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
 831 }
 832
 833 static const struct ieee80211_iface_limit if_limits[] = {
 834         { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) |
 835                                  BIT(NL80211_IFTYPE_P2P_CLIENT) |
 836                                  BIT(NL80211_IFTYPE_WDS) },
 837         { .max = 8,     .types =
 838 #ifdef CONFIG_MAC80211_MESH
 839                                  BIT(NL80211_IFTYPE_MESH_POINT) |
 840 #endif
 841                                  BIT(NL80211_IFTYPE_AP) |
 842                                  BIT(NL80211_IFTYPE_P2P_GO) },
 843 };
 844
 845
 846 static const struct ieee80211_iface_limit if_dfs_limits[] = {
 847         { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
 848 };
 849
 850 static const struct ieee80211_iface_combination if_comb[] = {
 851         {
 852                 .limits = if_limits,
 853                 .n_limits = ARRAY_SIZE(if_limits),
 854                 .max_interfaces = 2048,
 855                 .num_different_channels = 1,
 856                 .beacon_int_infra_match = true,
 857         },
 858         {
 859                 .limits = if_dfs_limits,
 860                 .n_limits = ARRAY_SIZE(if_dfs_limits),
 861                 .max_interfaces = 1,
 862                 .num_different_channels = 1,
 863                 .beacon_int_infra_match = true,
 864                 .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
 865                                         BIT(NL80211_CHAN_HT20),
 866         }
 867 };
 868
 869 #ifdef CONFIG_PM
 870 static const struct wiphy_wowlan_support ath9k_wowlan_support = {
 871         .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
 872         .n_patterns = MAX_NUM_USER_PATTERN,
 873         .pattern_min_len = 1,
 874         .pattern_max_len = MAX_PATTERN_SIZE,
 875 };
 876 #endif
 877
 878 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 879 {
 880         struct ath_hw *ah = sc->sc_ah;
 881         struct ath_common *common = ath9k_hw_common(ah);
 882
 883         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 884                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
 885                 IEEE80211_HW_SIGNAL_DBM |
 886                 IEEE80211_HW_SUPPORTS_PS |
 887                 IEEE80211_HW_PS_NULLFUNC_STACK |
 888                 IEEE80211_HW_SPECTRUM_MGMT |
 889                 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
 890                 IEEE80211_HW_SUPPORTS_RC_TABLE |
 891                 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
 892
 893         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 894                 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
 895
 896                 if (AR_SREV_9280_20_OR_LATER(ah))
 897                         hw->radiotap_mcs_details |=
 898                                 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
 899         }
 900
 901         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
 902                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
 903
 904         hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
 905
 906         hw->wiphy->interface_modes =
 907                 BIT(NL80211_IFTYPE_P2P_GO) |
 908                 BIT(NL80211_IFTYPE_P2P_CLIENT) |
 909                 BIT(NL80211_IFTYPE_AP) |
 910                 BIT(NL80211_IFTYPE_WDS) |
 911                 BIT(NL80211_IFTYPE_STATION) |
 912                 BIT(NL80211_IFTYPE_ADHOC) |
 913                 BIT(NL80211_IFTYPE_MESH_POINT);
 914
 915         hw->wiphy->iface_combinations = if_comb;
 916         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 917
 918         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 919
 920         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 921         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
 922         hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
 923         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
 924         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
 925
 926 #ifdef CONFIG_PM_SLEEP
 927         if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
 928             (sc->driver_data & ATH9K_PCI_WOW) &&
 929             device_can_wakeup(sc->dev))
 930                 hw->wiphy->wowlan = &ath9k_wowlan_support;
 931
 932         atomic_set(&sc->wow_sleep_proc_intr, -1);
 933         atomic_set(&sc->wow_got_bmiss_intr, -1);
 934 #endif
 935
 936         hw->queues = 4;
 937         hw->max_rates = 4;
 938         hw->channel_change_time = 5000;
 939         hw->max_listen_interval = 1;
 940         hw->max_rate_tries = 10;
 941         hw->sta_data_size = sizeof(struct ath_node);
 942         hw->vif_data_size = sizeof(struct ath_vif);
 943
 944         hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
 945         hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
 946
 947         /* single chain devices with rx diversity */
 948         if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 949                 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
 950
 951         sc->ant_rx = hw->wiphy->available_antennas_rx;
 952         sc->ant_tx = hw->wiphy->available_antennas_tx;
 953
 954         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 955                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 956                         &sc->sbands[IEEE80211_BAND_2GHZ];
 957         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 958                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 959                         &sc->sbands[IEEE80211_BAND_5GHZ];
 960
 961         ath9k_reload_chainmask_settings(sc);
 962
 963         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 964 }
 965
 966 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 967                     const struct ath_bus_ops *bus_ops)
 968 {
 969         struct ieee80211_hw *hw = sc->hw;
 970         struct ath_common *common;
 971         struct ath_hw *ah;
 972         int error = 0;
 973         struct ath_regulatory *reg;
 974
 975         /* Bring up device */
 976         error = ath9k_init_softc(devid, sc, bus_ops);
 977         if (error)
 978                 return error;
 979
 980         ah = sc->sc_ah;
 981         common = ath9k_hw_common(ah);
 982         ath9k_set_hw_capab(sc, hw);
 983
 984         /* Initialize regulatory */
 985         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
 986                               ath9k_reg_notifier);
 987         if (error)
 988                 goto deinit;
 989
 990         reg = &common->regulatory;
 991
 992         /* Setup TX DMA */
 993         error = ath_tx_init(sc, ATH_TXBUF);
 994         if (error != 0)
 995                 goto deinit;
 996
 997         /* Setup RX DMA */
 998         error = ath_rx_init(sc, ATH_RXBUF);
 999         if (error != 0)
1000                 goto deinit;
1001
1002         ath9k_init_txpower_limits(sc);
1003
1004 #ifdef CONFIG_MAC80211_LEDS
1005         /* must be initialized before ieee80211_register_hw */
1006         sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1007                 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1008                 ARRAY_SIZE(ath9k_tpt_blink));
1009 #endif
1010
1011         /* Register with mac80211 */
1012         error = ieee80211_register_hw(hw);
1013         if (error)
1014                 goto rx_cleanup;
1015
1016         error = ath9k_init_debug(ah);
1017         if (error) {
1018                 ath_err(common, "Unable to create debugfs files\n");
1019                 goto unregister;
1020         }
1021
1022         /* Handle world regulatory */
1023         if (!ath_is_world_regd(reg)) {
1024                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1025                 if (error)
1026                         goto debug_cleanup;
1027         }
1028
1029         ath_init_leds(sc);
1030         ath_start_rfkill_poll(sc);
1031
1032         return 0;
1033
1034 debug_cleanup:
1035         ath9k_deinit_debug(sc);
1036 unregister:
1037         ieee80211_unregister_hw(hw);
1038 rx_cleanup:
1039         ath_rx_cleanup(sc);
1040 deinit:
1041         ath9k_deinit_softc(sc);
1042         return error;
1043 }
1044
1045 /*****************************/
1046 /*     De-Initialization     */
1047 /*****************************/
1048
1049 static void ath9k_deinit_softc(struct ath_softc *sc)
1050 {
1051         int i = 0;
1052
1053         ath9k_deinit_btcoex(sc);
1054
1055         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1056                 if (ATH_TXQ_SETUP(sc, i))
1057                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1058
1059         ath9k_hw_deinit(sc->sc_ah);
1060         if (sc->dfs_detector != NULL)
1061                 sc->dfs_detector->exit(sc->dfs_detector);
1062
1063         ath9k_eeprom_release(sc);
1064 }
1065
1066 void ath9k_deinit_device(struct ath_softc *sc)
1067 {
1068         struct ieee80211_hw *hw = sc->hw;
1069
1070         ath9k_ps_wakeup(sc);
1071
1072         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1073         ath_deinit_leds(sc);
1074
1075         ath9k_ps_restore(sc);
1076
1077         ath9k_deinit_debug(sc);
1078         ieee80211_unregister_hw(hw);
1079         ath_rx_cleanup(sc);
1080         ath9k_deinit_softc(sc);
1081 }
1082
1083 /************************/
1084 /*     Module Hooks     */
1085 /************************/
1086
1087 static int __init ath9k_init(void)
1088 {
1089         int error;
1090
1091         /* Register rate control algorithm */
1092         error = ath_rate_control_register();
1093         if (error != 0) {
1094                 pr_err("Unable to register rate control algorithm: %d\n",
1095                        error);
1096                 goto err_out;
1097         }
1098
1099         error = ath_pci_init();
1100         if (error < 0) {
1101                 pr_err("No PCI devices found, driver not installed\n");
1102                 error = -ENODEV;
1103                 goto err_rate_unregister;
1104         }
1105
1106         error = ath_ahb_init();
1107         if (error < 0) {
1108                 error = -ENODEV;
1109                 goto err_pci_exit;
1110         }
1111
1112         return 0;
1113
1114  err_pci_exit:
1115         ath_pci_exit();
1116
1117  err_rate_unregister:
1118         ath_rate_control_unregister();
1119  err_out:
1120         return error;
1121 }
1122 module_init(ath9k_init);
1123
1124 static void __exit ath9k_exit(void)
1125 {
1126         is_ath9k_unloaded = true;
1127         ath_ahb_exit();
1128         ath_pci_exit();
1129         ath_rate_control_unregister();
1130         pr_info("%s: Driver unloaded\n", dev_info);
1131 }
1132 module_exit(ath9k_exit);