2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/ath9k_platform.h>
23 static char *dev_info = "ath9k";
25 MODULE_AUTHOR("Atheros Communications");
26 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
27 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
28 MODULE_LICENSE("Dual BSD/GPL");
30 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
31 module_param_named(debug, ath9k_debug, uint, 0);
32 MODULE_PARM_DESC(debug, "Debugging mask");
34 int ath9k_modparam_nohwcrypt;
35 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
36 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
39 module_param_named(blink, led_blink, int, 0444);
40 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
42 static int ath9k_btcoex_enable;
43 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
44 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
46 bool is_ath9k_unloaded;
47 /* We use the hw_value as an index into our private channel structure */
49 #define CHAN2G(_freq, _idx) { \
50 .band = IEEE80211_BAND_2GHZ, \
51 .center_freq = (_freq), \
56 #define CHAN5G(_freq, _idx) { \
57 .band = IEEE80211_BAND_5GHZ, \
58 .center_freq = (_freq), \
63 /* Some 2 GHz radios are actually tunable on 2312-2732
64 * on 5 MHz steps, we support the channels which we know
65 * we have calibration data for all cards though to make
67 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
68 CHAN2G(2412, 0), /* Channel 1 */
69 CHAN2G(2417, 1), /* Channel 2 */
70 CHAN2G(2422, 2), /* Channel 3 */
71 CHAN2G(2427, 3), /* Channel 4 */
72 CHAN2G(2432, 4), /* Channel 5 */
73 CHAN2G(2437, 5), /* Channel 6 */
74 CHAN2G(2442, 6), /* Channel 7 */
75 CHAN2G(2447, 7), /* Channel 8 */
76 CHAN2G(2452, 8), /* Channel 9 */
77 CHAN2G(2457, 9), /* Channel 10 */
78 CHAN2G(2462, 10), /* Channel 11 */
79 CHAN2G(2467, 11), /* Channel 12 */
80 CHAN2G(2472, 12), /* Channel 13 */
81 CHAN2G(2484, 13), /* Channel 14 */
84 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
85 * on 5 MHz steps, we support the channels which we know
86 * we have calibration data for all cards though to make
88 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
89 /* _We_ call this UNII 1 */
90 CHAN5G(5180, 14), /* Channel 36 */
91 CHAN5G(5200, 15), /* Channel 40 */
92 CHAN5G(5220, 16), /* Channel 44 */
93 CHAN5G(5240, 17), /* Channel 48 */
94 /* _We_ call this UNII 2 */
95 CHAN5G(5260, 18), /* Channel 52 */
96 CHAN5G(5280, 19), /* Channel 56 */
97 CHAN5G(5300, 20), /* Channel 60 */
98 CHAN5G(5320, 21), /* Channel 64 */
99 /* _We_ call this "Middle band" */
100 CHAN5G(5500, 22), /* Channel 100 */
101 CHAN5G(5520, 23), /* Channel 104 */
102 CHAN5G(5540, 24), /* Channel 108 */
103 CHAN5G(5560, 25), /* Channel 112 */
104 CHAN5G(5580, 26), /* Channel 116 */
105 CHAN5G(5600, 27), /* Channel 120 */
106 CHAN5G(5620, 28), /* Channel 124 */
107 CHAN5G(5640, 29), /* Channel 128 */
108 CHAN5G(5660, 30), /* Channel 132 */
109 CHAN5G(5680, 31), /* Channel 136 */
110 CHAN5G(5700, 32), /* Channel 140 */
111 /* _We_ call this UNII 3 */
112 CHAN5G(5745, 33), /* Channel 149 */
113 CHAN5G(5765, 34), /* Channel 153 */
114 CHAN5G(5785, 35), /* Channel 157 */
115 CHAN5G(5805, 36), /* Channel 161 */
116 CHAN5G(5825, 37), /* Channel 165 */
119 /* Atheros hardware rate code addition for short premble */
120 #define SHPCHECK(__hw_rate, __flags) \
121 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
123 #define RATE(_bitrate, _hw_rate, _flags) { \
124 .bitrate = (_bitrate), \
126 .hw_value = (_hw_rate), \
127 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
130 static struct ieee80211_rate ath9k_legacy_rates[] = {
132 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
133 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
145 #ifdef CONFIG_MAC80211_LEDS
146 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
147 { .throughput = 0 * 1024, .blink_time = 334 },
148 { .throughput = 1 * 1024, .blink_time = 260 },
149 { .throughput = 5 * 1024, .blink_time = 220 },
150 { .throughput = 10 * 1024, .blink_time = 190 },
151 { .throughput = 20 * 1024, .blink_time = 170 },
152 { .throughput = 50 * 1024, .blink_time = 150 },
153 { .throughput = 70 * 1024, .blink_time = 130 },
154 { .throughput = 100 * 1024, .blink_time = 110 },
155 { .throughput = 200 * 1024, .blink_time = 80 },
156 { .throughput = 300 * 1024, .blink_time = 50 },
160 static void ath9k_deinit_softc(struct ath_softc *sc);
163 * Read and write, they both share the same lock. We do this to serialize
164 * reads and writes on Atheros 802.11n PCI devices only. This is required
165 * as the FIFO on these devices can only accept sanely 2 requests.
168 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
170 struct ath_hw *ah = (struct ath_hw *) hw_priv;
171 struct ath_common *common = ath9k_hw_common(ah);
172 struct ath_softc *sc = (struct ath_softc *) common->priv;
174 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
176 spin_lock_irqsave(&sc->sc_serial_rw, flags);
177 iowrite32(val, sc->mem + reg_offset);
178 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
180 iowrite32(val, sc->mem + reg_offset);
183 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
185 struct ath_hw *ah = (struct ath_hw *) hw_priv;
186 struct ath_common *common = ath9k_hw_common(ah);
187 struct ath_softc *sc = (struct ath_softc *) common->priv;
190 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
192 spin_lock_irqsave(&sc->sc_serial_rw, flags);
193 val = ioread32(sc->mem + reg_offset);
194 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
196 val = ioread32(sc->mem + reg_offset);
200 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
205 val = ioread32(sc->mem + reg_offset);
208 iowrite32(val, sc->mem + reg_offset);
213 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
215 struct ath_hw *ah = (struct ath_hw *) hw_priv;
216 struct ath_common *common = ath9k_hw_common(ah);
217 struct ath_softc *sc = (struct ath_softc *) common->priv;
218 unsigned long uninitialized_var(flags);
221 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
222 spin_lock_irqsave(&sc->sc_serial_rw, flags);
223 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
224 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
226 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
231 /**************************/
233 /**************************/
235 static void setup_ht_cap(struct ath_softc *sc,
236 struct ieee80211_sta_ht_cap *ht_info)
238 struct ath_hw *ah = sc->sc_ah;
239 struct ath_common *common = ath9k_hw_common(ah);
240 u8 tx_streams, rx_streams;
243 ht_info->ht_supported = true;
244 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
245 IEEE80211_HT_CAP_SM_PS |
246 IEEE80211_HT_CAP_SGI_40 |
247 IEEE80211_HT_CAP_DSSSCCK40;
249 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
250 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
252 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
253 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
255 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
256 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
258 if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
260 else if (AR_SREV_9300_20_OR_LATER(ah))
265 if (AR_SREV_9280_20_OR_LATER(ah)) {
266 if (max_streams >= 2)
267 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
268 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
271 /* set up supported mcs set */
272 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
273 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
274 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
276 ath_dbg(common, ATH_DBG_CONFIG,
277 "TX streams %d, RX streams: %d\n",
278 tx_streams, rx_streams);
280 if (tx_streams != rx_streams) {
281 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
282 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
283 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
286 for (i = 0; i < rx_streams; i++)
287 ht_info->mcs.rx_mask[i] = 0xff;
289 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
292 static int ath9k_reg_notifier(struct wiphy *wiphy,
293 struct regulatory_request *request)
295 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
296 struct ath_softc *sc = hw->priv;
297 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
299 return ath_reg_notifier_apply(wiphy, request, reg);
303 * This function will allocate both the DMA descriptor structure, and the
304 * buffers it contains. These are used to contain the descriptors used
307 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
308 struct list_head *head, const char *name,
309 int nbuf, int ndesc, bool is_tx)
311 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
314 int i, bsize, error, desc_len;
316 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
319 INIT_LIST_HEAD(head);
322 desc_len = sc->sc_ah->caps.tx_desc_len;
324 desc_len = sizeof(struct ath_desc);
326 /* ath_desc must be a multiple of DWORDs */
327 if ((desc_len % 4) != 0) {
328 ath_err(common, "ath_desc not DWORD aligned\n");
329 BUG_ON((desc_len % 4) != 0);
334 dd->dd_desc_len = desc_len * nbuf * ndesc;
337 * Need additional DMA memory because we can't use
338 * descriptors that cross the 4K page boundary. Assume
339 * one skipped descriptor per 4K page.
341 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
343 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
346 while (ndesc_skipped) {
347 dma_len = ndesc_skipped * desc_len;
348 dd->dd_desc_len += dma_len;
350 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
354 /* allocate descriptors */
355 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
356 &dd->dd_desc_paddr, GFP_KERNEL);
357 if (dd->dd_desc == NULL) {
361 ds = (u8 *) dd->dd_desc;
362 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
363 name, ds, (u32) dd->dd_desc_len,
364 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
366 /* allocate buffers */
367 bsize = sizeof(struct ath_buf) * nbuf;
368 bf = kzalloc(bsize, GFP_KERNEL);
375 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
377 bf->bf_daddr = DS2PHYS(dd, ds);
379 if (!(sc->sc_ah->caps.hw_caps &
380 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
382 * Skip descriptor addresses which can cause 4KB
383 * boundary crossing (addr + length) with a 32 dword
386 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
387 BUG_ON((caddr_t) bf->bf_desc >=
388 ((caddr_t) dd->dd_desc +
391 ds += (desc_len * ndesc);
393 bf->bf_daddr = DS2PHYS(dd, ds);
396 list_add_tail(&bf->list, head);
400 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
403 memset(dd, 0, sizeof(*dd));
407 void ath9k_init_crypto(struct ath_softc *sc)
409 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
412 /* Get the hardware key cache size. */
413 common->keymax = AR_KEYTABLE_SIZE;
416 * Reset the key cache since some parts do not
417 * reset the contents on initial power up.
419 for (i = 0; i < common->keymax; i++)
420 ath_hw_keyreset(common, (u16) i);
423 * Check whether the separate key cache entries
424 * are required to handle both tx+rx MIC keys.
425 * With split mic keys the number of stations is limited
426 * to 27 otherwise 59.
428 if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
429 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
432 static int ath9k_init_btcoex(struct ath_softc *sc)
437 switch (sc->sc_ah->btcoex_hw.scheme) {
438 case ATH_BTCOEX_CFG_NONE:
440 case ATH_BTCOEX_CFG_2WIRE:
441 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
443 case ATH_BTCOEX_CFG_3WIRE:
444 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
445 r = ath_init_btcoex_timer(sc);
448 txq = sc->tx.txq_map[WME_AC_BE];
449 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
450 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
460 static int ath9k_init_queues(struct ath_softc *sc)
464 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
465 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
467 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
470 for (i = 0; i < WME_NUM_AC; i++) {
471 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
472 sc->tx.txq_map[i]->mac80211_qnum = i;
477 static int ath9k_init_channels_rates(struct ath_softc *sc)
481 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
482 ARRAY_SIZE(ath9k_5ghz_chantable) !=
485 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
486 channels = kmemdup(ath9k_2ghz_chantable,
487 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
491 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
492 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
493 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
494 ARRAY_SIZE(ath9k_2ghz_chantable);
495 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
496 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
497 ARRAY_SIZE(ath9k_legacy_rates);
500 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
501 channels = kmemdup(ath9k_5ghz_chantable,
502 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
504 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
505 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
509 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
510 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
511 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
512 ARRAY_SIZE(ath9k_5ghz_chantable);
513 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
514 ath9k_legacy_rates + 4;
515 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
516 ARRAY_SIZE(ath9k_legacy_rates) - 4;
521 static void ath9k_init_misc(struct ath_softc *sc)
523 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
525 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
527 sc->config.txpowlimit = ATH_TXPOWER_MAX;
529 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
530 sc->sc_flags |= SC_OP_TXAGGR;
531 sc->sc_flags |= SC_OP_RXAGGR;
534 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
535 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
537 ath9k_hw_set_diversity(sc->sc_ah, true);
538 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
540 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
542 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
544 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
545 sc->beacon.bslot[i] = NULL;
547 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
548 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
551 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
552 const struct ath_bus_ops *bus_ops)
554 struct ath9k_platform_data *pdata = sc->dev->platform_data;
555 struct ath_hw *ah = NULL;
556 struct ath_common *common;
560 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
565 ah->hw_version.devid = devid;
566 ah->hw_version.subsysid = subsysid;
567 ah->reg_ops.read = ath9k_ioread32;
568 ah->reg_ops.write = ath9k_iowrite32;
569 ah->reg_ops.rmw = ath9k_reg_rmw;
573 ah->ah_flags |= AH_USE_EEPROM;
574 sc->sc_ah->led_pin = -1;
576 sc->sc_ah->gpio_mask = pdata->gpio_mask;
577 sc->sc_ah->gpio_val = pdata->gpio_val;
578 sc->sc_ah->led_pin = pdata->led_pin;
579 ah->is_clk_25mhz = pdata->is_clk_25mhz;
580 ah->get_mac_revision = pdata->get_mac_revision;
581 ah->external_reset = pdata->external_reset;
584 common = ath9k_hw_common(ah);
585 common->ops = &ah->reg_ops;
586 common->bus_ops = bus_ops;
590 common->debug_mask = ath9k_debug;
591 common->btcoex_enabled = ath9k_btcoex_enable == 1;
592 common->disable_ani = false;
593 spin_lock_init(&common->cc_lock);
595 spin_lock_init(&sc->sc_serial_rw);
596 spin_lock_init(&sc->sc_pm_lock);
597 mutex_init(&sc->mutex);
598 #ifdef CONFIG_ATH9K_DEBUGFS
599 spin_lock_init(&sc->nodes_lock);
600 INIT_LIST_HEAD(&sc->nodes);
602 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
603 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
607 * Cache line size is used to size and align various
608 * structures used to communicate with the hardware.
610 ath_read_cachesize(common, &csz);
611 common->cachelsz = csz << 2; /* convert to bytes */
613 /* Initializes the hardware for all supported chipsets */
614 ret = ath9k_hw_init(ah);
618 if (pdata && pdata->macaddr)
619 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
621 ret = ath9k_init_queues(sc);
625 ret = ath9k_init_btcoex(sc);
629 ret = ath9k_init_channels_rates(sc);
633 ath9k_init_crypto(sc);
639 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
640 if (ATH_TXQ_SETUP(sc, i))
641 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
652 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
654 struct ieee80211_supported_band *sband;
655 struct ieee80211_channel *chan;
656 struct ath_hw *ah = sc->sc_ah;
657 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
660 sband = &sc->sbands[band];
661 for (i = 0; i < sband->n_channels; i++) {
662 chan = &sband->channels[i];
663 ah->curchan = &ah->channels[chan->hw_value];
664 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
665 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
666 chan->max_power = reg->max_power_level / 2;
670 static void ath9k_init_txpower_limits(struct ath_softc *sc)
672 struct ath_hw *ah = sc->sc_ah;
673 struct ath9k_channel *curchan = ah->curchan;
675 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
676 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
677 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
678 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
680 ah->curchan = curchan;
683 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
685 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
687 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
688 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
689 IEEE80211_HW_SIGNAL_DBM |
690 IEEE80211_HW_SUPPORTS_PS |
691 IEEE80211_HW_PS_NULLFUNC_STACK |
692 IEEE80211_HW_SPECTRUM_MGMT |
693 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
695 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
696 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
698 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
699 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
701 hw->wiphy->interface_modes =
702 BIT(NL80211_IFTYPE_P2P_GO) |
703 BIT(NL80211_IFTYPE_P2P_CLIENT) |
704 BIT(NL80211_IFTYPE_AP) |
705 BIT(NL80211_IFTYPE_WDS) |
706 BIT(NL80211_IFTYPE_STATION) |
707 BIT(NL80211_IFTYPE_ADHOC) |
708 BIT(NL80211_IFTYPE_MESH_POINT);
710 if (AR_SREV_5416(sc->sc_ah))
711 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
713 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
717 hw->channel_change_time = 5000;
718 hw->max_listen_interval = 10;
719 hw->max_rate_tries = 10;
720 hw->sta_data_size = sizeof(struct ath_node);
721 hw->vif_data_size = sizeof(struct ath_vif);
723 #ifdef CONFIG_ATH9K_RATE_CONTROL
724 hw->rate_control_algorithm = "ath9k_rate_control";
727 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
728 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
729 &sc->sbands[IEEE80211_BAND_2GHZ];
730 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
731 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
732 &sc->sbands[IEEE80211_BAND_5GHZ];
734 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
735 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
736 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
737 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
738 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
741 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
744 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
745 const struct ath_bus_ops *bus_ops)
747 struct ieee80211_hw *hw = sc->hw;
748 struct ath_common *common;
751 struct ath_regulatory *reg;
753 /* Bring up device */
754 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
759 common = ath9k_hw_common(ah);
760 ath9k_set_hw_capab(sc, hw);
762 /* Initialize regulatory */
763 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
768 reg = &common->regulatory;
771 error = ath_tx_init(sc, ATH_TXBUF);
776 error = ath_rx_init(sc, ATH_RXBUF);
780 ath9k_init_txpower_limits(sc);
782 #ifdef CONFIG_MAC80211_LEDS
783 /* must be initialized before ieee80211_register_hw */
784 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
785 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
786 ARRAY_SIZE(ath9k_tpt_blink));
789 /* Register with mac80211 */
790 error = ieee80211_register_hw(hw);
794 error = ath9k_init_debug(ah);
796 ath_err(common, "Unable to create debugfs files\n");
800 /* Handle world regulatory */
801 if (!ath_is_world_regd(reg)) {
802 error = regulatory_hint(hw->wiphy, reg->alpha2);
807 INIT_WORK(&sc->hw_check_work, ath_hw_check);
808 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
809 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
810 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
813 ath_start_rfkill_poll(sc);
818 ieee80211_unregister_hw(hw);
826 ath9k_deinit_softc(sc);
831 /*****************************/
832 /* De-Initialization */
833 /*****************************/
835 static void ath9k_deinit_softc(struct ath_softc *sc)
839 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
840 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
842 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
843 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
845 if ((sc->btcoex.no_stomp_timer) &&
846 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
847 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
849 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
850 if (ATH_TXQ_SETUP(sc, i))
851 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
853 ath9k_hw_deinit(sc->sc_ah);
859 void ath9k_deinit_device(struct ath_softc *sc)
861 struct ieee80211_hw *hw = sc->hw;
865 wiphy_rfkill_stop_polling(sc->hw->wiphy);
868 ath9k_ps_restore(sc);
870 ieee80211_unregister_hw(hw);
873 ath9k_deinit_softc(sc);
876 void ath_descdma_cleanup(struct ath_softc *sc,
877 struct ath_descdma *dd,
878 struct list_head *head)
880 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
883 INIT_LIST_HEAD(head);
884 kfree(dd->dd_bufptr);
885 memset(dd, 0, sizeof(*dd));
888 /************************/
890 /************************/
892 static int __init ath9k_init(void)
896 /* Register rate control algorithm */
897 error = ath_rate_control_register();
900 "ath9k: Unable to register rate control "
906 error = ath_pci_init();
909 "ath9k: No PCI devices found, driver not installed.\n");
911 goto err_rate_unregister;
914 error = ath_ahb_init();
926 ath_rate_control_unregister();
930 module_init(ath9k_init);
932 static void __exit ath9k_exit(void)
934 is_ath9k_unloaded = true;
937 ath_rate_control_unregister();
938 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
940 module_exit(ath9k_exit);