2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 static char *dev_info = "ath9k";
21 MODULE_AUTHOR("Atheros Communications");
22 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
23 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
24 MODULE_LICENSE("Dual BSD/GPL");
26 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
27 module_param_named(debug, ath9k_debug, uint, 0);
28 MODULE_PARM_DESC(debug, "Debugging mask");
30 int modparam_nohwcrypt;
31 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
32 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
34 /* We use the hw_value as an index into our private channel structure */
36 #define CHAN2G(_freq, _idx) { \
37 .center_freq = (_freq), \
42 #define CHAN5G(_freq, _idx) { \
43 .band = IEEE80211_BAND_5GHZ, \
44 .center_freq = (_freq), \
49 /* Some 2 GHz radios are actually tunable on 2312-2732
50 * on 5 MHz steps, we support the channels which we know
51 * we have calibration data for all cards though to make
53 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
54 CHAN2G(2412, 0), /* Channel 1 */
55 CHAN2G(2417, 1), /* Channel 2 */
56 CHAN2G(2422, 2), /* Channel 3 */
57 CHAN2G(2427, 3), /* Channel 4 */
58 CHAN2G(2432, 4), /* Channel 5 */
59 CHAN2G(2437, 5), /* Channel 6 */
60 CHAN2G(2442, 6), /* Channel 7 */
61 CHAN2G(2447, 7), /* Channel 8 */
62 CHAN2G(2452, 8), /* Channel 9 */
63 CHAN2G(2457, 9), /* Channel 10 */
64 CHAN2G(2462, 10), /* Channel 11 */
65 CHAN2G(2467, 11), /* Channel 12 */
66 CHAN2G(2472, 12), /* Channel 13 */
67 CHAN2G(2484, 13), /* Channel 14 */
70 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
71 * on 5 MHz steps, we support the channels which we know
72 * we have calibration data for all cards though to make
74 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
75 /* _We_ call this UNII 1 */
76 CHAN5G(5180, 14), /* Channel 36 */
77 CHAN5G(5200, 15), /* Channel 40 */
78 CHAN5G(5220, 16), /* Channel 44 */
79 CHAN5G(5240, 17), /* Channel 48 */
80 /* _We_ call this UNII 2 */
81 CHAN5G(5260, 18), /* Channel 52 */
82 CHAN5G(5280, 19), /* Channel 56 */
83 CHAN5G(5300, 20), /* Channel 60 */
84 CHAN5G(5320, 21), /* Channel 64 */
85 /* _We_ call this "Middle band" */
86 CHAN5G(5500, 22), /* Channel 100 */
87 CHAN5G(5520, 23), /* Channel 104 */
88 CHAN5G(5540, 24), /* Channel 108 */
89 CHAN5G(5560, 25), /* Channel 112 */
90 CHAN5G(5580, 26), /* Channel 116 */
91 CHAN5G(5600, 27), /* Channel 120 */
92 CHAN5G(5620, 28), /* Channel 124 */
93 CHAN5G(5640, 29), /* Channel 128 */
94 CHAN5G(5660, 30), /* Channel 132 */
95 CHAN5G(5680, 31), /* Channel 136 */
96 CHAN5G(5700, 32), /* Channel 140 */
97 /* _We_ call this UNII 3 */
98 CHAN5G(5745, 33), /* Channel 149 */
99 CHAN5G(5765, 34), /* Channel 153 */
100 CHAN5G(5785, 35), /* Channel 157 */
101 CHAN5G(5805, 36), /* Channel 161 */
102 CHAN5G(5825, 37), /* Channel 165 */
105 /* Atheros hardware rate code addition for short premble */
106 #define SHPCHECK(__hw_rate, __flags) \
107 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
109 #define RATE(_bitrate, _hw_rate, _flags) { \
110 .bitrate = (_bitrate), \
112 .hw_value = (_hw_rate), \
113 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
116 static struct ieee80211_rate ath9k_legacy_rates[] = {
118 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
131 static void ath9k_deinit_softc(struct ath_softc *sc);
134 * Read and write, they both share the same lock. We do this to serialize
135 * reads and writes on Atheros 802.11n PCI devices only. This is required
136 * as the FIFO on these devices can only accept sanely 2 requests.
139 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
141 struct ath_hw *ah = (struct ath_hw *) hw_priv;
142 struct ath_common *common = ath9k_hw_common(ah);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
145 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
147 spin_lock_irqsave(&sc->sc_serial_rw, flags);
148 iowrite32(val, sc->mem + reg_offset);
149 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
151 iowrite32(val, sc->mem + reg_offset);
154 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
156 struct ath_hw *ah = (struct ath_hw *) hw_priv;
157 struct ath_common *common = ath9k_hw_common(ah);
158 struct ath_softc *sc = (struct ath_softc *) common->priv;
161 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
163 spin_lock_irqsave(&sc->sc_serial_rw, flags);
164 val = ioread32(sc->mem + reg_offset);
165 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
167 val = ioread32(sc->mem + reg_offset);
171 static const struct ath_ops ath9k_common_ops = {
172 .read = ath9k_ioread32,
173 .write = ath9k_iowrite32,
176 /**************************/
178 /**************************/
180 static void setup_ht_cap(struct ath_softc *sc,
181 struct ieee80211_sta_ht_cap *ht_info)
183 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
184 u8 tx_streams, rx_streams;
186 ht_info->ht_supported = true;
187 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
188 IEEE80211_HT_CAP_SM_PS |
189 IEEE80211_HT_CAP_SGI_40 |
190 IEEE80211_HT_CAP_DSSSCCK40;
192 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
193 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
195 /* set up supported mcs set */
196 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
197 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
199 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
202 if (tx_streams != rx_streams) {
203 ath_print(common, ATH_DBG_CONFIG,
204 "TX streams %d, RX streams: %d\n",
205 tx_streams, rx_streams);
206 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
207 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
208 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
211 ht_info->mcs.rx_mask[0] = 0xff;
213 ht_info->mcs.rx_mask[1] = 0xff;
215 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
218 static int ath9k_reg_notifier(struct wiphy *wiphy,
219 struct regulatory_request *request)
221 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
222 struct ath_wiphy *aphy = hw->priv;
223 struct ath_softc *sc = aphy->sc;
224 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
226 return ath_reg_notifier_apply(wiphy, request, reg);
230 * This function will allocate both the DMA descriptor structure, and the
231 * buffers it contains. These are used to contain the descriptors used
234 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
235 struct list_head *head, const char *name,
238 #define DS2PHYS(_dd, _ds) \
239 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
240 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
241 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
242 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
247 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
250 INIT_LIST_HEAD(head);
251 /* ath_desc must be a multiple of DWORDs */
252 if ((sizeof(struct ath_desc) % 4) != 0) {
253 ath_print(common, ATH_DBG_FATAL,
254 "ath_desc not DWORD aligned\n");
255 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
260 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
263 * Need additional DMA memory because we can't use
264 * descriptors that cross the 4K page boundary. Assume
265 * one skipped descriptor per 4K page.
267 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
269 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
272 while (ndesc_skipped) {
273 dma_len = ndesc_skipped * sizeof(struct ath_desc);
274 dd->dd_desc_len += dma_len;
276 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
280 /* allocate descriptors */
281 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
282 &dd->dd_desc_paddr, GFP_KERNEL);
283 if (dd->dd_desc == NULL) {
288 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
289 name, ds, (u32) dd->dd_desc_len,
290 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
292 /* allocate buffers */
293 bsize = sizeof(struct ath_buf) * nbuf;
294 bf = kzalloc(bsize, GFP_KERNEL);
301 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
303 bf->bf_daddr = DS2PHYS(dd, ds);
305 if (!(sc->sc_ah->caps.hw_caps &
306 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
308 * Skip descriptor addresses which can cause 4KB
309 * boundary crossing (addr + length) with a 32 dword
312 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
313 BUG_ON((caddr_t) bf->bf_desc >=
314 ((caddr_t) dd->dd_desc +
319 bf->bf_daddr = DS2PHYS(dd, ds);
322 list_add_tail(&bf->list, head);
326 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
329 memset(dd, 0, sizeof(*dd));
331 #undef ATH_DESC_4KB_BOUND_CHECK
332 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
336 static void ath9k_init_crypto(struct ath_softc *sc)
338 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
341 /* Get the hardware key cache size. */
342 common->keymax = sc->sc_ah->caps.keycache_size;
343 if (common->keymax > ATH_KEYMAX) {
344 ath_print(common, ATH_DBG_ANY,
345 "Warning, using only %u entries in %u key cache\n",
346 ATH_KEYMAX, common->keymax);
347 common->keymax = ATH_KEYMAX;
351 * Reset the key cache since some parts do not
352 * reset the contents on initial power up.
354 for (i = 0; i < common->keymax; i++)
355 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
357 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
358 ATH9K_CIPHER_TKIP, NULL)) {
360 * Whether we should enable h/w TKIP MIC.
361 * XXX: if we don't support WME TKIP MIC, then we wouldn't
362 * report WMM capable, so it's always safe to turn on
363 * TKIP MIC in this case.
365 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
369 * Check whether the separate key cache entries
370 * are required to handle both tx+rx MIC keys.
371 * With split mic keys the number of stations is limited
372 * to 27 otherwise 59.
374 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
375 ATH9K_CIPHER_TKIP, NULL)
376 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
377 ATH9K_CIPHER_MIC, NULL)
378 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT,
380 common->splitmic = 1;
382 /* turn on mcast key search if possible */
383 if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
384 (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
389 static int ath9k_init_btcoex(struct ath_softc *sc)
393 switch (sc->sc_ah->btcoex_hw.scheme) {
394 case ATH_BTCOEX_CFG_NONE:
396 case ATH_BTCOEX_CFG_2WIRE:
397 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
399 case ATH_BTCOEX_CFG_3WIRE:
400 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
401 r = ath_init_btcoex_timer(sc);
404 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
405 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
406 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
416 static int ath9k_init_queues(struct ath_softc *sc)
418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
421 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
422 sc->tx.hwq_map[i] = -1;
424 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
425 if (sc->beacon.beaconq == -1) {
426 ath_print(common, ATH_DBG_FATAL,
427 "Unable to setup a beacon xmit queue\n");
431 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
432 if (sc->beacon.cabq == NULL) {
433 ath_print(common, ATH_DBG_FATAL,
434 "Unable to setup CAB xmit queue\n");
438 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
441 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
442 ath_print(common, ATH_DBG_FATAL,
443 "Unable to setup xmit queue for BK traffic\n");
447 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
448 ath_print(common, ATH_DBG_FATAL,
449 "Unable to setup xmit queue for BE traffic\n");
452 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
453 ath_print(common, ATH_DBG_FATAL,
454 "Unable to setup xmit queue for VI traffic\n");
457 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
458 ath_print(common, ATH_DBG_FATAL,
459 "Unable to setup xmit queue for VO traffic\n");
466 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
467 if (ATH_TXQ_SETUP(sc, i))
468 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
473 static void ath9k_init_channels_rates(struct ath_softc *sc)
475 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
476 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
477 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
478 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
479 ARRAY_SIZE(ath9k_2ghz_chantable);
480 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
481 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
482 ARRAY_SIZE(ath9k_legacy_rates);
485 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
486 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
487 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
488 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
489 ARRAY_SIZE(ath9k_5ghz_chantable);
490 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
491 ath9k_legacy_rates + 4;
492 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
493 ARRAY_SIZE(ath9k_legacy_rates) - 4;
497 static void ath9k_init_misc(struct ath_softc *sc)
499 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
502 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
503 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
505 sc->config.txpowlimit = ATH_TXPOWER_MAX;
507 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
508 sc->sc_flags |= SC_OP_TXAGGR;
509 sc->sc_flags |= SC_OP_RXAGGR;
512 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
513 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
515 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
516 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
519 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
521 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
523 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
524 sc->beacon.bslot[i] = NULL;
525 sc->beacon.bslot_aphy[i] = NULL;
529 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
530 const struct ath_bus_ops *bus_ops)
532 struct ath_hw *ah = NULL;
533 struct ath_common *common;
537 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
541 ah->hw_version.devid = devid;
542 ah->hw_version.subsysid = subsysid;
545 common = ath9k_hw_common(ah);
546 common->ops = &ath9k_common_ops;
547 common->bus_ops = bus_ops;
551 common->debug_mask = ath9k_debug;
553 spin_lock_init(&sc->wiphy_lock);
554 spin_lock_init(&sc->sc_resetlock);
555 spin_lock_init(&sc->sc_serial_rw);
556 spin_lock_init(&sc->sc_pm_lock);
557 mutex_init(&sc->mutex);
558 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
559 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
563 * Cache line size is used to size and align various
564 * structures used to communicate with the hardware.
566 ath_read_cachesize(common, &csz);
567 common->cachelsz = csz << 2; /* convert to bytes */
569 ret = ath9k_hw_init(ah);
571 ath_print(common, ATH_DBG_FATAL,
572 "Unable to initialize hardware; "
573 "initialization status: %d\n", ret);
577 ret = ath9k_init_debug(ah);
579 ath_print(common, ATH_DBG_FATAL,
580 "Unable to create debugfs files\n");
584 ret = ath9k_init_queues(sc);
588 ret = ath9k_init_btcoex(sc);
592 ath9k_init_crypto(sc);
593 ath9k_init_channels_rates(sc);
599 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
600 if (ATH_TXQ_SETUP(sc, i))
601 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
603 ath9k_exit_debug(ah);
607 tasklet_kill(&sc->intr_tq);
608 tasklet_kill(&sc->bcon_tasklet);
616 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
618 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
620 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
621 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
622 IEEE80211_HW_SIGNAL_DBM |
623 IEEE80211_HW_SUPPORTS_PS |
624 IEEE80211_HW_PS_NULLFUNC_STACK |
625 IEEE80211_HW_SPECTRUM_MGMT |
626 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
628 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
629 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
631 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
632 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
634 hw->wiphy->interface_modes =
635 BIT(NL80211_IFTYPE_AP) |
636 BIT(NL80211_IFTYPE_STATION) |
637 BIT(NL80211_IFTYPE_ADHOC) |
638 BIT(NL80211_IFTYPE_MESH_POINT);
640 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
644 hw->channel_change_time = 5000;
645 hw->max_listen_interval = 10;
646 hw->max_rate_tries = 10;
647 hw->sta_data_size = sizeof(struct ath_node);
648 hw->vif_data_size = sizeof(struct ath_vif);
650 hw->rate_control_algorithm = "ath9k_rate_control";
652 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
653 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
654 &sc->sbands[IEEE80211_BAND_2GHZ];
655 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
656 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
657 &sc->sbands[IEEE80211_BAND_5GHZ];
659 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
660 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
661 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
662 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
663 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
666 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
669 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
670 const struct ath_bus_ops *bus_ops)
672 struct ieee80211_hw *hw = sc->hw;
673 struct ath_common *common;
676 struct ath_regulatory *reg;
678 /* Bring up device */
679 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
684 common = ath9k_hw_common(ah);
685 ath9k_set_hw_capab(sc, hw);
687 /* Initialize regulatory */
688 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
693 reg = &common->regulatory;
696 error = ath_tx_init(sc, ATH_TXBUF);
701 error = ath_rx_init(sc, ATH_RXBUF);
705 /* Register with mac80211 */
706 error = ieee80211_register_hw(hw);
710 /* Handle world regulatory */
711 if (!ath_is_world_regd(reg)) {
712 error = regulatory_hint(hw->wiphy, reg->alpha2);
717 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
718 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
719 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
722 ath_start_rfkill_poll(sc);
727 ieee80211_unregister_hw(hw);
735 ath9k_deinit_softc(sc);
740 /*****************************/
741 /* De-Initialization */
742 /*****************************/
744 static void ath9k_deinit_softc(struct ath_softc *sc)
748 if ((sc->btcoex.no_stomp_timer) &&
749 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
750 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
752 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
753 if (ATH_TXQ_SETUP(sc, i))
754 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
756 ath9k_exit_debug(sc->sc_ah);
757 ath9k_hw_deinit(sc->sc_ah);
759 tasklet_kill(&sc->intr_tq);
760 tasklet_kill(&sc->bcon_tasklet);
763 void ath9k_deinit_device(struct ath_softc *sc)
765 struct ieee80211_hw *hw = sc->hw;
770 wiphy_rfkill_stop_polling(sc->hw->wiphy);
773 for (i = 0; i < sc->num_sec_wiphy; i++) {
774 struct ath_wiphy *aphy = sc->sec_wiphy[i];
777 sc->sec_wiphy[i] = NULL;
778 ieee80211_unregister_hw(aphy->hw);
779 ieee80211_free_hw(aphy->hw);
781 kfree(sc->sec_wiphy);
783 ieee80211_unregister_hw(hw);
786 ath9k_deinit_softc(sc);
789 void ath_descdma_cleanup(struct ath_softc *sc,
790 struct ath_descdma *dd,
791 struct list_head *head)
793 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
796 INIT_LIST_HEAD(head);
797 kfree(dd->dd_bufptr);
798 memset(dd, 0, sizeof(*dd));
801 /************************/
803 /************************/
805 static int __init ath9k_init(void)
809 /* Register rate control algorithm */
810 error = ath_rate_control_register();
813 "ath9k: Unable to register rate control "
819 error = ath9k_debug_create_root();
822 "ath9k: Unable to create debugfs root: %d\n",
824 goto err_rate_unregister;
827 error = ath_pci_init();
830 "ath9k: No PCI devices found, driver not installed.\n");
832 goto err_remove_root;
835 error = ath_ahb_init();
847 ath9k_debug_remove_root();
849 ath_rate_control_unregister();
853 module_init(ath9k_init);
855 static void __exit ath9k_exit(void)
859 ath9k_debug_remove_root();
860 ath_rate_control_unregister();
861 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
863 module_exit(ath9k_exit);