2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi)
22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask);
28 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
30 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
31 REG_WRITE(ah, AR_IMR_S1,
32 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
33 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
34 REG_RMW_FIELD(ah, AR_IMR_S2,
35 AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask);
38 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
40 return REG_READ(ah, AR_QTXDP(q));
43 bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
45 REG_WRITE(ah, AR_QTXDP(q), txdp);
50 bool ath9k_hw_txstart(struct ath_hw *ah, u32 q)
52 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q);
54 REG_WRITE(ah, AR_Q_TXE, 1 << q);
59 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
63 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
66 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
75 u32 txcfg, curLevel, newLevel;
78 if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD)
81 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
83 txcfg = REG_READ(ah, AR_TXCFG);
84 curLevel = MS(txcfg, AR_FTRIG);
87 if (curLevel < MAX_TX_FIFO_THRESHOLD)
89 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
91 if (newLevel != curLevel)
92 REG_WRITE(ah, AR_TXCFG,
93 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
95 ath9k_hw_set_interrupts(ah, omask);
97 ah->tx_trig_level = newLevel;
99 return newLevel != curLevel;
102 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
104 #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
105 #define ATH9K_TIME_QUANTUM 100 /* usec */
107 struct ath9k_hw_capabilities *pCap = &ah->caps;
108 struct ath9k_tx_queue_info *qi;
110 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
112 if (q >= pCap->total_queues) {
113 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, "
114 "invalid queue: %u\n", q);
119 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
120 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, "
121 "inactive queue: %u\n", q);
125 REG_WRITE(ah, AR_Q_TXD, 1 << q);
127 for (wait = wait_time; wait != 0; wait--) {
128 if (ath9k_hw_numtxpending(ah, q) == 0)
130 udelay(ATH9K_TIME_QUANTUM);
133 if (ath9k_hw_numtxpending(ah, q)) {
134 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
135 "%s: Num of pending TX Frames %d on Q %d\n",
136 __func__, ath9k_hw_numtxpending(ah, q), q);
138 for (j = 0; j < 2; j++) {
139 tsfLow = REG_READ(ah, AR_TSF_L32);
140 REG_WRITE(ah, AR_QUIET2,
141 SM(10, AR_QUIET2_QUIET_DUR));
142 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
143 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
144 REG_SET_BIT(ah, AR_TIMER_MODE,
147 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
150 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
151 "TSF has moved while trying to set "
152 "quiet time TSF: 0x%08x\n", tsfLow);
155 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
158 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
161 while (ath9k_hw_numtxpending(ah, q)) {
163 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
164 "Failed to stop TX DMA in 100 "
165 "msec after killing last frame\n");
168 udelay(ATH9K_TIME_QUANTUM);
171 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
174 REG_WRITE(ah, AR_Q_TXD, 0);
177 #undef ATH9K_TX_STOP_DMA_TIMEOUT
178 #undef ATH9K_TIME_QUANTUM
181 bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
182 u32 segLen, bool firstSeg,
183 bool lastSeg, const struct ath_desc *ds0)
185 struct ar5416_desc *ads = AR5416DESC(ds);
188 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
189 } else if (lastSeg) {
191 ads->ds_ctl1 = segLen;
192 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
193 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
196 ads->ds_ctl1 = segLen | AR_TxMore;
200 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
201 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
202 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
203 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
204 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
209 void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
211 struct ar5416_desc *ads = AR5416DESC(ds);
213 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
214 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
215 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
216 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
217 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
220 int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
222 struct ar5416_desc *ads = AR5416DESC(ds);
224 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
227 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
228 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
229 ds->ds_txstat.ts_status = 0;
230 ds->ds_txstat.ts_flags = 0;
232 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
233 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
234 if (ads->ds_txstatus1 & AR_Filtered)
235 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
236 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
237 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
238 ath9k_hw_updatetxtriglevel(ah, true);
240 if (ads->ds_txstatus9 & AR_TxOpExceeded)
241 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
242 if (ads->ds_txstatus1 & AR_TxTimerExpired)
243 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
245 if (ads->ds_txstatus1 & AR_DescCfgErr)
246 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
247 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
248 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
249 ath9k_hw_updatetxtriglevel(ah, true);
251 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
252 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
253 ath9k_hw_updatetxtriglevel(ah, true);
255 if (ads->ds_txstatus0 & AR_TxBaStatus) {
256 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
257 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
258 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
261 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
262 switch (ds->ds_txstat.ts_rateindex) {
264 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
267 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
270 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
273 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
277 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
278 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
279 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
280 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
281 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
282 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
283 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
284 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
285 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
286 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
287 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
288 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
289 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
290 ds->ds_txstat.ts_antenna = 0;
295 void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
296 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
297 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
299 struct ar5416_desc *ads = AR5416DESC(ds);
301 txPower += ah->txpower_indexoffset;
305 ads->ds_ctl0 = (pktLen & AR_FrameLen)
306 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
307 | SM(txPower, AR_XmitPower)
308 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
309 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
310 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
311 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
314 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
315 | SM(type, AR_FrameType)
316 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
317 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
318 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
320 ads->ds_ctl6 = SM(keyType, AR_EncrType);
322 if (AR_SREV_9285(ah)) {
330 void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
331 struct ath_desc *lastds,
332 u32 durUpdateEn, u32 rtsctsRate,
334 struct ath9k_11n_rate_series series[],
335 u32 nseries, u32 flags)
337 struct ar5416_desc *ads = AR5416DESC(ds);
338 struct ar5416_desc *last_ads = AR5416DESC(lastds);
341 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
342 ds_ctl0 = ads->ds_ctl0;
344 if (flags & ATH9K_TXDESC_RTSENA) {
345 ds_ctl0 &= ~AR_CTSEnable;
346 ds_ctl0 |= AR_RTSEnable;
348 ds_ctl0 &= ~AR_RTSEnable;
349 ds_ctl0 |= AR_CTSEnable;
352 ads->ds_ctl0 = ds_ctl0;
355 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
358 ads->ds_ctl2 = set11nTries(series, 0)
359 | set11nTries(series, 1)
360 | set11nTries(series, 2)
361 | set11nTries(series, 3)
362 | (durUpdateEn ? AR_DurUpdateEna : 0)
363 | SM(0, AR_BurstDur);
365 ads->ds_ctl3 = set11nRate(series, 0)
366 | set11nRate(series, 1)
367 | set11nRate(series, 2)
368 | set11nRate(series, 3);
370 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
371 | set11nPktDurRTSCTS(series, 1);
373 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
374 | set11nPktDurRTSCTS(series, 3);
376 ads->ds_ctl7 = set11nRateFlags(series, 0)
377 | set11nRateFlags(series, 1)
378 | set11nRateFlags(series, 2)
379 | set11nRateFlags(series, 3)
380 | SM(rtsctsRate, AR_RTSCTSRate);
381 last_ads->ds_ctl2 = ads->ds_ctl2;
382 last_ads->ds_ctl3 = ads->ds_ctl3;
385 void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
388 struct ar5416_desc *ads = AR5416DESC(ds);
390 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
391 ads->ds_ctl6 &= ~AR_AggrLen;
392 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
395 void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
398 struct ar5416_desc *ads = AR5416DESC(ds);
401 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
404 ctl6 &= ~AR_PadDelim;
405 ctl6 |= SM(numDelims, AR_PadDelim);
409 void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
411 struct ar5416_desc *ads = AR5416DESC(ds);
413 ads->ds_ctl1 |= AR_IsAggr;
414 ads->ds_ctl1 &= ~AR_MoreAggr;
415 ads->ds_ctl6 &= ~AR_PadDelim;
418 void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
420 struct ar5416_desc *ads = AR5416DESC(ds);
422 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
425 void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
428 struct ar5416_desc *ads = AR5416DESC(ds);
430 ads->ds_ctl2 &= ~AR_BurstDur;
431 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
434 void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
437 struct ar5416_desc *ads = AR5416DESC(ds);
440 ads->ds_ctl0 |= AR_VirtMoreFrag;
442 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
445 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
447 *txqs &= ah->intr_txqs;
448 ah->intr_txqs &= ~(*txqs);
451 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
452 const struct ath9k_tx_queue_info *qinfo)
455 struct ath9k_hw_capabilities *pCap = &ah->caps;
456 struct ath9k_tx_queue_info *qi;
458 if (q >= pCap->total_queues) {
459 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "invalid queue: %u\n", q);
465 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
466 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, "
467 "inactive queue: %u\n", q);
471 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
473 qi->tqi_ver = qinfo->tqi_ver;
474 qi->tqi_subtype = qinfo->tqi_subtype;
475 qi->tqi_qflags = qinfo->tqi_qflags;
476 qi->tqi_priority = qinfo->tqi_priority;
477 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
478 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
480 qi->tqi_aifs = INIT_AIFS;
481 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
482 cw = min(qinfo->tqi_cwmin, 1024U);
484 while (qi->tqi_cwmin < cw)
485 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
487 qi->tqi_cwmin = qinfo->tqi_cwmin;
488 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
489 cw = min(qinfo->tqi_cwmax, 1024U);
491 while (qi->tqi_cwmax < cw)
492 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
494 qi->tqi_cwmax = INIT_CWMAX;
496 if (qinfo->tqi_shretry != 0)
497 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
499 qi->tqi_shretry = INIT_SH_RETRY;
500 if (qinfo->tqi_lgretry != 0)
501 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
503 qi->tqi_lgretry = INIT_LG_RETRY;
504 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
505 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
506 qi->tqi_burstTime = qinfo->tqi_burstTime;
507 qi->tqi_readyTime = qinfo->tqi_readyTime;
509 switch (qinfo->tqi_subtype) {
511 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
512 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
521 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
522 struct ath9k_tx_queue_info *qinfo)
524 struct ath9k_hw_capabilities *pCap = &ah->caps;
525 struct ath9k_tx_queue_info *qi;
527 if (q >= pCap->total_queues) {
528 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "invalid queue: %u\n", q);
534 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
535 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, "
536 "inactive queue: %u\n", q);
540 qinfo->tqi_qflags = qi->tqi_qflags;
541 qinfo->tqi_ver = qi->tqi_ver;
542 qinfo->tqi_subtype = qi->tqi_subtype;
543 qinfo->tqi_qflags = qi->tqi_qflags;
544 qinfo->tqi_priority = qi->tqi_priority;
545 qinfo->tqi_aifs = qi->tqi_aifs;
546 qinfo->tqi_cwmin = qi->tqi_cwmin;
547 qinfo->tqi_cwmax = qi->tqi_cwmax;
548 qinfo->tqi_shretry = qi->tqi_shretry;
549 qinfo->tqi_lgretry = qi->tqi_lgretry;
550 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
551 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
552 qinfo->tqi_burstTime = qi->tqi_burstTime;
553 qinfo->tqi_readyTime = qi->tqi_readyTime;
558 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
559 const struct ath9k_tx_queue_info *qinfo)
561 struct ath9k_tx_queue_info *qi;
562 struct ath9k_hw_capabilities *pCap = &ah->caps;
566 case ATH9K_TX_QUEUE_BEACON:
567 q = pCap->total_queues - 1;
569 case ATH9K_TX_QUEUE_CAB:
570 q = pCap->total_queues - 2;
572 case ATH9K_TX_QUEUE_PSPOLL:
575 case ATH9K_TX_QUEUE_UAPSD:
576 q = pCap->total_queues - 3;
578 case ATH9K_TX_QUEUE_DATA:
579 for (q = 0; q < pCap->total_queues; q++)
580 if (ah->txq[q].tqi_type ==
581 ATH9K_TX_QUEUE_INACTIVE)
583 if (q == pCap->total_queues) {
584 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
585 "No available TX queue\n");
590 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n",
595 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
598 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
599 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
600 "TX queue: %u already active\n", q);
603 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
607 TXQ_FLAG_TXOKINT_ENABLE
608 | TXQ_FLAG_TXERRINT_ENABLE
609 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
610 qi->tqi_aifs = INIT_AIFS;
611 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
612 qi->tqi_cwmax = INIT_CWMAX;
613 qi->tqi_shretry = INIT_SH_RETRY;
614 qi->tqi_lgretry = INIT_LG_RETRY;
615 qi->tqi_physCompBuf = 0;
617 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
618 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
624 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
626 struct ath9k_hw_capabilities *pCap = &ah->caps;
627 struct ath9k_tx_queue_info *qi;
629 if (q >= pCap->total_queues) {
630 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, "
631 "invalid queue: %u\n", q);
635 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
636 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, "
637 "inactive queue: %u\n", q);
641 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
643 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
644 ah->txok_interrupt_mask &= ~(1 << q);
645 ah->txerr_interrupt_mask &= ~(1 << q);
646 ah->txdesc_interrupt_mask &= ~(1 << q);
647 ah->txeol_interrupt_mask &= ~(1 << q);
648 ah->txurn_interrupt_mask &= ~(1 << q);
649 ath9k_hw_set_txq_interrupts(ah, qi);
654 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
656 struct ath9k_hw_capabilities *pCap = &ah->caps;
657 struct ath9k_channel *chan = ah->curchan;
658 struct ath9k_tx_queue_info *qi;
659 u32 cwMin, chanCwMin, value;
661 if (q >= pCap->total_queues) {
662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, "
663 "invalid queue: %u\n", q);
668 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
669 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, "
670 "inactive queue: %u\n", q);
674 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
676 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
677 if (chan && IS_CHAN_B(chan))
678 chanCwMin = INIT_CWMIN_11B;
680 chanCwMin = INIT_CWMIN;
682 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
684 cwMin = qi->tqi_cwmin;
686 REG_WRITE(ah, AR_DLCL_IFS(q),
687 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
688 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
689 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
691 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
692 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
693 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
694 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
696 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
697 REG_WRITE(ah, AR_DMISC(q),
698 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
700 if (qi->tqi_cbrPeriod) {
701 REG_WRITE(ah, AR_QCBRCFG(q),
702 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
703 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
704 REG_WRITE(ah, AR_QMISC(q),
705 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
706 (qi->tqi_cbrOverflowLimit ?
707 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
709 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
710 REG_WRITE(ah, AR_QRDYTIMECFG(q),
711 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
715 REG_WRITE(ah, AR_DCHNTIME(q),
716 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
717 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
719 if (qi->tqi_burstTime
720 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
721 REG_WRITE(ah, AR_QMISC(q),
722 REG_READ(ah, AR_QMISC(q)) |
723 AR_Q_MISC_RDYTIME_EXP_POLICY);
727 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
728 REG_WRITE(ah, AR_DMISC(q),
729 REG_READ(ah, AR_DMISC(q)) |
730 AR_D_MISC_POST_FR_BKOFF_DIS);
732 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
733 REG_WRITE(ah, AR_DMISC(q),
734 REG_READ(ah, AR_DMISC(q)) |
735 AR_D_MISC_FRAG_BKOFF_EN);
737 switch (qi->tqi_type) {
738 case ATH9K_TX_QUEUE_BEACON:
739 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
740 | AR_Q_MISC_FSP_DBA_GATED
741 | AR_Q_MISC_BEACON_USE
742 | AR_Q_MISC_CBR_INCR_DIS1);
744 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
745 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
746 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
747 | AR_D_MISC_BEACON_USE
748 | AR_D_MISC_POST_FR_BKOFF_DIS);
750 case ATH9K_TX_QUEUE_CAB:
751 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
752 | AR_Q_MISC_FSP_DBA_GATED
753 | AR_Q_MISC_CBR_INCR_DIS1
754 | AR_Q_MISC_CBR_INCR_DIS0);
755 value = (qi->tqi_readyTime -
756 (ah->config.sw_beacon_response_time -
757 ah->config.dma_beacon_response_time) -
758 ah->config.additional_swba_backoff) * 1024;
759 REG_WRITE(ah, AR_QRDYTIMECFG(q),
760 value | AR_Q_RDYTIMECFG_EN);
761 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
762 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
763 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
765 case ATH9K_TX_QUEUE_PSPOLL:
766 REG_WRITE(ah, AR_QMISC(q),
767 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
769 case ATH9K_TX_QUEUE_UAPSD:
770 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
771 AR_D_MISC_POST_FR_BKOFF_DIS);
777 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
778 REG_WRITE(ah, AR_DMISC(q),
779 REG_READ(ah, AR_DMISC(q)) |
780 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
781 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
782 AR_D_MISC_POST_FR_BKOFF_DIS);
785 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
786 ah->txok_interrupt_mask |= 1 << q;
788 ah->txok_interrupt_mask &= ~(1 << q);
789 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
790 ah->txerr_interrupt_mask |= 1 << q;
792 ah->txerr_interrupt_mask &= ~(1 << q);
793 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
794 ah->txdesc_interrupt_mask |= 1 << q;
796 ah->txdesc_interrupt_mask &= ~(1 << q);
797 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
798 ah->txeol_interrupt_mask |= 1 << q;
800 ah->txeol_interrupt_mask &= ~(1 << q);
801 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
802 ah->txurn_interrupt_mask |= 1 << q;
804 ah->txurn_interrupt_mask &= ~(1 << q);
805 ath9k_hw_set_txq_interrupts(ah, qi);
810 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
811 u32 pa, struct ath_desc *nds, u64 tsf)
813 struct ar5416_desc ads;
814 struct ar5416_desc *adsp = AR5416DESC(ds);
817 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
820 ads.u.rx = adsp->u.rx;
822 ds->ds_rxstat.rs_status = 0;
823 ds->ds_rxstat.rs_flags = 0;
825 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
826 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
828 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
829 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
830 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
831 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
832 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
833 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
834 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
835 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
836 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
838 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
840 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
841 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
843 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
844 ds->ds_rxstat.rs_moreaggr =
845 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
846 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
847 ds->ds_rxstat.rs_flags =
848 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
849 ds->ds_rxstat.rs_flags |=
850 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
852 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
853 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
854 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
855 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
856 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
857 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
859 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
860 if (ads.ds_rxstatus8 & AR_CRCErr)
861 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
862 else if (ads.ds_rxstatus8 & AR_PHYErr) {
863 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
864 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
865 ds->ds_rxstat.rs_phyerr = phyerr;
866 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
867 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
868 else if (ads.ds_rxstatus8 & AR_MichaelErr)
869 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
875 bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
878 struct ar5416_desc *ads = AR5416DESC(ds);
879 struct ath9k_hw_capabilities *pCap = &ah->caps;
881 ads->ds_ctl1 = size & AR_BufLen;
882 if (flags & ATH9K_RXDESC_INTREQ)
883 ads->ds_ctl1 |= AR_RxIntrReq;
885 ads->ds_rxstatus8 &= ~AR_RxDone;
886 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
887 memset(&(ads->u), 0, sizeof(ads->u));
892 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
897 REG_SET_BIT(ah, AR_DIAG_SW,
898 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
900 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
901 0, AH_WAIT_TIMEOUT)) {
902 REG_CLR_BIT(ah, AR_DIAG_SW,
906 reg = REG_READ(ah, AR_OBS_BUS_1);
907 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
908 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg);
913 REG_CLR_BIT(ah, AR_DIAG_SW,
914 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
920 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
922 REG_WRITE(ah, AR_RXDP, rxdp);
925 void ath9k_hw_rxena(struct ath_hw *ah)
927 REG_WRITE(ah, AR_CR, AR_CR_RXE);
930 void ath9k_hw_startpcureceive(struct ath_hw *ah)
932 ath9k_enable_mib_counters(ah);
936 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
939 void ath9k_hw_stoppcurecv(struct ath_hw *ah)
941 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
943 ath9k_hw_disable_mib_counters(ah);
946 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
948 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
949 #define AH_RX_TIME_QUANTUM 100 /* usec */
953 REG_WRITE(ah, AR_CR, AR_CR_RXD);
955 /* Wait for rx enable bit to go low */
956 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
957 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
959 udelay(AH_TIME_QUANTUM);
963 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
964 "DMA failed to stop in %d ms "
965 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
966 AH_RX_STOP_DMA_TIMEOUT / 1000,
968 REG_READ(ah, AR_DIAG_SW));
974 #undef AH_RX_TIME_QUANTUM
975 #undef AH_RX_STOP_DMA_TIMEOUT