2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
21 struct ath9k_tx_queue_info *qi)
23 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 ah->txurn_interrupt_mask);
29 ENABLE_REGWRITE_BUFFER(ah);
31 REG_WRITE(ah, AR_IMR_S0,
32 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
33 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
34 REG_WRITE(ah, AR_IMR_S1,
35 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
36 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
39 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42 REGWRITE_BUFFER_FLUSH(ah);
45 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47 return REG_READ(ah, AR_QTXDP(q));
49 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53 REG_WRITE(ah, AR_QTXDP(q), txdp);
55 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
60 "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
63 EXPORT_SYMBOL(ath9k_hw_txstart);
65 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
67 struct ar5416_desc *ads = AR5416DESC(ds);
69 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
70 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
71 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
72 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
73 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
75 EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
77 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
81 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
84 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
90 EXPORT_SYMBOL(ath9k_hw_numtxpending);
93 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
95 * @ah: atheros hardware struct
96 * @bIncTrigLevel: whether or not the frame trigger level should be updated
98 * The frame trigger level specifies the minimum number of bytes,
99 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
100 * before the PCU will initiate sending the frame on the air. This can
101 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
102 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
105 * Caution must be taken to ensure to set the frame trigger level based
106 * on the DMA request size. For example if the DMA request size is set to
107 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
108 * there need to be enough space in the tx FIFO for the requested transfer
109 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
110 * the threshold to a value beyond 6, then the transmit will hang.
112 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
113 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
114 * there is a hardware issue which forces us to use 2 KB instead so the
115 * frame trigger level must not exceed 2 KB for these chipsets.
117 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
119 u32 txcfg, curLevel, newLevel;
121 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
124 ath9k_hw_disable_interrupts(ah);
126 txcfg = REG_READ(ah, AR_TXCFG);
127 curLevel = MS(txcfg, AR_FTRIG);
130 if (curLevel < ah->config.max_txtrig_level)
132 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
134 if (newLevel != curLevel)
135 REG_WRITE(ah, AR_TXCFG,
136 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
138 ath9k_hw_enable_interrupts(ah);
140 ah->tx_trig_level = newLevel;
142 return newLevel != curLevel;
144 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
146 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
148 #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
149 #define ATH9K_TIME_QUANTUM 100 /* usec */
150 struct ath_common *common = ath9k_hw_common(ah);
151 struct ath9k_hw_capabilities *pCap = &ah->caps;
152 struct ath9k_tx_queue_info *qi;
154 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
156 if (q >= pCap->total_queues) {
157 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
158 "invalid queue: %u\n", q);
163 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
164 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
165 "inactive queue: %u\n", q);
169 REG_WRITE(ah, AR_Q_TXD, 1 << q);
171 for (wait = wait_time; wait != 0; wait--) {
172 if (ath9k_hw_numtxpending(ah, q) == 0)
174 udelay(ATH9K_TIME_QUANTUM);
177 if (ath9k_hw_numtxpending(ah, q)) {
178 ath_print(common, ATH_DBG_QUEUE,
179 "%s: Num of pending TX Frames %d on Q %d\n",
180 __func__, ath9k_hw_numtxpending(ah, q), q);
182 for (j = 0; j < 2; j++) {
183 tsfLow = REG_READ(ah, AR_TSF_L32);
184 REG_WRITE(ah, AR_QUIET2,
185 SM(10, AR_QUIET2_QUIET_DUR));
186 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
187 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
188 REG_SET_BIT(ah, AR_TIMER_MODE,
191 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
194 ath_print(common, ATH_DBG_QUEUE,
195 "TSF has moved while trying to set "
196 "quiet time TSF: 0x%08x\n", tsfLow);
199 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
202 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
205 while (ath9k_hw_numtxpending(ah, q)) {
207 ath_print(common, ATH_DBG_FATAL,
208 "Failed to stop TX DMA in 100 "
209 "msec after killing last frame\n");
212 udelay(ATH9K_TIME_QUANTUM);
215 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
218 REG_WRITE(ah, AR_Q_TXD, 0);
221 #undef ATH9K_TX_STOP_DMA_TIMEOUT
222 #undef ATH9K_TIME_QUANTUM
224 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
226 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
228 *txqs &= ah->intr_txqs;
229 ah->intr_txqs &= ~(*txqs);
231 EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
233 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
234 const struct ath9k_tx_queue_info *qinfo)
237 struct ath_common *common = ath9k_hw_common(ah);
238 struct ath9k_hw_capabilities *pCap = &ah->caps;
239 struct ath9k_tx_queue_info *qi;
241 if (q >= pCap->total_queues) {
242 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
243 "invalid queue: %u\n", q);
248 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
249 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
250 "inactive queue: %u\n", q);
254 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
256 qi->tqi_ver = qinfo->tqi_ver;
257 qi->tqi_subtype = qinfo->tqi_subtype;
258 qi->tqi_qflags = qinfo->tqi_qflags;
259 qi->tqi_priority = qinfo->tqi_priority;
260 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
261 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
263 qi->tqi_aifs = INIT_AIFS;
264 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
265 cw = min(qinfo->tqi_cwmin, 1024U);
267 while (qi->tqi_cwmin < cw)
268 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
270 qi->tqi_cwmin = qinfo->tqi_cwmin;
271 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
272 cw = min(qinfo->tqi_cwmax, 1024U);
274 while (qi->tqi_cwmax < cw)
275 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
277 qi->tqi_cwmax = INIT_CWMAX;
279 if (qinfo->tqi_shretry != 0)
280 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
282 qi->tqi_shretry = INIT_SH_RETRY;
283 if (qinfo->tqi_lgretry != 0)
284 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
286 qi->tqi_lgretry = INIT_LG_RETRY;
287 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
288 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
289 qi->tqi_burstTime = qinfo->tqi_burstTime;
290 qi->tqi_readyTime = qinfo->tqi_readyTime;
292 switch (qinfo->tqi_subtype) {
294 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
295 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
303 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
305 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
306 struct ath9k_tx_queue_info *qinfo)
308 struct ath_common *common = ath9k_hw_common(ah);
309 struct ath9k_hw_capabilities *pCap = &ah->caps;
310 struct ath9k_tx_queue_info *qi;
312 if (q >= pCap->total_queues) {
313 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
314 "invalid queue: %u\n", q);
319 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
320 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
321 "inactive queue: %u\n", q);
325 qinfo->tqi_qflags = qi->tqi_qflags;
326 qinfo->tqi_ver = qi->tqi_ver;
327 qinfo->tqi_subtype = qi->tqi_subtype;
328 qinfo->tqi_qflags = qi->tqi_qflags;
329 qinfo->tqi_priority = qi->tqi_priority;
330 qinfo->tqi_aifs = qi->tqi_aifs;
331 qinfo->tqi_cwmin = qi->tqi_cwmin;
332 qinfo->tqi_cwmax = qi->tqi_cwmax;
333 qinfo->tqi_shretry = qi->tqi_shretry;
334 qinfo->tqi_lgretry = qi->tqi_lgretry;
335 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
336 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
337 qinfo->tqi_burstTime = qi->tqi_burstTime;
338 qinfo->tqi_readyTime = qi->tqi_readyTime;
342 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
344 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
345 const struct ath9k_tx_queue_info *qinfo)
347 struct ath_common *common = ath9k_hw_common(ah);
348 struct ath9k_tx_queue_info *qi;
349 struct ath9k_hw_capabilities *pCap = &ah->caps;
353 case ATH9K_TX_QUEUE_BEACON:
354 q = pCap->total_queues - 1;
356 case ATH9K_TX_QUEUE_CAB:
357 q = pCap->total_queues - 2;
359 case ATH9K_TX_QUEUE_PSPOLL:
362 case ATH9K_TX_QUEUE_UAPSD:
363 q = pCap->total_queues - 3;
365 case ATH9K_TX_QUEUE_DATA:
366 for (q = 0; q < pCap->total_queues; q++)
367 if (ah->txq[q].tqi_type ==
368 ATH9K_TX_QUEUE_INACTIVE)
370 if (q == pCap->total_queues) {
371 ath_print(common, ATH_DBG_FATAL,
372 "No available TX queue\n");
377 ath_print(common, ATH_DBG_FATAL,
378 "Invalid TX queue type: %u\n", type);
382 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
385 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
386 ath_print(common, ATH_DBG_FATAL,
387 "TX queue: %u already active\n", q);
390 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
394 TXQ_FLAG_TXOKINT_ENABLE
395 | TXQ_FLAG_TXERRINT_ENABLE
396 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
397 qi->tqi_aifs = INIT_AIFS;
398 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
399 qi->tqi_cwmax = INIT_CWMAX;
400 qi->tqi_shretry = INIT_SH_RETRY;
401 qi->tqi_lgretry = INIT_LG_RETRY;
402 qi->tqi_physCompBuf = 0;
404 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
405 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
410 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
412 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
414 struct ath9k_hw_capabilities *pCap = &ah->caps;
415 struct ath_common *common = ath9k_hw_common(ah);
416 struct ath9k_tx_queue_info *qi;
418 if (q >= pCap->total_queues) {
419 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
420 "invalid queue: %u\n", q);
424 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
425 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
426 "inactive queue: %u\n", q);
430 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
432 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
433 ah->txok_interrupt_mask &= ~(1 << q);
434 ah->txerr_interrupt_mask &= ~(1 << q);
435 ah->txdesc_interrupt_mask &= ~(1 << q);
436 ah->txeol_interrupt_mask &= ~(1 << q);
437 ah->txurn_interrupt_mask &= ~(1 << q);
438 ath9k_hw_set_txq_interrupts(ah, qi);
442 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
444 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
446 struct ath9k_hw_capabilities *pCap = &ah->caps;
447 struct ath_common *common = ath9k_hw_common(ah);
448 struct ath9k_channel *chan = ah->curchan;
449 struct ath9k_tx_queue_info *qi;
450 u32 cwMin, chanCwMin, value;
452 if (q >= pCap->total_queues) {
453 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
454 "invalid queue: %u\n", q);
459 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
460 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
461 "inactive queue: %u\n", q);
465 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
467 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
468 if (chan && IS_CHAN_B(chan))
469 chanCwMin = INIT_CWMIN_11B;
471 chanCwMin = INIT_CWMIN;
473 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
475 cwMin = qi->tqi_cwmin;
477 ENABLE_REGWRITE_BUFFER(ah);
479 REG_WRITE(ah, AR_DLCL_IFS(q),
480 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
481 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
482 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
484 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
485 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
486 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
487 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
489 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
490 REG_WRITE(ah, AR_DMISC(q),
491 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
493 if (qi->tqi_cbrPeriod) {
494 REG_WRITE(ah, AR_QCBRCFG(q),
495 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
496 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
497 REG_WRITE(ah, AR_QMISC(q),
498 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
499 (qi->tqi_cbrOverflowLimit ?
500 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
502 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
503 REG_WRITE(ah, AR_QRDYTIMECFG(q),
504 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
508 REG_WRITE(ah, AR_DCHNTIME(q),
509 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
510 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
512 if (qi->tqi_burstTime
513 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
514 REG_WRITE(ah, AR_QMISC(q),
515 REG_READ(ah, AR_QMISC(q)) |
516 AR_Q_MISC_RDYTIME_EXP_POLICY);
520 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
521 REG_WRITE(ah, AR_DMISC(q),
522 REG_READ(ah, AR_DMISC(q)) |
523 AR_D_MISC_POST_FR_BKOFF_DIS);
526 REGWRITE_BUFFER_FLUSH(ah);
528 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
529 REG_WRITE(ah, AR_DMISC(q),
530 REG_READ(ah, AR_DMISC(q)) |
531 AR_D_MISC_FRAG_BKOFF_EN);
533 switch (qi->tqi_type) {
534 case ATH9K_TX_QUEUE_BEACON:
535 ENABLE_REGWRITE_BUFFER(ah);
537 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
538 | AR_Q_MISC_FSP_DBA_GATED
539 | AR_Q_MISC_BEACON_USE
540 | AR_Q_MISC_CBR_INCR_DIS1);
542 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
543 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
544 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
545 | AR_D_MISC_BEACON_USE
546 | AR_D_MISC_POST_FR_BKOFF_DIS);
548 REGWRITE_BUFFER_FLUSH(ah);
551 * cwmin and cwmax should be 0 for beacon queue
552 * but not for IBSS as we would create an imbalance
553 * on beaconing fairness for participating nodes.
555 if (AR_SREV_9300_20_OR_LATER(ah) &&
556 ah->opmode != NL80211_IFTYPE_ADHOC) {
557 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
558 | SM(0, AR_D_LCL_IFS_CWMAX)
559 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
562 case ATH9K_TX_QUEUE_CAB:
563 ENABLE_REGWRITE_BUFFER(ah);
565 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
566 | AR_Q_MISC_FSP_DBA_GATED
567 | AR_Q_MISC_CBR_INCR_DIS1
568 | AR_Q_MISC_CBR_INCR_DIS0);
569 value = (qi->tqi_readyTime -
570 (ah->config.sw_beacon_response_time -
571 ah->config.dma_beacon_response_time) -
572 ah->config.additional_swba_backoff) * 1024;
573 REG_WRITE(ah, AR_QRDYTIMECFG(q),
574 value | AR_Q_RDYTIMECFG_EN);
575 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
576 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
577 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
579 REGWRITE_BUFFER_FLUSH(ah);
582 case ATH9K_TX_QUEUE_PSPOLL:
583 REG_WRITE(ah, AR_QMISC(q),
584 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
586 case ATH9K_TX_QUEUE_UAPSD:
587 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
588 AR_D_MISC_POST_FR_BKOFF_DIS);
594 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
595 REG_WRITE(ah, AR_DMISC(q),
596 REG_READ(ah, AR_DMISC(q)) |
597 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
598 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
599 AR_D_MISC_POST_FR_BKOFF_DIS);
602 if (AR_SREV_9300_20_OR_LATER(ah))
603 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
605 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
606 ah->txok_interrupt_mask |= 1 << q;
608 ah->txok_interrupt_mask &= ~(1 << q);
609 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
610 ah->txerr_interrupt_mask |= 1 << q;
612 ah->txerr_interrupt_mask &= ~(1 << q);
613 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
614 ah->txdesc_interrupt_mask |= 1 << q;
616 ah->txdesc_interrupt_mask &= ~(1 << q);
617 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
618 ah->txeol_interrupt_mask |= 1 << q;
620 ah->txeol_interrupt_mask &= ~(1 << q);
621 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
622 ah->txurn_interrupt_mask |= 1 << q;
624 ah->txurn_interrupt_mask &= ~(1 << q);
625 ath9k_hw_set_txq_interrupts(ah, qi);
629 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
631 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
632 struct ath_rx_status *rs, u64 tsf)
634 struct ar5416_desc ads;
635 struct ar5416_desc *adsp = AR5416DESC(ds);
638 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
641 ads.u.rx = adsp->u.rx;
646 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
647 rs->rs_tstamp = ads.AR_RcvTimestamp;
649 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
650 rs->rs_rssi = ATH9K_RSSI_BAD;
651 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
652 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
653 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
654 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
655 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
656 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
658 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
659 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
661 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
663 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
665 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
667 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
669 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
672 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
673 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
675 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
677 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
678 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
680 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
682 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
683 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
685 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
687 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
689 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
690 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
691 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
692 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
693 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
694 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
696 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
697 if (ads.ds_rxstatus8 & AR_CRCErr)
698 rs->rs_status |= ATH9K_RXERR_CRC;
699 else if (ads.ds_rxstatus8 & AR_PHYErr) {
700 rs->rs_status |= ATH9K_RXERR_PHY;
701 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
702 rs->rs_phyerr = phyerr;
703 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
704 rs->rs_status |= ATH9K_RXERR_DECRYPT;
705 else if ((ads.ds_rxstatus8 & AR_MichaelErr) &&
706 rs->rs_keyix != ATH9K_RXKEYIX_INVALID)
707 rs->rs_status |= ATH9K_RXERR_MIC;
708 else if (ads.ds_rxstatus8 & AR_KeyMiss)
709 rs->rs_status |= ATH9K_RXERR_DECRYPT;
714 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
717 * This can stop or re-enables RX.
719 * If bool is set this will kill any frame which is currently being
720 * transferred between the MAC and baseband and also prevent any new
721 * frames from getting started.
723 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
728 REG_SET_BIT(ah, AR_DIAG_SW,
729 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
731 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
732 0, AH_WAIT_TIMEOUT)) {
733 REG_CLR_BIT(ah, AR_DIAG_SW,
737 reg = REG_READ(ah, AR_OBS_BUS_1);
738 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
739 "RX failed to go idle in 10 ms RXSM=0x%x\n",
745 REG_CLR_BIT(ah, AR_DIAG_SW,
746 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
751 EXPORT_SYMBOL(ath9k_hw_setrxabort);
753 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
755 REG_WRITE(ah, AR_RXDP, rxdp);
757 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
759 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
761 ath9k_enable_mib_counters(ah);
763 ath9k_ani_reset(ah, is_scanning);
765 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
767 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
769 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
771 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
773 ath9k_hw_disable_mib_counters(ah);
775 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
777 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
779 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
780 #define AH_RX_TIME_QUANTUM 100 /* usec */
781 struct ath_common *common = ath9k_hw_common(ah);
784 REG_WRITE(ah, AR_CR, AR_CR_RXD);
786 /* Wait for rx enable bit to go low */
787 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
788 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
790 udelay(AH_TIME_QUANTUM);
794 ath_print(common, ATH_DBG_FATAL,
795 "DMA failed to stop in %d ms "
796 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
797 AH_RX_STOP_DMA_TIMEOUT / 1000,
799 REG_READ(ah, AR_DIAG_SW));
805 #undef AH_RX_TIME_QUANTUM
806 #undef AH_RX_STOP_DMA_TIMEOUT
808 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
810 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
812 struct ath9k_tx_queue_info qi;
814 memset(&qi, 0, sizeof(qi));
818 /* NB: don't enable any interrupts */
819 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
821 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
823 bool ath9k_hw_intrpend(struct ath_hw *ah)
827 if (AR_SREV_9100(ah))
830 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
831 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
834 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
835 if ((host_isr & AR_INTR_SYNC_DEFAULT)
836 && (host_isr != AR_INTR_SPURIOUS))
841 EXPORT_SYMBOL(ath9k_hw_intrpend);
843 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
845 struct ath_common *common = ath9k_hw_common(ah);
847 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
848 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
849 (void) REG_READ(ah, AR_IER);
850 if (!AR_SREV_9100(ah)) {
851 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
852 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
854 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
855 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
858 EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
860 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
862 struct ath_common *common = ath9k_hw_common(ah);
864 if (!(ah->imask & ATH9K_INT_GLOBAL))
867 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
868 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
869 if (!AR_SREV_9100(ah)) {
870 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
872 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
875 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
876 AR_INTR_SYNC_DEFAULT);
877 REG_WRITE(ah, AR_INTR_SYNC_MASK,
878 AR_INTR_SYNC_DEFAULT);
880 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
881 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
883 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
885 void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
887 enum ath9k_int omask = ah->imask;
889 struct ath9k_hw_capabilities *pCap = &ah->caps;
890 struct ath_common *common = ath9k_hw_common(ah);
892 if (!(ints & ATH9K_INT_GLOBAL))
893 ath9k_hw_enable_interrupts(ah);
895 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
897 /* TODO: global int Ref count */
898 mask = ints & ATH9K_INT_COMMON;
901 if (ints & ATH9K_INT_TX) {
902 if (ah->config.tx_intr_mitigation)
903 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
905 if (ah->txok_interrupt_mask)
907 if (ah->txdesc_interrupt_mask)
908 mask |= AR_IMR_TXDESC;
910 if (ah->txerr_interrupt_mask)
911 mask |= AR_IMR_TXERR;
912 if (ah->txeol_interrupt_mask)
913 mask |= AR_IMR_TXEOL;
915 if (ints & ATH9K_INT_RX) {
916 if (AR_SREV_9300_20_OR_LATER(ah)) {
917 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
918 if (ah->config.rx_intr_mitigation) {
919 mask &= ~AR_IMR_RXOK_LP;
920 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
922 mask |= AR_IMR_RXOK_LP;
925 if (ah->config.rx_intr_mitigation)
926 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
928 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
930 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
931 mask |= AR_IMR_GENTMR;
934 if (ints & (ATH9K_INT_BMISC)) {
935 mask |= AR_IMR_BCNMISC;
936 if (ints & ATH9K_INT_TIM)
937 mask2 |= AR_IMR_S2_TIM;
938 if (ints & ATH9K_INT_DTIM)
939 mask2 |= AR_IMR_S2_DTIM;
940 if (ints & ATH9K_INT_DTIMSYNC)
941 mask2 |= AR_IMR_S2_DTIMSYNC;
942 if (ints & ATH9K_INT_CABEND)
943 mask2 |= AR_IMR_S2_CABEND;
944 if (ints & ATH9K_INT_TSFOOR)
945 mask2 |= AR_IMR_S2_TSFOOR;
948 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
949 mask |= AR_IMR_BCNMISC;
950 if (ints & ATH9K_INT_GTT)
951 mask2 |= AR_IMR_S2_GTT;
952 if (ints & ATH9K_INT_CST)
953 mask2 |= AR_IMR_S2_CST;
956 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
957 REG_WRITE(ah, AR_IMR, mask);
958 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
959 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
960 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
961 ah->imrs2_reg |= mask2;
962 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
964 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
965 if (ints & ATH9K_INT_TIM_TIMER)
966 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
968 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
971 ath9k_hw_enable_interrupts(ah);
975 EXPORT_SYMBOL(ath9k_hw_set_interrupts);