2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
21 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
24 #define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
27 #define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
30 #define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
35 #define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
40 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
41 AR_STBC##_index : 0) \
42 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
44 #define CCK_SIFS_TIME 10
45 #define CCK_PREAMBLE_BITS 144
46 #define CCK_PLCP_BITS 48
48 #define OFDM_SIFS_TIME 16
49 #define OFDM_PREAMBLE_TIME 20
50 #define OFDM_PLCP_BITS 22
51 #define OFDM_SYMBOL_TIME 4
53 #define OFDM_SIFS_TIME_HALF 32
54 #define OFDM_PREAMBLE_TIME_HALF 40
55 #define OFDM_PLCP_BITS_HALF 22
56 #define OFDM_SYMBOL_TIME_HALF 8
58 #define OFDM_SIFS_TIME_QUARTER 64
59 #define OFDM_PREAMBLE_TIME_QUARTER 80
60 #define OFDM_PLCP_BITS_QUARTER 22
61 #define OFDM_SYMBOL_TIME_QUARTER 16
65 #define INIT_CWMIN_11B 31
66 #define INIT_CWMAX 1023
67 #define INIT_SH_RETRY 10
68 #define INIT_LG_RETRY 10
69 #define INIT_SSH_RETRY 32
70 #define INIT_SLG_RETRY 32
72 #define ATH9K_SLOT_TIME_6 6
73 #define ATH9K_SLOT_TIME_9 9
74 #define ATH9K_SLOT_TIME_20 20
76 #define ATH9K_TXERR_XRETRY 0x01
77 #define ATH9K_TXERR_FILT 0x02
78 #define ATH9K_TXERR_FIFO 0x04
79 #define ATH9K_TXERR_XTXOP 0x08
80 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
81 #define ATH9K_TX_ACKED 0x20
82 #define ATH9K_TXERR_MASK \
83 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
84 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
86 #define ATH9K_TX_BA 0x01
87 #define ATH9K_TX_PWRMGMT 0x02
88 #define ATH9K_TX_DESC_CFG_ERR 0x04
89 #define ATH9K_TX_DATA_UNDERRUN 0x08
90 #define ATH9K_TX_DELIM_UNDERRUN 0x10
91 #define ATH9K_TX_SW_FILTERED 0x80
94 #define MIN_TX_FIFO_THRESHOLD 0x1
97 * Single stream device AR9285 and AR9271 require 2 KB
98 * to work around a hardware issue, all other devices
99 * have can use the max 4 KB limit.
101 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
103 struct ath_tx_status {
132 struct ath_rx_status {
159 struct ath_htc_rx_status {
185 #define ATH9K_RXERR_CRC 0x01
186 #define ATH9K_RXERR_PHY 0x02
187 #define ATH9K_RXERR_FIFO 0x04
188 #define ATH9K_RXERR_DECRYPT 0x08
189 #define ATH9K_RXERR_MIC 0x10
191 #define ATH9K_RX_MORE 0x01
192 #define ATH9K_RX_MORE_AGGR 0x02
193 #define ATH9K_RX_GI 0x04
194 #define ATH9K_RX_2040 0x08
195 #define ATH9K_RX_DELIM_CRC_PRE 0x10
196 #define ATH9K_RX_DELIM_CRC_POST 0x20
197 #define ATH9K_RX_DECRYPT_BUSY 0x40
199 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
200 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
203 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
204 ATH9K_PHYERR_TIMING = 1, /* Timing error */
205 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
206 ATH9K_PHYERR_RATE = 3, /* Illegal rate */
207 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
208 ATH9K_PHYERR_RADAR = 5, /* Radar detect */
209 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
210 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
212 ATH9K_PHYERR_OFDM_TIMING = 17,
213 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
214 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
215 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
216 ATH9K_PHYERR_OFDM_POWER_DROP = 21,
217 ATH9K_PHYERR_OFDM_SERVICE = 22,
218 ATH9K_PHYERR_OFDM_RESTART = 23,
219 ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
221 ATH9K_PHYERR_CCK_TIMING = 25,
222 ATH9K_PHYERR_CCK_HEADER_CRC = 26,
223 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
224 ATH9K_PHYERR_CCK_SERVICE = 30,
225 ATH9K_PHYERR_CCK_RESTART = 31,
226 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32,
227 ATH9K_PHYERR_CCK_POWER_DROP = 33,
229 ATH9K_PHYERR_HT_CRC_ERROR = 34,
230 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35,
231 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36,
233 ATH9K_PHYERR_MAX = 37,
245 #define ATH9K_TXDESC_CLRDMASK 0x0001
246 #define ATH9K_TXDESC_NOACK 0x0002
247 #define ATH9K_TXDESC_RTSENA 0x0004
248 #define ATH9K_TXDESC_CTSENA 0x0008
249 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
250 * the descriptor its marked on. We take a tx interrupt to reap
251 * descriptors when the h/w hits an EOL condition or
252 * when the descriptor is specifically marked to generate
253 * an interrupt with this flag. Descriptors should be
254 * marked periodically to insure timely replenishing of the
255 * supply needed for sending frames. Defering interrupts
256 * reduces system load and potentially allows more concurrent
257 * work to be done but if done to aggressively can cause
258 * senders to backup. When the hardware queue is left too
259 * large rate control information may also be too out of
260 * date. An Alternative for this is TX interrupt mitigation
261 * but this needs more testing. */
262 #define ATH9K_TXDESC_INTREQ 0x0010
263 #define ATH9K_TXDESC_VEOL 0x0020
264 #define ATH9K_TXDESC_EXT_ONLY 0x0040
265 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
266 #define ATH9K_TXDESC_VMF 0x0100
267 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
268 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400
269 #define ATH9K_TXDESC_LDPC 0x00010000
271 #define ATH9K_RXDESC_INTREQ 0x0020
315 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
316 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
318 #define ds_ctl2 u.tx.ctl2
319 #define ds_ctl3 u.tx.ctl3
320 #define ds_ctl4 u.tx.ctl4
321 #define ds_ctl5 u.tx.ctl5
322 #define ds_ctl6 u.tx.ctl6
323 #define ds_ctl7 u.tx.ctl7
324 #define ds_ctl8 u.tx.ctl8
325 #define ds_ctl9 u.tx.ctl9
326 #define ds_ctl10 u.tx.ctl10
327 #define ds_ctl11 u.tx.ctl11
329 #define ds_txstatus0 u.tx.status0
330 #define ds_txstatus1 u.tx.status1
331 #define ds_txstatus2 u.tx.status2
332 #define ds_txstatus3 u.tx.status3
333 #define ds_txstatus4 u.tx.status4
334 #define ds_txstatus5 u.tx.status5
335 #define ds_txstatus6 u.tx.status6
336 #define ds_txstatus7 u.tx.status7
337 #define ds_txstatus8 u.tx.status8
338 #define ds_txstatus9 u.tx.status9
340 #define ds_rxstatus0 u.rx.status0
341 #define ds_rxstatus1 u.rx.status1
342 #define ds_rxstatus2 u.rx.status2
343 #define ds_rxstatus3 u.rx.status3
344 #define ds_rxstatus4 u.rx.status4
345 #define ds_rxstatus5 u.rx.status5
346 #define ds_rxstatus6 u.rx.status6
347 #define ds_rxstatus7 u.rx.status7
348 #define ds_rxstatus8 u.rx.status8
350 #define AR_FrameLen 0x00000fff
351 #define AR_VirtMoreFrag 0x00001000
352 #define AR_TxCtlRsvd00 0x0000e000
353 #define AR_XmitPower 0x003f0000
354 #define AR_XmitPower_S 16
355 #define AR_RTSEnable 0x00400000
356 #define AR_VEOL 0x00800000
357 #define AR_ClrDestMask 0x01000000
358 #define AR_TxCtlRsvd01 0x1e000000
359 #define AR_TxIntrReq 0x20000000
360 #define AR_DestIdxValid 0x40000000
361 #define AR_CTSEnable 0x80000000
363 #define AR_TxMore 0x00001000
364 #define AR_DestIdx 0x000fe000
365 #define AR_DestIdx_S 13
366 #define AR_FrameType 0x00f00000
367 #define AR_FrameType_S 20
368 #define AR_NoAck 0x01000000
369 #define AR_InsertTS 0x02000000
370 #define AR_CorruptFCS 0x04000000
371 #define AR_ExtOnly 0x08000000
372 #define AR_ExtAndCtl 0x10000000
373 #define AR_MoreAggr 0x20000000
374 #define AR_IsAggr 0x40000000
376 #define AR_BurstDur 0x00007fff
377 #define AR_BurstDur_S 0
378 #define AR_DurUpdateEna 0x00008000
379 #define AR_XmitDataTries0 0x000f0000
380 #define AR_XmitDataTries0_S 16
381 #define AR_XmitDataTries1 0x00f00000
382 #define AR_XmitDataTries1_S 20
383 #define AR_XmitDataTries2 0x0f000000
384 #define AR_XmitDataTries2_S 24
385 #define AR_XmitDataTries3 0xf0000000
386 #define AR_XmitDataTries3_S 28
388 #define AR_XmitRate0 0x000000ff
389 #define AR_XmitRate0_S 0
390 #define AR_XmitRate1 0x0000ff00
391 #define AR_XmitRate1_S 8
392 #define AR_XmitRate2 0x00ff0000
393 #define AR_XmitRate2_S 16
394 #define AR_XmitRate3 0xff000000
395 #define AR_XmitRate3_S 24
397 #define AR_PacketDur0 0x00007fff
398 #define AR_PacketDur0_S 0
399 #define AR_RTSCTSQual0 0x00008000
400 #define AR_PacketDur1 0x7fff0000
401 #define AR_PacketDur1_S 16
402 #define AR_RTSCTSQual1 0x80000000
404 #define AR_PacketDur2 0x00007fff
405 #define AR_PacketDur2_S 0
406 #define AR_RTSCTSQual2 0x00008000
407 #define AR_PacketDur3 0x7fff0000
408 #define AR_PacketDur3_S 16
409 #define AR_RTSCTSQual3 0x80000000
411 #define AR_AggrLen 0x0000ffff
412 #define AR_AggrLen_S 0
413 #define AR_TxCtlRsvd60 0x00030000
414 #define AR_PadDelim 0x03fc0000
415 #define AR_PadDelim_S 18
416 #define AR_EncrType 0x0c000000
417 #define AR_EncrType_S 26
418 #define AR_TxCtlRsvd61 0xf0000000
419 #define AR_LDPC 0x80000000
421 #define AR_2040_0 0x00000001
422 #define AR_GI0 0x00000002
423 #define AR_ChainSel0 0x0000001c
424 #define AR_ChainSel0_S 2
425 #define AR_2040_1 0x00000020
426 #define AR_GI1 0x00000040
427 #define AR_ChainSel1 0x00000380
428 #define AR_ChainSel1_S 7
429 #define AR_2040_2 0x00000400
430 #define AR_GI2 0x00000800
431 #define AR_ChainSel2 0x00007000
432 #define AR_ChainSel2_S 12
433 #define AR_2040_3 0x00008000
434 #define AR_GI3 0x00010000
435 #define AR_ChainSel3 0x000e0000
436 #define AR_ChainSel3_S 17
437 #define AR_RTSCTSRate 0x0ff00000
438 #define AR_RTSCTSRate_S 20
439 #define AR_STBC0 0x10000000
440 #define AR_STBC1 0x20000000
441 #define AR_STBC2 0x40000000
442 #define AR_STBC3 0x80000000
444 #define AR_TxRSSIAnt00 0x000000ff
445 #define AR_TxRSSIAnt00_S 0
446 #define AR_TxRSSIAnt01 0x0000ff00
447 #define AR_TxRSSIAnt01_S 8
448 #define AR_TxRSSIAnt02 0x00ff0000
449 #define AR_TxRSSIAnt02_S 16
450 #define AR_TxStatusRsvd00 0x3f000000
451 #define AR_TxBaStatus 0x40000000
452 #define AR_TxStatusRsvd01 0x80000000
455 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
456 * transmitted successfully. If clear, no ACK or BA was received to indicate
457 * successful transmission when we were expecting an ACK or BA.
459 #define AR_FrmXmitOK 0x00000001
460 #define AR_ExcessiveRetries 0x00000002
461 #define AR_FIFOUnderrun 0x00000004
462 #define AR_Filtered 0x00000008
463 #define AR_RTSFailCnt 0x000000f0
464 #define AR_RTSFailCnt_S 4
465 #define AR_DataFailCnt 0x00000f00
466 #define AR_DataFailCnt_S 8
467 #define AR_VirtRetryCnt 0x0000f000
468 #define AR_VirtRetryCnt_S 12
469 #define AR_TxDelimUnderrun 0x00010000
470 #define AR_TxDataUnderrun 0x00020000
471 #define AR_DescCfgErr 0x00040000
472 #define AR_TxTimerExpired 0x00080000
473 #define AR_TxStatusRsvd10 0xfff00000
475 #define AR_SendTimestamp ds_txstatus2
476 #define AR_BaBitmapLow ds_txstatus3
477 #define AR_BaBitmapHigh ds_txstatus4
479 #define AR_TxRSSIAnt10 0x000000ff
480 #define AR_TxRSSIAnt10_S 0
481 #define AR_TxRSSIAnt11 0x0000ff00
482 #define AR_TxRSSIAnt11_S 8
483 #define AR_TxRSSIAnt12 0x00ff0000
484 #define AR_TxRSSIAnt12_S 16
485 #define AR_TxRSSICombined 0xff000000
486 #define AR_TxRSSICombined_S 24
488 #define AR_TxTid 0xf0000000
489 #define AR_TxTid_S 28
491 #define AR_TxEVM0 ds_txstatus5
492 #define AR_TxEVM1 ds_txstatus6
493 #define AR_TxEVM2 ds_txstatus7
495 #define AR_TxDone 0x00000001
496 #define AR_SeqNum 0x00001ffe
497 #define AR_SeqNum_S 1
498 #define AR_TxStatusRsvd80 0x0001e000
499 #define AR_TxOpExceeded 0x00020000
500 #define AR_TxStatusRsvd81 0x001c0000
501 #define AR_FinalTxIdx 0x00600000
502 #define AR_FinalTxIdx_S 21
503 #define AR_TxStatusRsvd82 0x01800000
504 #define AR_PowerMgmt 0x02000000
505 #define AR_TxStatusRsvd83 0xfc000000
507 #define AR_RxCTLRsvd00 0xffffffff
509 #define AR_RxCtlRsvd00 0x00001000
510 #define AR_RxIntrReq 0x00002000
511 #define AR_RxCtlRsvd01 0xffffc000
513 #define AR_RxRSSIAnt00 0x000000ff
514 #define AR_RxRSSIAnt00_S 0
515 #define AR_RxRSSIAnt01 0x0000ff00
516 #define AR_RxRSSIAnt01_S 8
517 #define AR_RxRSSIAnt02 0x00ff0000
518 #define AR_RxRSSIAnt02_S 16
519 #define AR_RxRate 0xff000000
520 #define AR_RxRate_S 24
521 #define AR_RxStatusRsvd00 0xff000000
523 #define AR_DataLen 0x00000fff
524 #define AR_RxMore 0x00001000
525 #define AR_NumDelim 0x003fc000
526 #define AR_NumDelim_S 14
527 #define AR_RxStatusRsvd10 0xff800000
529 #define AR_RcvTimestamp ds_rxstatus2
531 #define AR_GI 0x00000001
532 #define AR_2040 0x00000002
533 #define AR_Parallel40 0x00000004
534 #define AR_Parallel40_S 2
535 #define AR_RxStatusRsvd30 0x000000f8
536 #define AR_RxAntenna 0xffffff00
537 #define AR_RxAntenna_S 8
539 #define AR_RxRSSIAnt10 0x000000ff
540 #define AR_RxRSSIAnt10_S 0
541 #define AR_RxRSSIAnt11 0x0000ff00
542 #define AR_RxRSSIAnt11_S 8
543 #define AR_RxRSSIAnt12 0x00ff0000
544 #define AR_RxRSSIAnt12_S 16
545 #define AR_RxRSSICombined 0xff000000
546 #define AR_RxRSSICombined_S 24
548 #define AR_RxEVM0 ds_rxstatus4
549 #define AR_RxEVM1 ds_rxstatus5
550 #define AR_RxEVM2 ds_rxstatus6
552 #define AR_RxDone 0x00000001
553 #define AR_RxFrameOK 0x00000002
554 #define AR_CRCErr 0x00000004
555 #define AR_DecryptCRCErr 0x00000008
556 #define AR_PHYErr 0x00000010
557 #define AR_MichaelErr 0x00000020
558 #define AR_PreDelimCRCErr 0x00000040
559 #define AR_RxStatusRsvd70 0x00000080
560 #define AR_RxKeyIdxValid 0x00000100
561 #define AR_KeyIdx 0x0000fe00
562 #define AR_KeyIdx_S 9
563 #define AR_PHYErrCode 0x0000ff00
564 #define AR_PHYErrCode_S 8
565 #define AR_RxMoreAggr 0x00010000
566 #define AR_RxAggr 0x00020000
567 #define AR_PostDelimCRCErr 0x00040000
568 #define AR_RxStatusRsvd71 0x3ff80000
569 #define AR_DecryptBusyErr 0x40000000
570 #define AR_KeyMiss 0x80000000
572 enum ath9k_tx_queue {
573 ATH9K_TX_QUEUE_INACTIVE = 0,
575 ATH9K_TX_QUEUE_BEACON,
577 ATH9K_TX_QUEUE_UAPSD,
578 ATH9K_TX_QUEUE_PSPOLL
581 #define ATH9K_NUM_TX_QUEUES 10
583 /* Used as a queue subtype instead of a WMM AC */
584 #define ATH9K_WME_UPSD 4
586 enum ath9k_tx_queue_flags {
587 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
588 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
589 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
590 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
591 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
592 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
593 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
594 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
595 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
598 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
599 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
601 #define ATH9K_DECOMP_MASK_SIZE 128
602 #define ATH9K_READY_TIME_LO_BOUND 50
603 #define ATH9K_READY_TIME_HI_BOUND 96
605 enum ath9k_pkt_type {
606 ATH9K_PKT_TYPE_NORMAL = 0,
608 ATH9K_PKT_TYPE_PSPOLL,
609 ATH9K_PKT_TYPE_BEACON,
610 ATH9K_PKT_TYPE_PROBE_RESP,
611 ATH9K_PKT_TYPE_CHIRP,
612 ATH9K_PKT_TYPE_GRP_POLL,
615 struct ath9k_tx_queue_info {
617 enum ath9k_tx_queue tqi_type;
619 enum ath9k_tx_queue_flags tqi_qflags;
627 u32 tqi_cbrOverflowLimit;
634 enum ath9k_rx_filter {
635 ATH9K_RX_FILTER_UCAST = 0x00000001,
636 ATH9K_RX_FILTER_MCAST = 0x00000002,
637 ATH9K_RX_FILTER_BCAST = 0x00000004,
638 ATH9K_RX_FILTER_CONTROL = 0x00000008,
639 ATH9K_RX_FILTER_BEACON = 0x00000010,
640 ATH9K_RX_FILTER_PROM = 0x00000020,
641 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
642 ATH9K_RX_FILTER_PHYERR = 0x00000100,
643 ATH9K_RX_FILTER_MYBEACON = 0x00000200,
644 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
645 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
646 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
647 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
650 #define ATH9K_RATESERIES_RTS_CTS 0x0001
651 #define ATH9K_RATESERIES_2040 0x0002
652 #define ATH9K_RATESERIES_HALFGI 0x0004
653 #define ATH9K_RATESERIES_STBC 0x0008
655 struct ath9k_11n_rate_series {
663 struct ath9k_keyval {
667 u8 kv_val[16]; /* TK */
668 u8 kv_mic[8]; /* Michael MIC key */
669 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
670 * supports both MIC keys in the same key cache entry;
671 * in that case, kv_mic is the RX key) */
674 enum ath9k_key_type {
675 ATH9K_KEY_TYPE_CLEAR,
682 ATH9K_CIPHER_WEP = 0,
683 ATH9K_CIPHER_AES_OCB = 1,
684 ATH9K_CIPHER_AES_CCM = 2,
685 ATH9K_CIPHER_CKIP = 3,
686 ATH9K_CIPHER_TKIP = 4,
687 ATH9K_CIPHER_CLR = 5,
688 ATH9K_CIPHER_MIC = 127
692 struct ath9k_channel;
694 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
695 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
696 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
697 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
698 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
699 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
700 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
701 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
702 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
703 const struct ath9k_tx_queue_info *qinfo);
704 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
705 struct ath9k_tx_queue_info *qinfo);
706 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
707 const struct ath9k_tx_queue_info *qinfo);
708 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
709 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
710 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
711 struct ath_rx_status *rs, u64 tsf);
712 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
713 u32 size, u32 flags);
714 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
715 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
716 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
717 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
718 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
719 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
720 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
722 /* Interrupt Handling */
723 bool ath9k_hw_intrpend(struct ath_hw *ah);
724 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
725 enum ath9k_int ints);
727 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);