drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static void ath_cache_conf_rate(struct ath_softc *sc,
  22                                 struct ieee80211_conf *conf)
  23 {
  24         switch (conf->channel->band) {
  25         case IEEE80211_BAND_2GHZ:
  26                 if (conf_is_ht20(conf))
  27                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  28                 else if (conf_is_ht40_minus(conf))
  29                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  30                 else if (conf_is_ht40_plus(conf))
  31                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  32                 else
  33                         sc->cur_rate_mode = ATH9K_MODE_11G;
  34                 break;
  35         case IEEE80211_BAND_5GHZ:
  36                 if (conf_is_ht20(conf))
  37                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  38                 else if (conf_is_ht40_minus(conf))
  39                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  40                 else if (conf_is_ht40_plus(conf))
  41                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  42                 else
  43                         sc->cur_rate_mode = ATH9K_MODE_11A;
  44                 break;
  45         default:
  46                 BUG_ON(1);
  47                 break;
  48         }
  49 }
  50
  51 static void ath_update_txpow(struct ath_softc *sc)
  52 {
  53         struct ath_hw *ah = sc->sc_ah;
  54
  55         if (sc->curtxpow != sc->config.txpowlimit) {
  56                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  57                 /* read back in case value is clamped */
  58                 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  59         }
  60 }
  61
  62 static u8 parse_mpdudensity(u8 mpdudensity)
  63 {
  64         /*
  65          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  66          *   0 for no restriction
  67          *   1 for 1/4 us
  68          *   2 for 1/2 us
  69          *   3 for 1 us
  70          *   4 for 2 us
  71          *   5 for 4 us
  72          *   6 for 8 us
  73          *   7 for 16 us
  74          */
  75         switch (mpdudensity) {
  76         case 0:
  77                 return 0;
  78         case 1:
  79         case 2:
  80         case 3:
  81                 /* Our lower layer calculations limit our precision to
  82                    1 microsecond */
  83                 return 1;
  84         case 4:
  85                 return 2;
  86         case 5:
  87                 return 4;
  88         case 6:
  89                 return 8;
  90         case 7:
  91                 return 16;
  92         default:
  93                 return 0;
  94         }
  95 }
  96
  97 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  98                                                 struct ieee80211_hw *hw)
  99 {
 100         struct ieee80211_channel *curchan = hw->conf.channel;
 101         struct ath9k_channel *channel;
 102         u8 chan_idx;
 103
 104         chan_idx = curchan->hw_value;
 105         channel = &sc->sc_ah->channels[chan_idx];
 106         ath9k_update_ichannel(sc, hw, channel);
 107         return channel;
 108 }
 109
 110 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 111 {
 112         unsigned long flags;
 113         bool ret;
 114
 115         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 116         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 117         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 118
 119         return ret;
 120 }
 121
 122 void ath9k_ps_wakeup(struct ath_softc *sc)
 123 {
 124         unsigned long flags;
 125
 126         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 127         if (++sc->ps_usecount != 1)
 128                 goto unlock;
 129
 130         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 131
 132  unlock:
 133         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 134 }
 135
 136 void ath9k_ps_restore(struct ath_softc *sc)
 137 {
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 141         if (--sc->ps_usecount != 0)
 142                 goto unlock;
 143
 144         if (sc->ps_idle)
 145                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 146         else if (sc->ps_enabled &&
 147                  !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 148                               PS_WAIT_FOR_CAB |
 149                               PS_WAIT_FOR_PSPOLL_DATA |
 150                               PS_WAIT_FOR_TX_ACK)))
 151                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 152
 153  unlock:
 154         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 155 }
 156
 157 static void ath_start_ani(struct ath_common *common)
 158 {
 159         struct ath_hw *ah = common->ah;
 160         unsigned long timestamp = jiffies_to_msecs(jiffies);
 161         struct ath_softc *sc = (struct ath_softc *) common->priv;
 162
 163         if (!(sc->sc_flags & SC_OP_ANI_RUN))
 164                 return;
 165
 166         if (sc->sc_flags & SC_OP_OFFCHANNEL)
 167                 return;
 168
 169         common->ani.longcal_timer = timestamp;
 170         common->ani.shortcal_timer = timestamp;
 171         common->ani.checkani_timer = timestamp;
 172
 173         mod_timer(&common->ani.timer,
 174                   jiffies +
 175                         msecs_to_jiffies((u32)ah->config.ani_poll_interval));
 176 }
 177
 178 /*
 179  * Set/change channels.  If the channel is really being changed, it's done
 180  * by reseting the chip.  To accomplish this we must first cleanup any pending
 181  * DMA, then restart stuff.
 182 */
 183 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 184                     struct ath9k_channel *hchan)
 185 {
 186         struct ath_wiphy *aphy = hw->priv;
 187         struct ath_hw *ah = sc->sc_ah;
 188         struct ath_common *common = ath9k_hw_common(ah);
 189         struct ieee80211_conf *conf = &common->hw->conf;
 190         bool fastcc = true, stopped;
 191         struct ieee80211_channel *channel = hw->conf.channel;
 192         struct ath9k_hw_cal_data *caldata = NULL;
 193         int r;
 194
 195         if (sc->sc_flags & SC_OP_INVALID)
 196                 return -EIO;
 197
 198         del_timer_sync(&common->ani.timer);
 199         cancel_work_sync(&sc->paprd_work);
 200         cancel_work_sync(&sc->hw_check_work);
 201         cancel_delayed_work_sync(&sc->tx_complete_work);
 202
 203         ath9k_ps_wakeup(sc);
 204
 205         /*
 206          * This is only performed if the channel settings have
 207          * actually changed.
 208          *
 209          * To switch channels clear any pending DMA operations;
 210          * wait long enough for the RX fifo to drain, reset the
 211          * hardware at the new frequency, and then re-enable
 212          * the relevant bits of the h/w.
 213          */
 214         ath9k_hw_set_interrupts(ah, 0);
 215         ath_drain_all_txq(sc, false);
 216         stopped = ath_stoprecv(sc);
 217
 218         /* XXX: do not flush receive queue here. We don't want
 219          * to flush data frames already in queue because of
 220          * changing channel. */
 221
 222         if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
 223                 fastcc = false;
 224
 225         if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
 226                 caldata = &aphy->caldata;
 227
 228         ath_print(common, ATH_DBG_CONFIG,
 229                   "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
 230                   sc->sc_ah->curchan->channel,
 231                   channel->center_freq, conf_is_ht40(conf),
 232                   fastcc);
 233
 234         spin_lock_bh(&sc->sc_resetlock);
 235
 236         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 237         if (r) {
 238                 ath_print(common, ATH_DBG_FATAL,
 239                           "Unable to reset channel (%u MHz), "
 240                           "reset status %d\n",
 241                           channel->center_freq, r);
 242                 spin_unlock_bh(&sc->sc_resetlock);
 243                 goto ps_restore;
 244         }
 245         spin_unlock_bh(&sc->sc_resetlock);
 246
 247         if (ath_startrecv(sc) != 0) {
 248                 ath_print(common, ATH_DBG_FATAL,
 249                           "Unable to restart recv logic\n");
 250                 r = -EIO;
 251                 goto ps_restore;
 252         }
 253
 254         ath_cache_conf_rate(sc, &hw->conf);
 255         ath_update_txpow(sc);
 256         ath9k_hw_set_interrupts(ah, ah->imask);
 257
 258         if (!(sc->sc_flags & (SC_OP_OFFCHANNEL | SC_OP_SCANNING))) {
 259                 ath_start_ani(common);
 260                 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
 261                 ath_beacon_config(sc, NULL);
 262         }
 263
 264  ps_restore:
 265         ath9k_ps_restore(sc);
 266         return r;
 267 }
 268
 269 static void ath_paprd_activate(struct ath_softc *sc)
 270 {
 271         struct ath_hw *ah = sc->sc_ah;
 272         struct ath9k_hw_cal_data *caldata = ah->caldata;
 273         int chain;
 274
 275         if (!caldata || !caldata->paprd_done)
 276                 return;
 277
 278         ath9k_ps_wakeup(sc);
 279         ar9003_paprd_enable(ah, false);
 280         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
 281                 if (!(ah->caps.tx_chainmask & BIT(chain)))
 282                         continue;
 283
 284                 ar9003_paprd_populate_single_table(ah, caldata, chain);
 285         }
 286
 287         ar9003_paprd_enable(ah, true);
 288         ath9k_ps_restore(sc);
 289 }
 290
 291 void ath_paprd_calibrate(struct work_struct *work)
 292 {
 293         struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
 294         struct ieee80211_hw *hw = sc->hw;
 295         struct ath_hw *ah = sc->sc_ah;
 296         struct ieee80211_hdr *hdr;
 297         struct sk_buff *skb = NULL;
 298         struct ieee80211_tx_info *tx_info;
 299         int band = hw->conf.channel->band;
 300         struct ieee80211_supported_band *sband = &sc->sbands[band];
 301         struct ath_tx_control txctl;
 302         struct ath9k_hw_cal_data *caldata = ah->caldata;
 303         int qnum, ftype;
 304         int chain_ok = 0;
 305         int chain;
 306         int len = 1800;
 307         int time_left;
 308         int i;
 309
 310         if (!caldata)
 311                 return;
 312
 313         skb = alloc_skb(len, GFP_KERNEL);
 314         if (!skb)
 315                 return;
 316
 317         tx_info = IEEE80211_SKB_CB(skb);
 318
 319         skb_put(skb, len);
 320         memset(skb->data, 0, len);
 321         hdr = (struct ieee80211_hdr *)skb->data;
 322         ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
 323         hdr->frame_control = cpu_to_le16(ftype);
 324         hdr->duration_id = cpu_to_le16(10);
 325         memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
 326         memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
 327         memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
 328
 329         memset(&txctl, 0, sizeof(txctl));
 330         qnum = sc->tx.hwq_map[WME_AC_BE];
 331         txctl.txq = &sc->tx.txq[qnum];
 332
 333         ath9k_ps_wakeup(sc);
 334         ar9003_paprd_init_table(ah);
 335         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
 336                 if (!(ah->caps.tx_chainmask & BIT(chain)))
 337                         continue;
 338
 339                 chain_ok = 0;
 340                 memset(tx_info, 0, sizeof(*tx_info));
 341                 tx_info->band = band;
 342
 343                 for (i = 0; i < 4; i++) {
 344                         tx_info->control.rates[i].idx = sband->n_bitrates - 1;
 345                         tx_info->control.rates[i].count = 6;
 346                 }
 347
 348                 init_completion(&sc->paprd_complete);
 349                 ar9003_paprd_setup_gain_table(ah, chain);
 350                 txctl.paprd = BIT(chain);
 351                 if (ath_tx_start(hw, skb, &txctl) != 0)
 352                         break;
 353
 354                 time_left = wait_for_completion_timeout(&sc->paprd_complete,
 355                                 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
 356                 if (!time_left) {
 357                         ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 358                                   "Timeout waiting for paprd training on "
 359                                   "TX chain %d\n",
 360                                   chain);
 361                         goto fail_paprd;
 362                 }
 363
 364                 if (!ar9003_paprd_is_done(ah))
 365                         break;
 366
 367                 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
 368                         break;
 369
 370                 chain_ok = 1;
 371         }
 372         kfree_skb(skb);
 373
 374         if (chain_ok) {
 375                 caldata->paprd_done = true;
 376                 ath_paprd_activate(sc);
 377         }
 378
 379 fail_paprd:
 380         ath9k_ps_restore(sc);
 381 }
 382
 383 /*
 384  *  This routine performs the periodic noise floor calibration function
 385  *  that is used to adjust and optimize the chip performance.  This
 386  *  takes environmental changes (location, temperature) into account.
 387  *  When the task is complete, it reschedules itself depending on the
 388  *  appropriate interval that was calculated.
 389  */
 390 void ath_ani_calibrate(unsigned long data)
 391 {
 392         struct ath_softc *sc = (struct ath_softc *)data;
 393         struct ath_hw *ah = sc->sc_ah;
 394         struct ath_common *common = ath9k_hw_common(ah);
 395         bool longcal = false;
 396         bool shortcal = false;
 397         bool aniflag = false;
 398         unsigned int timestamp = jiffies_to_msecs(jiffies);
 399         u32 cal_interval, short_cal_interval;
 400
 401         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 402                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 403
 404         /* Only calibrate if awake */
 405         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 406                 goto set_timer;
 407
 408         ath9k_ps_wakeup(sc);
 409
 410         /* Long calibration runs independently of short calibration. */
 411         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 412                 longcal = true;
 413                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 414                 common->ani.longcal_timer = timestamp;
 415         }
 416
 417         /* Short calibration applies only while caldone is false */
 418         if (!common->ani.caldone) {
 419                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
 420                         shortcal = true;
 421                         ath_print(common, ATH_DBG_ANI,
 422                                   "shortcal @%lu\n", jiffies);
 423                         common->ani.shortcal_timer = timestamp;
 424                         common->ani.resetcal_timer = timestamp;
 425                 }
 426         } else {
 427                 if ((timestamp - common->ani.resetcal_timer) >=
 428                     ATH_RESTART_CALINTERVAL) {
 429                         common->ani.caldone = ath9k_hw_reset_calvalid(ah);
 430                         if (common->ani.caldone)
 431                                 common->ani.resetcal_timer = timestamp;
 432                 }
 433         }
 434
 435         /* Verify whether we must check ANI */
 436         if ((timestamp - common->ani.checkani_timer) >=
 437              ah->config.ani_poll_interval) {
 438                 aniflag = true;
 439                 common->ani.checkani_timer = timestamp;
 440         }
 441
 442         /* Skip all processing if there's nothing to do. */
 443         if (longcal || shortcal || aniflag) {
 444                 /* Call ANI routine if necessary */
 445                 if (aniflag)
 446                         ath9k_hw_ani_monitor(ah, ah->curchan);
 447
 448                 /* Perform calibration if necessary */
 449                 if (longcal || shortcal) {
 450                         common->ani.caldone =
 451                                 ath9k_hw_calibrate(ah,
 452                                                    ah->curchan,
 453                                                    common->rx_chainmask,
 454                                                    longcal);
 455
 456                         if (longcal)
 457                                 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 458                                                                      ah->curchan);
 459
 460                         ath_print(common, ATH_DBG_ANI,
 461                                   " calibrate chan %u/%x nf: %d\n",
 462                                   ah->curchan->channel,
 463                                   ah->curchan->channelFlags,
 464                                   common->ani.noise_floor);
 465                 }
 466         }
 467
 468         ath9k_ps_restore(sc);
 469
 470 set_timer:
 471         /*
 472         * Set timer interval based on previous results.
 473         * The interval must be the shortest necessary to satisfy ANI,
 474         * short calibration and long calibration.
 475         */
 476         cal_interval = ATH_LONG_CALINTERVAL;
 477         if (sc->sc_ah->config.enable_ani)
 478                 cal_interval = min(cal_interval,
 479                                    (u32)ah->config.ani_poll_interval);
 480         if (!common->ani.caldone)
 481                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 482
 483         mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 484         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
 485                 if (!ah->caldata->paprd_done)
 486                         ieee80211_queue_work(sc->hw, &sc->paprd_work);
 487                 else
 488                         ath_paprd_activate(sc);
 489         }
 490 }
 491
 492 /*
 493  * Update tx/rx chainmask. For legacy association,
 494  * hard code chainmask to 1x1, for 11n association, use
 495  * the chainmask configuration, for bt coexistence, use
 496  * the chainmask configuration even in legacy mode.
 497  */
 498 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 499 {
 500         struct ath_hw *ah = sc->sc_ah;
 501         struct ath_common *common = ath9k_hw_common(ah);
 502
 503         if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
 504             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 505                 common->tx_chainmask = ah->caps.tx_chainmask;
 506                 common->rx_chainmask = ah->caps.rx_chainmask;
 507         } else {
 508                 common->tx_chainmask = 1;
 509                 common->rx_chainmask = 1;
 510         }
 511
 512         ath_print(common, ATH_DBG_CONFIG,
 513                   "tx chmask: %d, rx chmask: %d\n",
 514                   common->tx_chainmask,
 515                   common->rx_chainmask);
 516 }
 517
 518 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 519 {
 520         struct ath_node *an;
 521
 522         an = (struct ath_node *)sta->drv_priv;
 523
 524         if (sc->sc_flags & SC_OP_TXAGGR) {
 525                 ath_tx_node_init(sc, an);
 526                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 527                                      sta->ht_cap.ampdu_factor);
 528                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 529                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 530         }
 531 }
 532
 533 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 534 {
 535         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 536
 537         if (sc->sc_flags & SC_OP_TXAGGR)
 538                 ath_tx_node_cleanup(sc, an);
 539 }
 540
 541 void ath_hw_check(struct work_struct *work)
 542 {
 543         struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
 544         int i;
 545
 546         ath9k_ps_wakeup(sc);
 547
 548         for (i = 0; i < 3; i++) {
 549                 if (ath9k_hw_check_alive(sc->sc_ah))
 550                         goto out;
 551
 552                 msleep(1);
 553         }
 554         ath_reset(sc, false);
 555
 556 out:
 557         ath9k_ps_restore(sc);
 558 }
 559
 560 void ath9k_tasklet(unsigned long data)
 561 {
 562         struct ath_softc *sc = (struct ath_softc *)data;
 563         struct ath_hw *ah = sc->sc_ah;
 564         struct ath_common *common = ath9k_hw_common(ah);
 565
 566         u32 status = sc->intrstatus;
 567         u32 rxmask;
 568
 569         ath9k_ps_wakeup(sc);
 570
 571         if (status & ATH9K_INT_FATAL) {
 572                 ath_reset(sc, false);
 573                 ath9k_ps_restore(sc);
 574                 return;
 575         }
 576
 577         if (!ath9k_hw_check_alive(ah))
 578                 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 579
 580         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 581                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 582                           ATH9K_INT_RXORN);
 583         else
 584                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 585
 586         if (status & rxmask) {
 587                 spin_lock_bh(&sc->rx.rxflushlock);
 588
 589                 /* Check for high priority Rx first */
 590                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 591                     (status & ATH9K_INT_RXHP))
 592                         ath_rx_tasklet(sc, 0, true);
 593
 594                 ath_rx_tasklet(sc, 0, false);
 595                 spin_unlock_bh(&sc->rx.rxflushlock);
 596         }
 597
 598         if (status & ATH9K_INT_TX) {
 599                 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 600                         ath_tx_edma_tasklet(sc);
 601                 else
 602                         ath_tx_tasklet(sc);
 603         }
 604
 605         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 606                 /*
 607                  * TSF sync does not look correct; remain awake to sync with
 608                  * the next Beacon.
 609                  */
 610                 ath_print(common, ATH_DBG_PS,
 611                           "TSFOOR - Sync with next Beacon\n");
 612                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 613         }
 614
 615         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 616                 if (status & ATH9K_INT_GENTIMER)
 617                         ath_gen_timer_isr(sc->sc_ah);
 618
 619         /* re-enable hardware interrupt */
 620         ath9k_hw_set_interrupts(ah, ah->imask);
 621         ath9k_ps_restore(sc);
 622 }
 623
 624 irqreturn_t ath_isr(int irq, void *dev)
 625 {
 626 #define SCHED_INTR (                            \
 627                 ATH9K_INT_FATAL |               \
 628                 ATH9K_INT_RXORN |               \
 629                 ATH9K_INT_RXEOL |               \
 630                 ATH9K_INT_RX |                  \
 631                 ATH9K_INT_RXLP |                \
 632                 ATH9K_INT_RXHP |                \
 633                 ATH9K_INT_TX |                  \
 634                 ATH9K_INT_BMISS |               \
 635                 ATH9K_INT_CST |                 \
 636                 ATH9K_INT_TSFOOR |              \
 637                 ATH9K_INT_GENTIMER)
 638
 639         struct ath_softc *sc = dev;
 640         struct ath_hw *ah = sc->sc_ah;
 641         enum ath9k_int status;
 642         bool sched = false;
 643
 644         /*
 645          * The hardware is not ready/present, don't
 646          * touch anything. Note this can happen early
 647          * on if the IRQ is shared.
 648          */
 649         if (sc->sc_flags & SC_OP_INVALID)
 650                 return IRQ_NONE;
 651
 652
 653         /* shared irq, not for us */
 654
 655         if (!ath9k_hw_intrpend(ah))
 656                 return IRQ_NONE;
 657
 658         /*
 659          * Figure out the reason(s) for the interrupt.  Note
 660          * that the hal returns a pseudo-ISR that may include
 661          * bits we haven't explicitly enabled so we mask the
 662          * value to insure we only process bits we requested.
 663          */
 664         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 665         status &= ah->imask;    /* discard unasked-for bits */
 666
 667         /*
 668          * If there are no status bits set, then this interrupt was not
 669          * for me (should have been caught above).
 670          */
 671         if (!status)
 672                 return IRQ_NONE;
 673
 674         /* Cache the status */
 675         sc->intrstatus = status;
 676
 677         if (status & SCHED_INTR)
 678                 sched = true;
 679
 680         /*
 681          * If a FATAL or RXORN interrupt is received, we have to reset the
 682          * chip immediately.
 683          */
 684         if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
 685             !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
 686                 goto chip_reset;
 687
 688         if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 689             (status & ATH9K_INT_BB_WATCHDOG)) {
 690                 ar9003_hw_bb_watchdog_dbg_info(ah);
 691                 goto chip_reset;
 692         }
 693
 694         if (status & ATH9K_INT_SWBA)
 695                 tasklet_schedule(&sc->bcon_tasklet);
 696
 697         if (status & ATH9K_INT_TXURN)
 698                 ath9k_hw_updatetxtriglevel(ah, true);
 699
 700         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 701                 if (status & ATH9K_INT_RXEOL) {
 702                         ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 703                         ath9k_hw_set_interrupts(ah, ah->imask);
 704                 }
 705         }
 706
 707         if (status & ATH9K_INT_MIB) {
 708                 /*
 709                  * Disable interrupts until we service the MIB
 710                  * interrupt; otherwise it will continue to
 711                  * fire.
 712                  */
 713                 ath9k_hw_set_interrupts(ah, 0);
 714                 /*
 715                  * Let the hal handle the event. We assume
 716                  * it will clear whatever condition caused
 717                  * the interrupt.
 718                  */
 719                 ath9k_hw_procmibevent(ah);
 720                 ath9k_hw_set_interrupts(ah, ah->imask);
 721         }
 722
 723         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 724                 if (status & ATH9K_INT_TIM_TIMER) {
 725                         /* Clear RxAbort bit so that we can
 726                          * receive frames */
 727                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 728                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 729                         sc->ps_flags |= PS_WAIT_FOR_BEACON;
 730                 }
 731
 732 chip_reset:
 733
 734         ath_debug_stat_interrupt(sc, status);
 735
 736         if (sched) {
 737                 /* turn off every interrupt except SWBA */
 738                 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
 739                 tasklet_schedule(&sc->intr_tq);
 740         }
 741
 742         return IRQ_HANDLED;
 743
 744 #undef SCHED_INTR
 745 }
 746
 747 static u32 ath_get_extchanmode(struct ath_softc *sc,
 748                                struct ieee80211_channel *chan,
 749                                enum nl80211_channel_type channel_type)
 750 {
 751         u32 chanmode = 0;
 752
 753         switch (chan->band) {
 754         case IEEE80211_BAND_2GHZ:
 755                 switch(channel_type) {
 756                 case NL80211_CHAN_NO_HT:
 757                 case NL80211_CHAN_HT20:
 758                         chanmode = CHANNEL_G_HT20;
 759                         break;
 760                 case NL80211_CHAN_HT40PLUS:
 761                         chanmode = CHANNEL_G_HT40PLUS;
 762                         break;
 763                 case NL80211_CHAN_HT40MINUS:
 764                         chanmode = CHANNEL_G_HT40MINUS;
 765                         break;
 766                 }
 767                 break;
 768         case IEEE80211_BAND_5GHZ:
 769                 switch(channel_type) {
 770                 case NL80211_CHAN_NO_HT:
 771                 case NL80211_CHAN_HT20:
 772                         chanmode = CHANNEL_A_HT20;
 773                         break;
 774                 case NL80211_CHAN_HT40PLUS:
 775                         chanmode = CHANNEL_A_HT40PLUS;
 776                         break;
 777                 case NL80211_CHAN_HT40MINUS:
 778                         chanmode = CHANNEL_A_HT40MINUS;
 779                         break;
 780                 }
 781                 break;
 782         default:
 783                 break;
 784         }
 785
 786         return chanmode;
 787 }
 788
 789 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 790                                  struct ieee80211_vif *vif,
 791                                  struct ieee80211_bss_conf *bss_conf)
 792 {
 793         struct ath_hw *ah = sc->sc_ah;
 794         struct ath_common *common = ath9k_hw_common(ah);
 795
 796         if (bss_conf->assoc) {
 797                 ath_print(common, ATH_DBG_CONFIG,
 798                           "Bss Info ASSOC %d, bssid: %pM\n",
 799                            bss_conf->aid, common->curbssid);
 800
 801                 /* New association, store aid */
 802                 common->curaid = bss_conf->aid;
 803                 ath9k_hw_write_associd(ah);
 804
 805                 /*
 806                  * Request a re-configuration of Beacon related timers
 807                  * on the receipt of the first Beacon frame (i.e.,
 808                  * after time sync with the AP).
 809                  */
 810                 sc->ps_flags |= PS_BEACON_SYNC;
 811
 812                 /* Configure the beacon */
 813                 ath_beacon_config(sc, vif);
 814
 815                 /* Reset rssi stats */
 816                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
 817
 818                 sc->sc_flags |= SC_OP_ANI_RUN;
 819                 ath_start_ani(common);
 820         } else {
 821                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 822                 common->curaid = 0;
 823                 /* Stop ANI */
 824                 sc->sc_flags &= ~SC_OP_ANI_RUN;
 825                 del_timer_sync(&common->ani.timer);
 826         }
 827 }
 828
 829 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
 830 {
 831         struct ath_hw *ah = sc->sc_ah;
 832         struct ath_common *common = ath9k_hw_common(ah);
 833         struct ieee80211_channel *channel = hw->conf.channel;
 834         int r;
 835
 836         ath9k_ps_wakeup(sc);
 837         ath9k_hw_configpcipowersave(ah, 0, 0);
 838
 839         if (!ah->curchan)
 840                 ah->curchan = ath_get_curchannel(sc, sc->hw);
 841
 842         spin_lock_bh(&sc->sc_resetlock);
 843         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 844         if (r) {
 845                 ath_print(common, ATH_DBG_FATAL,
 846                           "Unable to reset channel (%u MHz), "
 847                           "reset status %d\n",
 848                           channel->center_freq, r);
 849         }
 850         spin_unlock_bh(&sc->sc_resetlock);
 851
 852         ath_update_txpow(sc);
 853         if (ath_startrecv(sc) != 0) {
 854                 ath_print(common, ATH_DBG_FATAL,
 855                           "Unable to restart recv logic\n");
 856                 return;
 857         }
 858
 859         if (sc->sc_flags & SC_OP_BEACONS)
 860                 ath_beacon_config(sc, NULL);    /* restart beacons */
 861
 862         /* Re-Enable  interrupts */
 863         ath9k_hw_set_interrupts(ah, ah->imask);
 864
 865         /* Enable LED */
 866         ath9k_hw_cfg_output(ah, ah->led_pin,
 867                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 868         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 869
 870         ieee80211_wake_queues(hw);
 871         ath9k_ps_restore(sc);
 872 }
 873
 874 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
 875 {
 876         struct ath_hw *ah = sc->sc_ah;
 877         struct ieee80211_channel *channel = hw->conf.channel;
 878         int r;
 879
 880         ath9k_ps_wakeup(sc);
 881         ieee80211_stop_queues(hw);
 882
 883         /*
 884          * Keep the LED on when the radio is disabled
 885          * during idle unassociated state.
 886          */
 887         if (!sc->ps_idle) {
 888                 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
 889                 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
 890         }
 891
 892         /* Disable interrupts */
 893         ath9k_hw_set_interrupts(ah, 0);
 894
 895         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
 896         ath_stoprecv(sc);               /* turn off frame recv */
 897         ath_flushrecv(sc);              /* flush recv queue */
 898
 899         if (!ah->curchan)
 900                 ah->curchan = ath_get_curchannel(sc, hw);
 901
 902         spin_lock_bh(&sc->sc_resetlock);
 903         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 904         if (r) {
 905                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
 906                           "Unable to reset channel (%u MHz), "
 907                           "reset status %d\n",
 908                           channel->center_freq, r);
 909         }
 910         spin_unlock_bh(&sc->sc_resetlock);
 911
 912         ath9k_hw_phy_disable(ah);
 913         ath9k_hw_configpcipowersave(ah, 1, 1);
 914         ath9k_ps_restore(sc);
 915         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
 916 }
 917
 918 int ath_reset(struct ath_softc *sc, bool retry_tx)
 919 {
 920         struct ath_hw *ah = sc->sc_ah;
 921         struct ath_common *common = ath9k_hw_common(ah);
 922         struct ieee80211_hw *hw = sc->hw;
 923         int r;
 924
 925         /* Stop ANI */
 926         del_timer_sync(&common->ani.timer);
 927
 928         ieee80211_stop_queues(hw);
 929
 930         ath9k_hw_set_interrupts(ah, 0);
 931         ath_drain_all_txq(sc, retry_tx);
 932         ath_stoprecv(sc);
 933         ath_flushrecv(sc);
 934
 935         spin_lock_bh(&sc->sc_resetlock);
 936         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
 937         if (r)
 938                 ath_print(common, ATH_DBG_FATAL,
 939                           "Unable to reset hardware; reset status %d\n", r);
 940         spin_unlock_bh(&sc->sc_resetlock);
 941
 942         if (ath_startrecv(sc) != 0)
 943                 ath_print(common, ATH_DBG_FATAL,
 944                           "Unable to start recv logic\n");
 945
 946         /*
 947          * We may be doing a reset in response to a request
 948          * that changes the channel so update any state that
 949          * might change as a result.
 950          */
 951         ath_cache_conf_rate(sc, &hw->conf);
 952
 953         ath_update_txpow(sc);
 954
 955         if (sc->sc_flags & SC_OP_BEACONS)
 956                 ath_beacon_config(sc, NULL);    /* restart beacons */
 957
 958         ath9k_hw_set_interrupts(ah, ah->imask);
 959
 960         if (retry_tx) {
 961                 int i;
 962                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 963                         if (ATH_TXQ_SETUP(sc, i)) {
 964                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
 965                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
 966                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
 967                         }
 968                 }
 969         }
 970
 971         ieee80211_wake_queues(hw);
 972
 973         /* Start ANI */
 974         ath_start_ani(common);
 975
 976         return r;
 977 }
 978
 979 static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 980 {
 981         int qnum;
 982
 983         switch (queue) {
 984         case 0:
 985                 qnum = sc->tx.hwq_map[WME_AC_VO];
 986                 break;
 987         case 1:
 988                 qnum = sc->tx.hwq_map[WME_AC_VI];
 989                 break;
 990         case 2:
 991                 qnum = sc->tx.hwq_map[WME_AC_BE];
 992                 break;
 993         case 3:
 994                 qnum = sc->tx.hwq_map[WME_AC_BK];
 995                 break;
 996         default:
 997                 qnum = sc->tx.hwq_map[WME_AC_BE];
 998                 break;
 999         }
1000
1001         return qnum;
1002 }
1003
1004 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1005 {
1006         int qnum;
1007
1008         switch (queue) {
1009         case WME_AC_VO:
1010                 qnum = 0;
1011                 break;
1012         case WME_AC_VI:
1013                 qnum = 1;
1014                 break;
1015         case WME_AC_BE:
1016                 qnum = 2;
1017                 break;
1018         case WME_AC_BK:
1019                 qnum = 3;
1020                 break;
1021         default:
1022                 qnum = -1;
1023                 break;
1024         }
1025
1026         return qnum;
1027 }
1028
1029 /* XXX: Remove me once we don't depend on ath9k_channel for all
1030  * this redundant data */
1031 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1032                            struct ath9k_channel *ichan)
1033 {
1034         struct ieee80211_channel *chan = hw->conf.channel;
1035         struct ieee80211_conf *conf = &hw->conf;
1036
1037         ichan->channel = chan->center_freq;
1038         ichan->chan = chan;
1039
1040         if (chan->band == IEEE80211_BAND_2GHZ) {
1041                 ichan->chanmode = CHANNEL_G;
1042                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
1043         } else {
1044                 ichan->chanmode = CHANNEL_A;
1045                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1046         }
1047
1048         if (conf_is_ht(conf))
1049                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1050                                             conf->channel_type);
1051 }
1052
1053 /**********************/
1054 /* mac80211 callbacks */
1055 /**********************/
1056
1057 static int ath9k_start(struct ieee80211_hw *hw)
1058 {
1059         struct ath_wiphy *aphy = hw->priv;
1060         struct ath_softc *sc = aphy->sc;
1061         struct ath_hw *ah = sc->sc_ah;
1062         struct ath_common *common = ath9k_hw_common(ah);
1063         struct ieee80211_channel *curchan = hw->conf.channel;
1064         struct ath9k_channel *init_channel;
1065         int r;
1066
1067         ath_print(common, ATH_DBG_CONFIG,
1068                   "Starting driver with initial channel: %d MHz\n",
1069                   curchan->center_freq);
1070
1071         mutex_lock(&sc->mutex);
1072
1073         if (ath9k_wiphy_started(sc)) {
1074                 if (sc->chan_idx == curchan->hw_value) {
1075                         /*
1076                          * Already on the operational channel, the new wiphy
1077                          * can be marked active.
1078                          */
1079                         aphy->state = ATH_WIPHY_ACTIVE;
1080                         ieee80211_wake_queues(hw);
1081                 } else {
1082                         /*
1083                          * Another wiphy is on another channel, start the new
1084                          * wiphy in paused state.
1085                          */
1086                         aphy->state = ATH_WIPHY_PAUSED;
1087                         ieee80211_stop_queues(hw);
1088                 }
1089                 mutex_unlock(&sc->mutex);
1090                 return 0;
1091         }
1092         aphy->state = ATH_WIPHY_ACTIVE;
1093
1094         /* setup initial channel */
1095
1096         sc->chan_idx = curchan->hw_value;
1097
1098         init_channel = ath_get_curchannel(sc, hw);
1099
1100         /* Reset SERDES registers */
1101         ath9k_hw_configpcipowersave(ah, 0, 0);
1102
1103         /*
1104          * The basic interface to setting the hardware in a good
1105          * state is ``reset''.  On return the hardware is known to
1106          * be powered up and with interrupts disabled.  This must
1107          * be followed by initialization of the appropriate bits
1108          * and then setup of the interrupt mask.
1109          */
1110         spin_lock_bh(&sc->sc_resetlock);
1111         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1112         if (r) {
1113                 ath_print(common, ATH_DBG_FATAL,
1114                           "Unable to reset hardware; reset status %d "
1115                           "(freq %u MHz)\n", r,
1116                           curchan->center_freq);
1117                 spin_unlock_bh(&sc->sc_resetlock);
1118                 goto mutex_unlock;
1119         }
1120         spin_unlock_bh(&sc->sc_resetlock);
1121
1122         /*
1123          * This is needed only to setup initial state
1124          * but it's best done after a reset.
1125          */
1126         ath_update_txpow(sc);
1127
1128         /*
1129          * Setup the hardware after reset:
1130          * The receive engine is set going.
1131          * Frame transmit is handled entirely
1132          * in the frame output path; there's nothing to do
1133          * here except setup the interrupt mask.
1134          */
1135         if (ath_startrecv(sc) != 0) {
1136                 ath_print(common, ATH_DBG_FATAL,
1137                           "Unable to start recv logic\n");
1138                 r = -EIO;
1139                 goto mutex_unlock;
1140         }
1141
1142         /* Setup our intr mask. */
1143         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1144                     ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1145                     ATH9K_INT_GLOBAL;
1146
1147         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1148                 ah->imask |= ATH9K_INT_RXHP |
1149                              ATH9K_INT_RXLP |
1150                              ATH9K_INT_BB_WATCHDOG;
1151         else
1152                 ah->imask |= ATH9K_INT_RX;
1153
1154         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1155                 ah->imask |= ATH9K_INT_GTT;
1156
1157         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1158                 ah->imask |= ATH9K_INT_CST;
1159
1160         ath_cache_conf_rate(sc, &hw->conf);
1161
1162         sc->sc_flags &= ~SC_OP_INVALID;
1163
1164         /* Disable BMISS interrupt when we're not associated */
1165         ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1166         ath9k_hw_set_interrupts(ah, ah->imask);
1167
1168         ieee80211_wake_queues(hw);
1169
1170         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1171
1172         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1173             !ah->btcoex_hw.enabled) {
1174                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1175                                            AR_STOMP_LOW_WLAN_WGHT);
1176                 ath9k_hw_btcoex_enable(ah);
1177
1178                 if (common->bus_ops->bt_coex_prep)
1179                         common->bus_ops->bt_coex_prep(common);
1180                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1181                         ath9k_btcoex_timer_resume(sc);
1182         }
1183
1184 mutex_unlock:
1185         mutex_unlock(&sc->mutex);
1186
1187         return r;
1188 }
1189
1190 static int ath9k_tx(struct ieee80211_hw *hw,
1191                     struct sk_buff *skb)
1192 {
1193         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1194         struct ath_wiphy *aphy = hw->priv;
1195         struct ath_softc *sc = aphy->sc;
1196         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1197         struct ath_tx_control txctl;
1198         int padpos, padsize;
1199         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1200         int qnum;
1201
1202         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1203                 ath_print(common, ATH_DBG_XMIT,
1204                           "ath9k: %s: TX in unexpected wiphy state "
1205                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
1206                 goto exit;
1207         }
1208
1209         if (sc->ps_enabled) {
1210                 /*
1211                  * mac80211 does not set PM field for normal data frames, so we
1212                  * need to update that based on the current PS mode.
1213                  */
1214                 if (ieee80211_is_data(hdr->frame_control) &&
1215                     !ieee80211_is_nullfunc(hdr->frame_control) &&
1216                     !ieee80211_has_pm(hdr->frame_control)) {
1217                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1218                                   "while in PS mode\n");
1219                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1220                 }
1221         }
1222
1223         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1224                 /*
1225                  * We are using PS-Poll and mac80211 can request TX while in
1226                  * power save mode. Need to wake up hardware for the TX to be
1227                  * completed and if needed, also for RX of buffered frames.
1228                  */
1229                 ath9k_ps_wakeup(sc);
1230                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1231                         ath9k_hw_setrxabort(sc->sc_ah, 0);
1232                 if (ieee80211_is_pspoll(hdr->frame_control)) {
1233                         ath_print(common, ATH_DBG_PS,
1234                                   "Sending PS-Poll to pick a buffered frame\n");
1235                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1236                 } else {
1237                         ath_print(common, ATH_DBG_PS,
1238                                   "Wake up to complete TX\n");
1239                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1240                 }
1241                 /*
1242                  * The actual restore operation will happen only after
1243                  * the sc_flags bit is cleared. We are just dropping
1244                  * the ps_usecount here.
1245                  */
1246                 ath9k_ps_restore(sc);
1247         }
1248
1249         memset(&txctl, 0, sizeof(struct ath_tx_control));
1250
1251         /*
1252          * As a temporary workaround, assign seq# here; this will likely need
1253          * to be cleaned up to work better with Beacon transmission and virtual
1254          * BSSes.
1255          */
1256         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1257                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1258                         sc->tx.seq_no += 0x10;
1259                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1260                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1261         }
1262
1263         /* Add the padding after the header if this is not already done */
1264         padpos = ath9k_cmn_padpos(hdr->frame_control);
1265         padsize = padpos & 3;
1266         if (padsize && skb->len>padpos) {
1267                 if (skb_headroom(skb) < padsize)
1268                         return -1;
1269                 skb_push(skb, padsize);
1270                 memmove(skb->data, skb->data + padsize, padpos);
1271         }
1272
1273         qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1274         txctl.txq = &sc->tx.txq[qnum];
1275
1276         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1277
1278         if (ath_tx_start(hw, skb, &txctl) != 0) {
1279                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
1280                 goto exit;
1281         }
1282
1283         return 0;
1284 exit:
1285         dev_kfree_skb_any(skb);
1286         return 0;
1287 }
1288
1289 static void ath9k_stop(struct ieee80211_hw *hw)
1290 {
1291         struct ath_wiphy *aphy = hw->priv;
1292         struct ath_softc *sc = aphy->sc;
1293         struct ath_hw *ah = sc->sc_ah;
1294         struct ath_common *common = ath9k_hw_common(ah);
1295         int i;
1296
1297         mutex_lock(&sc->mutex);
1298
1299         aphy->state = ATH_WIPHY_INACTIVE;
1300
1301         if (led_blink)
1302                 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1303
1304         cancel_delayed_work_sync(&sc->tx_complete_work);
1305         cancel_work_sync(&sc->paprd_work);
1306         cancel_work_sync(&sc->hw_check_work);
1307
1308         for (i = 0; i < sc->num_sec_wiphy; i++) {
1309                 if (sc->sec_wiphy[i])
1310                         break;
1311         }
1312
1313         if (i == sc->num_sec_wiphy) {
1314                 cancel_delayed_work_sync(&sc->wiphy_work);
1315                 cancel_work_sync(&sc->chan_work);
1316         }
1317
1318         if (sc->sc_flags & SC_OP_INVALID) {
1319                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
1320                 mutex_unlock(&sc->mutex);
1321                 return;
1322         }
1323
1324         if (ath9k_wiphy_started(sc)) {
1325                 mutex_unlock(&sc->mutex);
1326                 return; /* another wiphy still in use */
1327         }
1328
1329         /* Ensure HW is awake when we try to shut it down. */
1330         ath9k_ps_wakeup(sc);
1331
1332         if (ah->btcoex_hw.enabled) {
1333                 ath9k_hw_btcoex_disable(ah);
1334                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1335                         ath9k_btcoex_timer_pause(sc);
1336         }
1337
1338         /* make sure h/w will not generate any interrupt
1339          * before setting the invalid flag. */
1340         ath9k_hw_set_interrupts(ah, 0);
1341
1342         if (!(sc->sc_flags & SC_OP_INVALID)) {
1343                 ath_drain_all_txq(sc, false);
1344                 ath_stoprecv(sc);
1345                 ath9k_hw_phy_disable(ah);
1346         } else
1347                 sc->rx.rxlink = NULL;
1348
1349         /* disable HAL and put h/w to sleep */
1350         ath9k_hw_disable(ah);
1351         ath9k_hw_configpcipowersave(ah, 1, 1);
1352         ath9k_ps_restore(sc);
1353
1354         /* Finally, put the chip in FULL SLEEP mode */
1355         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1356
1357         sc->sc_flags |= SC_OP_INVALID;
1358
1359         mutex_unlock(&sc->mutex);
1360
1361         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
1362 }
1363
1364 static int ath9k_add_interface(struct ieee80211_hw *hw,
1365                                struct ieee80211_vif *vif)
1366 {
1367         struct ath_wiphy *aphy = hw->priv;
1368         struct ath_softc *sc = aphy->sc;
1369         struct ath_hw *ah = sc->sc_ah;
1370         struct ath_common *common = ath9k_hw_common(ah);
1371         struct ath_vif *avp = (void *)vif->drv_priv;
1372         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
1373         int ret = 0;
1374
1375         mutex_lock(&sc->mutex);
1376
1377         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
1378             sc->nvifs > 0) {
1379                 ret = -ENOBUFS;
1380                 goto out;
1381         }
1382
1383         switch (vif->type) {
1384         case NL80211_IFTYPE_STATION:
1385                 ic_opmode = NL80211_IFTYPE_STATION;
1386                 break;
1387         case NL80211_IFTYPE_ADHOC:
1388         case NL80211_IFTYPE_AP:
1389         case NL80211_IFTYPE_MESH_POINT:
1390                 if (sc->nbcnvifs >= ATH_BCBUF) {
1391                         ret = -ENOBUFS;
1392                         goto out;
1393                 }
1394                 ic_opmode = vif->type;
1395                 break;
1396         default:
1397                 ath_print(common, ATH_DBG_FATAL,
1398                         "Interface type %d not yet supported\n", vif->type);
1399                 ret = -EOPNOTSUPP;
1400                 goto out;
1401         }
1402
1403         ath_print(common, ATH_DBG_CONFIG,
1404                   "Attach a VIF of type: %d\n", ic_opmode);
1405
1406         /* Set the VIF opmode */
1407         avp->av_opmode = ic_opmode;
1408         avp->av_bslot = -1;
1409
1410         sc->nvifs++;
1411
1412         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1413                 ath9k_set_bssid_mask(hw);
1414
1415         if (sc->nvifs > 1)
1416                 goto out; /* skip global settings for secondary vif */
1417
1418         if (ic_opmode == NL80211_IFTYPE_AP) {
1419                 ath9k_hw_set_tsfadjust(ah, 1);
1420                 sc->sc_flags |= SC_OP_TSF_RESET;
1421         }
1422
1423         /* Set the device opmode */
1424         ah->opmode = ic_opmode;
1425
1426         /*
1427          * Enable MIB interrupts when there are hardware phy counters.
1428          * Note we only do this (at the moment) for station mode.
1429          */
1430         if ((vif->type == NL80211_IFTYPE_STATION) ||
1431             (vif->type == NL80211_IFTYPE_ADHOC) ||
1432             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1433                 if (ah->config.enable_ani)
1434                         ah->imask |= ATH9K_INT_MIB;
1435                 ah->imask |= ATH9K_INT_TSFOOR;
1436         }
1437
1438         ath9k_hw_set_interrupts(ah, ah->imask);
1439
1440         if (vif->type == NL80211_IFTYPE_AP    ||
1441             vif->type == NL80211_IFTYPE_ADHOC ||
1442             vif->type == NL80211_IFTYPE_MONITOR) {
1443                 sc->sc_flags |= SC_OP_ANI_RUN;
1444                 ath_start_ani(common);
1445         }
1446
1447 out:
1448         mutex_unlock(&sc->mutex);
1449         return ret;
1450 }
1451
1452 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1453                                    struct ieee80211_vif *vif)
1454 {
1455         struct ath_wiphy *aphy = hw->priv;
1456         struct ath_softc *sc = aphy->sc;
1457         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1458         struct ath_vif *avp = (void *)vif->drv_priv;
1459         int i;
1460
1461         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
1462
1463         mutex_lock(&sc->mutex);
1464
1465         /* Stop ANI */
1466         sc->sc_flags &= ~SC_OP_ANI_RUN;
1467         del_timer_sync(&common->ani.timer);
1468
1469         /* Reclaim beacon resources */
1470         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1471             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1472             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
1473                 ath9k_ps_wakeup(sc);
1474                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1475                 ath9k_ps_restore(sc);
1476         }
1477
1478         ath_beacon_return(sc, avp);
1479         sc->sc_flags &= ~SC_OP_BEACONS;
1480
1481         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1482                 if (sc->beacon.bslot[i] == vif) {
1483                         printk(KERN_DEBUG "%s: vif had allocated beacon "
1484                                "slot\n", __func__);
1485                         sc->beacon.bslot[i] = NULL;
1486                         sc->beacon.bslot_aphy[i] = NULL;
1487                 }
1488         }
1489
1490         sc->nvifs--;
1491
1492         mutex_unlock(&sc->mutex);
1493 }
1494
1495 void ath9k_enable_ps(struct ath_softc *sc)
1496 {
1497         struct ath_hw *ah = sc->sc_ah;
1498
1499         sc->ps_enabled = true;
1500         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1501                 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1502                         ah->imask |= ATH9K_INT_TIM_TIMER;
1503                         ath9k_hw_set_interrupts(ah, ah->imask);
1504                 }
1505                 ath9k_hw_setrxabort(ah, 1);
1506         }
1507 }
1508
1509 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1510 {
1511         struct ath_wiphy *aphy = hw->priv;
1512         struct ath_softc *sc = aphy->sc;
1513         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1514         struct ieee80211_conf *conf = &hw->conf;
1515         struct ath_hw *ah = sc->sc_ah;
1516         bool disable_radio;
1517
1518         mutex_lock(&sc->mutex);
1519
1520         /*
1521          * Leave this as the first check because we need to turn on the
1522          * radio if it was disabled before prior to processing the rest
1523          * of the changes. Likewise we must only disable the radio towards
1524          * the end.
1525          */
1526         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1527                 bool enable_radio;
1528                 bool all_wiphys_idle;
1529                 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1530
1531                 spin_lock_bh(&sc->wiphy_lock);
1532                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
1533                 ath9k_set_wiphy_idle(aphy, idle);
1534
1535                 enable_radio = (!idle && all_wiphys_idle);
1536
1537                 /*
1538                  * After we unlock here its possible another wiphy
1539                  * can be re-renabled so to account for that we will
1540                  * only disable the radio toward the end of this routine
1541                  * if by then all wiphys are still idle.
1542                  */
1543                 spin_unlock_bh(&sc->wiphy_lock);
1544
1545                 if (enable_radio) {
1546                         sc->ps_idle = false;
1547                         ath_radio_enable(sc, hw);
1548                         ath_print(common, ATH_DBG_CONFIG,
1549                                   "not-idle: enabling radio\n");
1550                 }
1551         }
1552
1553         /*
1554          * We just prepare to enable PS. We have to wait until our AP has
1555          * ACK'd our null data frame to disable RX otherwise we'll ignore
1556          * those ACKs and end up retransmitting the same null data frames.
1557          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1558          */
1559         if (changed & IEEE80211_CONF_CHANGE_PS) {
1560                 if (conf->flags & IEEE80211_CONF_PS) {
1561                         sc->ps_flags |= PS_ENABLED;
1562                         /*
1563                          * At this point we know hardware has received an ACK
1564                          * of a previously sent null data frame.
1565                          */
1566                         if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
1567                                 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1568                                 ath9k_enable_ps(sc);
1569                         }
1570                 } else {
1571                         sc->ps_enabled = false;
1572                         sc->ps_flags &= ~(PS_ENABLED |
1573                                           PS_NULLFUNC_COMPLETED);
1574                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
1575                         if (!(ah->caps.hw_caps &
1576                               ATH9K_HW_CAP_AUTOSLEEP)) {
1577                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
1578                                 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1579                                                   PS_WAIT_FOR_CAB |
1580                                                   PS_WAIT_FOR_PSPOLL_DATA |
1581                                                   PS_WAIT_FOR_TX_ACK);
1582                                 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1583                                         ah->imask &= ~ATH9K_INT_TIM_TIMER;
1584                                         ath9k_hw_set_interrupts(sc->sc_ah,
1585                                                         ah->imask);
1586                                 }
1587                         }
1588                 }
1589         }
1590
1591         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1592                 if (conf->flags & IEEE80211_CONF_MONITOR) {
1593                         ath_print(common, ATH_DBG_CONFIG,
1594                                   "HW opmode set to Monitor mode\n");
1595                         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1596                 }
1597         }
1598
1599         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
1600                 struct ieee80211_channel *curchan = hw->conf.channel;
1601                 int pos = curchan->hw_value;
1602
1603                 aphy->chan_idx = pos;
1604                 aphy->chan_is_ht = conf_is_ht(conf);
1605                 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1606                         sc->sc_flags |= SC_OP_OFFCHANNEL;
1607                 else
1608                         sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1609
1610                 if (aphy->state == ATH_WIPHY_SCAN ||
1611                     aphy->state == ATH_WIPHY_ACTIVE)
1612                         ath9k_wiphy_pause_all_forced(sc, aphy);
1613                 else {
1614                         /*
1615                          * Do not change operational channel based on a paused
1616                          * wiphy changes.
1617                          */
1618                         goto skip_chan_change;
1619                 }
1620
1621                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1622                           curchan->center_freq);
1623
1624                 /* XXX: remove me eventualy */
1625                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
1626
1627                 ath_update_chainmask(sc, conf_is_ht(conf));
1628
1629                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1630                         ath_print(common, ATH_DBG_FATAL,
1631                                   "Unable to set channel\n");
1632                         mutex_unlock(&sc->mutex);
1633                         return -EINVAL;
1634                 }
1635         }
1636
1637 skip_chan_change:
1638         if (changed & IEEE80211_CONF_CHANGE_POWER) {
1639                 sc->config.txpowlimit = 2 * conf->power_level;
1640                 ath_update_txpow(sc);
1641         }
1642
1643         spin_lock_bh(&sc->wiphy_lock);
1644         disable_radio = ath9k_all_wiphys_idle(sc);
1645         spin_unlock_bh(&sc->wiphy_lock);
1646
1647         if (disable_radio) {
1648                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1649                 sc->ps_idle = true;
1650                 ath_radio_disable(sc, hw);
1651         }
1652
1653         mutex_unlock(&sc->mutex);
1654
1655         return 0;
1656 }
1657
1658 #define SUPPORTED_FILTERS                       \
1659         (FIF_PROMISC_IN_BSS |                   \
1660         FIF_ALLMULTI |                          \
1661         FIF_CONTROL |                           \
1662         FIF_PSPOLL |                            \
1663         FIF_OTHER_BSS |                         \
1664         FIF_BCN_PRBRESP_PROMISC |               \
1665         FIF_FCSFAIL)
1666
1667 /* FIXME: sc->sc_full_reset ? */
1668 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1669                                    unsigned int changed_flags,
1670                                    unsigned int *total_flags,
1671                                    u64 multicast)
1672 {
1673         struct ath_wiphy *aphy = hw->priv;
1674         struct ath_softc *sc = aphy->sc;
1675         u32 rfilt;
1676
1677         changed_flags &= SUPPORTED_FILTERS;
1678         *total_flags &= SUPPORTED_FILTERS;
1679
1680         sc->rx.rxfilter = *total_flags;
1681         ath9k_ps_wakeup(sc);
1682         rfilt = ath_calcrxfilter(sc);
1683         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1684         ath9k_ps_restore(sc);
1685
1686         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1687                   "Set HW RX filter: 0x%x\n", rfilt);
1688 }
1689
1690 static int ath9k_sta_add(struct ieee80211_hw *hw,
1691                          struct ieee80211_vif *vif,
1692                          struct ieee80211_sta *sta)
1693 {
1694         struct ath_wiphy *aphy = hw->priv;
1695         struct ath_softc *sc = aphy->sc;
1696
1697         ath_node_attach(sc, sta);
1698
1699         return 0;
1700 }
1701
1702 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1703                             struct ieee80211_vif *vif,
1704                             struct ieee80211_sta *sta)
1705 {
1706         struct ath_wiphy *aphy = hw->priv;
1707         struct ath_softc *sc = aphy->sc;
1708
1709         ath_node_detach(sc, sta);
1710
1711         return 0;
1712 }
1713
1714 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
1715                          const struct ieee80211_tx_queue_params *params)
1716 {
1717         struct ath_wiphy *aphy = hw->priv;
1718         struct ath_softc *sc = aphy->sc;
1719         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1720         struct ath9k_tx_queue_info qi;
1721         int ret = 0, qnum;
1722
1723         if (queue >= WME_NUM_AC)
1724                 return 0;
1725
1726         mutex_lock(&sc->mutex);
1727
1728         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1729
1730         qi.tqi_aifs = params->aifs;
1731         qi.tqi_cwmin = params->cw_min;
1732         qi.tqi_cwmax = params->cw_max;
1733         qi.tqi_burstTime = params->txop;
1734         qnum = ath_get_hal_qnum(queue, sc);
1735
1736         ath_print(common, ATH_DBG_CONFIG,
1737                   "Configure tx [queue/halq] [%d/%d],  "
1738                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1739                   queue, qnum, params->aifs, params->cw_min,
1740                   params->cw_max, params->txop);
1741
1742         ret = ath_txq_update(sc, qnum, &qi);
1743         if (ret)
1744                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
1745
1746         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1747                 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
1748                         ath_beaconq_config(sc);
1749
1750         mutex_unlock(&sc->mutex);
1751
1752         return ret;
1753 }
1754
1755 static int ath9k_set_key(struct ieee80211_hw *hw,
1756                          enum set_key_cmd cmd,
1757                          struct ieee80211_vif *vif,
1758                          struct ieee80211_sta *sta,
1759                          struct ieee80211_key_conf *key)
1760 {
1761         struct ath_wiphy *aphy = hw->priv;
1762         struct ath_softc *sc = aphy->sc;
1763         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1764         int ret = 0;
1765
1766         if (modparam_nohwcrypt)
1767                 return -ENOSPC;
1768
1769         mutex_lock(&sc->mutex);
1770         ath9k_ps_wakeup(sc);
1771         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
1772
1773         switch (cmd) {
1774         case SET_KEY:
1775                 ret = ath9k_cmn_key_config(common, vif, sta, key);
1776                 if (ret >= 0) {
1777                         key->hw_key_idx = ret;
1778                         /* push IV and Michael MIC generation to stack */
1779                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1780                         if (key->alg == ALG_TKIP)
1781                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1782                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
1783                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1784                         ret = 0;
1785                 }
1786                 break;
1787         case DISABLE_KEY:
1788                 ath9k_cmn_key_delete(common, key);
1789                 break;
1790         default:
1791                 ret = -EINVAL;
1792         }
1793
1794         ath9k_ps_restore(sc);
1795         mutex_unlock(&sc->mutex);
1796
1797         return ret;
1798 }
1799
1800 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1801                                    struct ieee80211_vif *vif,
1802                                    struct ieee80211_bss_conf *bss_conf,
1803                                    u32 changed)
1804 {
1805         struct ath_wiphy *aphy = hw->priv;
1806         struct ath_softc *sc = aphy->sc;
1807         struct ath_hw *ah = sc->sc_ah;
1808         struct ath_common *common = ath9k_hw_common(ah);
1809         struct ath_vif *avp = (void *)vif->drv_priv;
1810         int slottime;
1811         int error;
1812
1813         mutex_lock(&sc->mutex);
1814
1815         if (changed & BSS_CHANGED_BSSID) {
1816                 /* Set BSSID */
1817                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1818                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1819                 common->curaid = 0;
1820                 ath9k_hw_write_associd(ah);
1821
1822                 /* Set aggregation protection mode parameters */
1823                 sc->config.ath_aggr_prot = 0;
1824
1825                 /* Only legacy IBSS for now */
1826                 if (vif->type == NL80211_IFTYPE_ADHOC)
1827                         ath_update_chainmask(sc, 0);
1828
1829                 ath_print(common, ATH_DBG_CONFIG,
1830                           "BSSID: %pM aid: 0x%x\n",
1831                           common->curbssid, common->curaid);
1832
1833                 /* need to reconfigure the beacon */
1834                 sc->sc_flags &= ~SC_OP_BEACONS ;
1835         }
1836
1837         /* Enable transmission of beacons (AP, IBSS, MESH) */
1838         if ((changed & BSS_CHANGED_BEACON) ||
1839             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1840                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1841                 error = ath_beacon_alloc(aphy, vif);
1842                 if (!error)
1843                         ath_beacon_config(sc, vif);
1844         }
1845
1846         if (changed & BSS_CHANGED_ERP_SLOT) {
1847                 if (bss_conf->use_short_slot)
1848                         slottime = 9;
1849                 else
1850                         slottime = 20;
1851                 if (vif->type == NL80211_IFTYPE_AP) {
1852                         /*
1853                          * Defer update, so that connected stations can adjust
1854                          * their settings at the same time.
1855                          * See beacon.c for more details
1856                          */
1857                         sc->beacon.slottime = slottime;
1858                         sc->beacon.updateslot = UPDATE;
1859                 } else {
1860                         ah->slottime = slottime;
1861                         ath9k_hw_init_global_settings(ah);
1862                 }
1863         }
1864
1865         /* Disable transmission of beacons */
1866         if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1867                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1868
1869         if (changed & BSS_CHANGED_BEACON_INT) {
1870                 sc->beacon_interval = bss_conf->beacon_int;
1871                 /*
1872                  * In case of AP mode, the HW TSF has to be reset
1873                  * when the beacon interval changes.
1874                  */
1875                 if (vif->type == NL80211_IFTYPE_AP) {
1876                         sc->sc_flags |= SC_OP_TSF_RESET;
1877                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1878                         error = ath_beacon_alloc(aphy, vif);
1879                         if (!error)
1880                                 ath_beacon_config(sc, vif);
1881                 } else {
1882                         ath_beacon_config(sc, vif);
1883                 }
1884         }
1885
1886         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1887                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1888                           bss_conf->use_short_preamble);
1889                 if (bss_conf->use_short_preamble)
1890                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1891                 else
1892                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1893         }
1894
1895         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1896                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1897                           bss_conf->use_cts_prot);
1898                 if (bss_conf->use_cts_prot &&
1899                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1900                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1901                 else
1902                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1903         }
1904
1905         if (changed & BSS_CHANGED_ASSOC) {
1906                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
1907                         bss_conf->assoc);
1908                 ath9k_bss_assoc_info(sc, vif, bss_conf);
1909         }
1910
1911         mutex_unlock(&sc->mutex);
1912 }
1913
1914 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1915 {
1916         u64 tsf;
1917         struct ath_wiphy *aphy = hw->priv;
1918         struct ath_softc *sc = aphy->sc;
1919
1920         mutex_lock(&sc->mutex);
1921         tsf = ath9k_hw_gettsf64(sc->sc_ah);
1922         mutex_unlock(&sc->mutex);
1923
1924         return tsf;
1925 }
1926
1927 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1928 {
1929         struct ath_wiphy *aphy = hw->priv;
1930         struct ath_softc *sc = aphy->sc;
1931
1932         mutex_lock(&sc->mutex);
1933         ath9k_hw_settsf64(sc->sc_ah, tsf);
1934         mutex_unlock(&sc->mutex);
1935 }
1936
1937 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1938 {
1939         struct ath_wiphy *aphy = hw->priv;
1940         struct ath_softc *sc = aphy->sc;
1941
1942         mutex_lock(&sc->mutex);
1943
1944         ath9k_ps_wakeup(sc);
1945         ath9k_hw_reset_tsf(sc->sc_ah);
1946         ath9k_ps_restore(sc);
1947
1948         mutex_unlock(&sc->mutex);
1949 }
1950
1951 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1952                               struct ieee80211_vif *vif,
1953                               enum ieee80211_ampdu_mlme_action action,
1954                               struct ieee80211_sta *sta,
1955                               u16 tid, u16 *ssn)
1956 {
1957         struct ath_wiphy *aphy = hw->priv;
1958         struct ath_softc *sc = aphy->sc;
1959         int ret = 0;
1960
1961         local_bh_disable();
1962
1963         switch (action) {
1964         case IEEE80211_AMPDU_RX_START:
1965                 if (!(sc->sc_flags & SC_OP_RXAGGR))
1966                         ret = -ENOTSUPP;
1967                 break;
1968         case IEEE80211_AMPDU_RX_STOP:
1969                 break;
1970         case IEEE80211_AMPDU_TX_START:
1971                 ath9k_ps_wakeup(sc);
1972                 ath_tx_aggr_start(sc, sta, tid, ssn);
1973                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1974                 ath9k_ps_restore(sc);
1975                 break;
1976         case IEEE80211_AMPDU_TX_STOP:
1977                 ath9k_ps_wakeup(sc);
1978                 ath_tx_aggr_stop(sc, sta, tid);
1979                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1980                 ath9k_ps_restore(sc);
1981                 break;
1982         case IEEE80211_AMPDU_TX_OPERATIONAL:
1983                 ath9k_ps_wakeup(sc);
1984                 ath_tx_aggr_resume(sc, sta, tid);
1985                 ath9k_ps_restore(sc);
1986                 break;
1987         default:
1988                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1989                           "Unknown AMPDU action\n");
1990         }
1991
1992         local_bh_enable();
1993
1994         return ret;
1995 }
1996
1997 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1998                              struct survey_info *survey)
1999 {
2000         struct ath_wiphy *aphy = hw->priv;
2001         struct ath_softc *sc = aphy->sc;
2002         struct ath_hw *ah = sc->sc_ah;
2003         struct ath_common *common = ath9k_hw_common(ah);
2004         struct ieee80211_conf *conf = &hw->conf;
2005
2006          if (idx != 0)
2007                 return -ENOENT;
2008
2009         survey->channel = conf->channel;
2010         survey->filled = SURVEY_INFO_NOISE_DBM;
2011         survey->noise = common->ani.noise_floor;
2012
2013         return 0;
2014 }
2015
2016 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2017 {
2018         struct ath_wiphy *aphy = hw->priv;
2019         struct ath_softc *sc = aphy->sc;
2020
2021         mutex_lock(&sc->mutex);
2022         if (ath9k_wiphy_scanning(sc)) {
2023                 /*
2024                  * There is a race here in mac80211 but fixing it requires
2025                  * we revisit how we handle the scan complete callback.
2026                  * After mac80211 fixes we will not have configured hardware
2027                  * to the home channel nor would we have configured the RX
2028                  * filter yet.
2029                  */
2030                 mutex_unlock(&sc->mutex);
2031                 return;
2032         }
2033
2034         aphy->state = ATH_WIPHY_SCAN;
2035         ath9k_wiphy_pause_all_forced(sc, aphy);
2036         sc->sc_flags |= SC_OP_SCANNING;
2037         mutex_unlock(&sc->mutex);
2038 }
2039
2040 /*
2041  * XXX: this requires a revisit after the driver
2042  * scan_complete gets moved to another place/removed in mac80211.
2043  */
2044 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2045 {
2046         struct ath_wiphy *aphy = hw->priv;
2047         struct ath_softc *sc = aphy->sc;
2048
2049         mutex_lock(&sc->mutex);
2050         aphy->state = ATH_WIPHY_ACTIVE;
2051         sc->sc_flags &= ~SC_OP_SCANNING;
2052         mutex_unlock(&sc->mutex);
2053 }
2054
2055 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2056 {
2057         struct ath_wiphy *aphy = hw->priv;
2058         struct ath_softc *sc = aphy->sc;
2059         struct ath_hw *ah = sc->sc_ah;
2060
2061         mutex_lock(&sc->mutex);
2062         ah->coverage_class = coverage_class;
2063         ath9k_hw_init_global_settings(ah);
2064         mutex_unlock(&sc->mutex);
2065 }
2066
2067 struct ieee80211_ops ath9k_ops = {
2068         .tx                 = ath9k_tx,
2069         .start              = ath9k_start,
2070         .stop               = ath9k_stop,
2071         .add_interface      = ath9k_add_interface,
2072         .remove_interface   = ath9k_remove_interface,
2073         .config             = ath9k_config,
2074         .configure_filter   = ath9k_configure_filter,
2075         .sta_add            = ath9k_sta_add,
2076         .sta_remove         = ath9k_sta_remove,
2077         .conf_tx            = ath9k_conf_tx,
2078         .bss_info_changed   = ath9k_bss_info_changed,
2079         .set_key            = ath9k_set_key,
2080         .get_tsf            = ath9k_get_tsf,
2081         .set_tsf            = ath9k_set_tsf,
2082         .reset_tsf          = ath9k_reset_tsf,
2083         .ampdu_action       = ath9k_ampdu_action,
2084         .get_survey         = ath9k_get_survey,
2085         .sw_scan_start      = ath9k_sw_scan_start,
2086         .sw_scan_complete   = ath9k_sw_scan_complete,
2087         .rfkill_poll        = ath9k_rfkill_poll_state,
2088         .set_coverage_class = ath9k_set_coverage_class,
2089 };