2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
21 static char *dev_info = "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33 module_param_named(debug, ath9k_debug, uint, 0);
34 MODULE_PARM_DESC(debug, "Debugging mask");
36 /* We use the hw_value as an index into our private channel structure */
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
107 static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
123 sc->hw_rate_table[ATH9K_MODE_11G];
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
137 sc->hw_rate_table[ATH9K_MODE_11A];
145 static void ath_update_txpow(struct ath_softc *sc)
147 struct ath_hw *ah = sc->sc_ah;
150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
154 sc->curtxpow = txpow;
158 static u8 parse_mpdudensity(u8 mpdudensity)
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
171 switch (mpdudensity) {
177 /* Our lower layer calculations limit our precision to
193 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
195 const struct ath_rate_table *rate_table = NULL;
196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
211 if (rate_table == NULL)
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
220 maxrates = rate_table->rate_cnt;
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
238 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
251 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
263 void ath9k_ps_wakeup(struct ath_softc *sc)
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
277 void ath9k_ps_restore(struct ath_softc *sc)
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
301 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
304 struct ath_hw *ah = sc->sc_ah;
305 struct ath_common *common = ath9k_hw_common(ah);
306 struct ieee80211_conf *conf = &common->hw->conf;
307 bool fastcc = true, stopped;
308 struct ieee80211_channel *channel = hw->conf.channel;
311 if (sc->sc_flags & SC_OP_INVALID)
317 * This is only performed if the channel settings have
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
325 ath9k_hw_set_interrupts(ah, 0);
326 ath_drain_all_txq(sc, false);
327 stopped = ath_stoprecv(sc);
329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
336 ath_print(common, ATH_DBG_CONFIG,
337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
338 sc->sc_ah->curchan->channel,
339 channel->center_freq, conf_is_ht40(conf));
341 spin_lock_bh(&sc->sc_resetlock);
343 r = ath9k_hw_reset(ah, hchan, fastcc);
345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
348 channel->center_freq, r);
349 spin_unlock_bh(&sc->sc_resetlock);
352 spin_unlock_bh(&sc->sc_resetlock);
354 sc->sc_flags &= ~SC_OP_FULL_RESET;
356 if (ath_startrecv(sc) != 0) {
357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
365 ath9k_hw_set_interrupts(ah, sc->imask);
368 ath9k_ps_restore(sc);
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
379 static void ath_ani_calibrate(unsigned long data)
381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
388 u32 cal_interval, short_cal_interval;
390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
397 spin_lock(&sc->ani_lock);
398 if (sc->sc_flags & SC_OP_SCANNING)
401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
407 /* Long calibration runs independently of short calibration. */
408 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
411 common->ani.longcal_timer = timestamp;
414 /* Short calibration applies only while caldone is false */
415 if (!common->ani.caldone) {
416 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
420 common->ani.shortcal_timer = timestamp;
421 common->ani.resetcal_timer = timestamp;
424 if ((timestamp - common->ani.resetcal_timer) >=
425 ATH_RESTART_CALINTERVAL) {
426 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
427 if (common->ani.caldone)
428 common->ani.resetcal_timer = timestamp;
432 /* Verify whether we must check ANI */
433 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
435 common->ani.checkani_timer = timestamp;
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
442 ath9k_hw_ani_monitor(ah, ah->curchan);
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
446 common->ani.caldone =
447 ath9k_hw_calibrate(ah,
449 common->rx_chainmask,
453 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 common->ani.noise_floor);
464 ath9k_ps_restore(sc);
467 spin_unlock(&sc->ani_lock);
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
473 cal_interval = ATH_LONG_CALINTERVAL;
474 if (sc->sc_ah->config.enable_ani)
475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
476 if (!common->ani.caldone)
477 cal_interval = min(cal_interval, (u32)short_cal_interval);
479 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
482 static void ath_start_ani(struct ath_common *common)
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
486 common->ani.longcal_timer = timestamp;
487 common->ani.shortcal_timer = timestamp;
488 common->ani.checkani_timer = timestamp;
490 mod_timer(&common->ani.timer,
491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
500 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
502 struct ath_hw *ah = sc->sc_ah;
503 struct ath_common *common = ath9k_hw_common(ah);
505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
514 ath_print(common, ATH_DBG_CONFIG,
515 "tx chmask: %d, rx chmask: %d\n",
516 common->tx_chainmask,
517 common->rx_chainmask);
520 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
524 an = (struct ath_node *)sta->drv_priv;
526 if (sc->sc_flags & SC_OP_TXAGGR) {
527 ath_tx_node_init(sc, an);
528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
535 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
543 static void ath9k_tasklet(unsigned long data)
545 struct ath_softc *sc = (struct ath_softc *)data;
546 struct ath_hw *ah = sc->sc_ah;
547 struct ath_common *common = ath9k_hw_common(ah);
549 u32 status = sc->intrstatus;
553 if (status & ATH9K_INT_FATAL) {
554 ath_reset(sc, false);
555 ath9k_ps_restore(sc);
559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
565 if (status & ATH9K_INT_TX)
568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
570 * TSF sync does not look correct; remain awake to sync with
573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
582 /* re-enable hardware interrupt */
583 ath9k_hw_set_interrupts(ah, sc->imask);
584 ath9k_ps_restore(sc);
587 irqreturn_t ath_isr(int irq, void *dev)
589 #define SCHED_INTR ( \
600 struct ath_softc *sc = dev;
601 struct ath_hw *ah = sc->sc_ah;
602 enum ath9k_int status;
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
610 if (sc->sc_flags & SC_OP_INVALID)
614 /* shared irq, not for us */
616 if (!ath9k_hw_intrpend(ah))
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
635 /* Cache the status */
636 sc->intrstatus = status;
638 if (status & SCHED_INTR)
642 * If a FATAL or RXORN interrupt is received, we have to reset the
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
654 if (status & ATH9K_INT_MIB) {
656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
660 ath9k_hw_set_interrupts(ah, 0);
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
666 ath9k_hw_procmibevent(ah);
667 ath9k_hw_set_interrupts(ah, sc->imask);
670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
672 /* Clear RxAbort bit so that we can
674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
675 ath9k_hw_setrxabort(sc->sc_ah, 0);
676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
681 ath_debug_stat_interrupt(sc, status);
684 /* turn off every interrupt except SWBA */
685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
686 tasklet_schedule(&sc->intr_tq);
694 static u32 ath_get_extchanmode(struct ath_softc *sc,
695 struct ieee80211_channel *chan,
696 enum nl80211_channel_type channel_type)
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
705 chanmode = CHANNEL_G_HT20;
707 case NL80211_CHAN_HT40PLUS:
708 chanmode = CHANNEL_G_HT40PLUS;
710 case NL80211_CHAN_HT40MINUS:
711 chanmode = CHANNEL_G_HT40MINUS;
715 case IEEE80211_BAND_5GHZ:
716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
719 chanmode = CHANNEL_A_HT20;
721 case NL80211_CHAN_HT40PLUS:
722 chanmode = CHANNEL_A_HT40PLUS;
724 case NL80211_CHAN_HT40MINUS:
725 chanmode = CHANNEL_A_HT40MINUS;
736 static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
737 struct ath9k_keyval *hk, const u8 *addr,
740 struct ath_hw *ah = common->ah;
744 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
745 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
749 * Group key installation - only two key cache entries are used
750 * regardless of splitmic capability since group key is only
751 * used either for TX or RX.
754 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
755 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
757 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
758 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
760 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
762 if (!common->splitmic) {
763 /* TX and RX keys share the same key cache entry. */
764 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
765 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
766 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
769 /* Separate key cache entries for TX and RX */
771 /* TX key goes at first index, RX key at +32. */
772 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
773 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
774 /* TX MIC entry failed. No need to proceed further */
775 ath_print(common, ATH_DBG_FATAL,
776 "Setting TX MIC Key Failed\n");
780 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
781 /* XXX delete tx key on failure? */
782 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
785 static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
789 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
790 if (test_bit(i, common->keymap) ||
791 test_bit(i + 64, common->keymap))
792 continue; /* At least one part of TKIP key allocated */
793 if (common->splitmic &&
794 (test_bit(i + 32, common->keymap) ||
795 test_bit(i + 64 + 32, common->keymap)))
796 continue; /* At least one part of TKIP key allocated */
798 /* Found a free slot for a TKIP key */
804 static int ath_reserve_key_cache_slot(struct ath_common *common)
808 /* First, try to find slots that would not be available for TKIP. */
809 if (common->splitmic) {
810 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
811 if (!test_bit(i, common->keymap) &&
812 (test_bit(i + 32, common->keymap) ||
813 test_bit(i + 64, common->keymap) ||
814 test_bit(i + 64 + 32, common->keymap)))
816 if (!test_bit(i + 32, common->keymap) &&
817 (test_bit(i, common->keymap) ||
818 test_bit(i + 64, common->keymap) ||
819 test_bit(i + 64 + 32, common->keymap)))
821 if (!test_bit(i + 64, common->keymap) &&
822 (test_bit(i , common->keymap) ||
823 test_bit(i + 32, common->keymap) ||
824 test_bit(i + 64 + 32, common->keymap)))
826 if (!test_bit(i + 64 + 32, common->keymap) &&
827 (test_bit(i, common->keymap) ||
828 test_bit(i + 32, common->keymap) ||
829 test_bit(i + 64, common->keymap)))
833 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
834 if (!test_bit(i, common->keymap) &&
835 test_bit(i + 64, common->keymap))
837 if (test_bit(i, common->keymap) &&
838 !test_bit(i + 64, common->keymap))
843 /* No partially used TKIP slots, pick any available slot */
844 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
845 /* Do not allow slots that could be needed for TKIP group keys
846 * to be used. This limitation could be removed if we know that
847 * TKIP will not be used. */
848 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
850 if (common->splitmic) {
851 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
853 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
857 if (!test_bit(i, common->keymap))
858 return i; /* Found a free slot for a key */
861 /* No free slot found */
865 static int ath_key_config(struct ath_common *common,
866 struct ieee80211_vif *vif,
867 struct ieee80211_sta *sta,
868 struct ieee80211_key_conf *key)
870 struct ath_hw *ah = common->ah;
871 struct ath9k_keyval hk;
872 const u8 *mac = NULL;
876 memset(&hk, 0, sizeof(hk));
880 hk.kv_type = ATH9K_CIPHER_WEP;
883 hk.kv_type = ATH9K_CIPHER_TKIP;
886 hk.kv_type = ATH9K_CIPHER_AES_CCM;
892 hk.kv_len = key->keylen;
893 memcpy(hk.kv_val, key->key, key->keylen);
895 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
896 /* For now, use the default keys for broadcast keys. This may
897 * need to change with virtual interfaces. */
899 } else if (key->keyidx) {
904 if (vif->type != NL80211_IFTYPE_AP) {
905 /* Only keyidx 0 should be used with unicast key, but
906 * allow this for client mode for now. */
915 if (key->alg == ALG_TKIP)
916 idx = ath_reserve_key_cache_slot_tkip(common);
918 idx = ath_reserve_key_cache_slot(common);
920 return -ENOSPC; /* no free key cache entries */
923 if (key->alg == ALG_TKIP)
924 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
925 vif->type == NL80211_IFTYPE_AP);
927 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
932 set_bit(idx, common->keymap);
933 if (key->alg == ALG_TKIP) {
934 set_bit(idx + 64, common->keymap);
935 if (common->splitmic) {
936 set_bit(idx + 32, common->keymap);
937 set_bit(idx + 64 + 32, common->keymap);
944 static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
946 struct ath_hw *ah = common->ah;
948 ath9k_hw_keyreset(ah, key->hw_key_idx);
949 if (key->hw_key_idx < IEEE80211_WEP_NKID)
952 clear_bit(key->hw_key_idx, common->keymap);
953 if (key->alg != ALG_TKIP)
956 clear_bit(key->hw_key_idx + 64, common->keymap);
957 if (common->splitmic) {
958 clear_bit(key->hw_key_idx + 32, common->keymap);
959 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
963 static void setup_ht_cap(struct ath_softc *sc,
964 struct ieee80211_sta_ht_cap *ht_info)
966 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
967 u8 tx_streams, rx_streams;
969 ht_info->ht_supported = true;
970 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
971 IEEE80211_HT_CAP_SM_PS |
972 IEEE80211_HT_CAP_SGI_40 |
973 IEEE80211_HT_CAP_DSSSCCK40;
975 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
976 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
978 /* set up supported mcs set */
979 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
980 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
982 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
985 if (tx_streams != rx_streams) {
986 ath_print(common, ATH_DBG_CONFIG,
987 "TX streams %d, RX streams: %d\n",
988 tx_streams, rx_streams);
989 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
990 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
991 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
994 ht_info->mcs.rx_mask[0] = 0xff;
996 ht_info->mcs.rx_mask[1] = 0xff;
998 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
1001 static void ath9k_bss_assoc_info(struct ath_softc *sc,
1002 struct ieee80211_vif *vif,
1003 struct ieee80211_bss_conf *bss_conf)
1005 struct ath_hw *ah = sc->sc_ah;
1006 struct ath_common *common = ath9k_hw_common(ah);
1008 if (bss_conf->assoc) {
1009 ath_print(common, ATH_DBG_CONFIG,
1010 "Bss Info ASSOC %d, bssid: %pM\n",
1011 bss_conf->aid, common->curbssid);
1013 /* New association, store aid */
1014 common->curaid = bss_conf->aid;
1015 ath9k_hw_write_associd(ah);
1018 * Request a re-configuration of Beacon related timers
1019 * on the receipt of the first Beacon frame (i.e.,
1020 * after time sync with the AP).
1022 sc->sc_flags |= SC_OP_BEACON_SYNC;
1024 /* Configure the beacon */
1025 ath_beacon_config(sc, vif);
1027 /* Reset rssi stats */
1028 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1030 ath_start_ani(common);
1032 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1035 del_timer_sync(&common->ani.timer);
1039 /********************************/
1041 /********************************/
1043 static void ath_led_blink_work(struct work_struct *work)
1045 struct ath_softc *sc = container_of(work, struct ath_softc,
1046 ath_led_blink_work.work);
1048 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1051 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1052 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1053 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1055 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1056 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1058 ieee80211_queue_delayed_work(sc->hw,
1059 &sc->ath_led_blink_work,
1060 (sc->sc_flags & SC_OP_LED_ON) ?
1061 msecs_to_jiffies(sc->led_off_duration) :
1062 msecs_to_jiffies(sc->led_on_duration));
1064 sc->led_on_duration = sc->led_on_cnt ?
1065 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1066 ATH_LED_ON_DURATION_IDLE;
1067 sc->led_off_duration = sc->led_off_cnt ?
1068 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1069 ATH_LED_OFF_DURATION_IDLE;
1070 sc->led_on_cnt = sc->led_off_cnt = 0;
1071 if (sc->sc_flags & SC_OP_LED_ON)
1072 sc->sc_flags &= ~SC_OP_LED_ON;
1074 sc->sc_flags |= SC_OP_LED_ON;
1077 static void ath_led_brightness(struct led_classdev *led_cdev,
1078 enum led_brightness brightness)
1080 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1081 struct ath_softc *sc = led->sc;
1083 switch (brightness) {
1085 if (led->led_type == ATH_LED_ASSOC ||
1086 led->led_type == ATH_LED_RADIO) {
1087 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1088 (led->led_type == ATH_LED_RADIO));
1089 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1090 if (led->led_type == ATH_LED_RADIO)
1091 sc->sc_flags &= ~SC_OP_LED_ON;
1097 if (led->led_type == ATH_LED_ASSOC) {
1098 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1099 ieee80211_queue_delayed_work(sc->hw,
1100 &sc->ath_led_blink_work, 0);
1101 } else if (led->led_type == ATH_LED_RADIO) {
1102 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1103 sc->sc_flags |= SC_OP_LED_ON;
1113 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1119 led->led_cdev.name = led->name;
1120 led->led_cdev.default_trigger = trigger;
1121 led->led_cdev.brightness_set = ath_led_brightness;
1123 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1125 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1126 "Failed to register led:%s", led->name);
1128 led->registered = 1;
1132 static void ath_unregister_led(struct ath_led *led)
1134 if (led->registered) {
1135 led_classdev_unregister(&led->led_cdev);
1136 led->registered = 0;
1140 static void ath_deinit_leds(struct ath_softc *sc)
1142 ath_unregister_led(&sc->assoc_led);
1143 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1144 ath_unregister_led(&sc->tx_led);
1145 ath_unregister_led(&sc->rx_led);
1146 ath_unregister_led(&sc->radio_led);
1147 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1150 static void ath_init_leds(struct ath_softc *sc)
1155 if (AR_SREV_9287(sc->sc_ah))
1156 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1158 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1160 /* Configure gpio 1 for output */
1161 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1162 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1163 /* LED off, active low */
1164 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1166 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1168 trigger = ieee80211_get_radio_led_name(sc->hw);
1169 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1170 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1171 ret = ath_register_led(sc, &sc->radio_led, trigger);
1172 sc->radio_led.led_type = ATH_LED_RADIO;
1176 trigger = ieee80211_get_assoc_led_name(sc->hw);
1177 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1178 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1179 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1180 sc->assoc_led.led_type = ATH_LED_ASSOC;
1184 trigger = ieee80211_get_tx_led_name(sc->hw);
1185 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1186 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1187 ret = ath_register_led(sc, &sc->tx_led, trigger);
1188 sc->tx_led.led_type = ATH_LED_TX;
1192 trigger = ieee80211_get_rx_led_name(sc->hw);
1193 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1194 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1195 ret = ath_register_led(sc, &sc->rx_led, trigger);
1196 sc->rx_led.led_type = ATH_LED_RX;
1203 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1204 ath_deinit_leds(sc);
1207 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
1209 struct ath_hw *ah = sc->sc_ah;
1210 struct ath_common *common = ath9k_hw_common(ah);
1211 struct ieee80211_channel *channel = hw->conf.channel;
1214 ath9k_ps_wakeup(sc);
1215 ath9k_hw_configpcipowersave(ah, 0, 0);
1218 ah->curchan = ath_get_curchannel(sc, sc->hw);
1220 spin_lock_bh(&sc->sc_resetlock);
1221 r = ath9k_hw_reset(ah, ah->curchan, false);
1223 ath_print(common, ATH_DBG_FATAL,
1224 "Unable to reset channel %u (%uMhz) ",
1225 "reset status %d\n",
1226 channel->center_freq, r);
1228 spin_unlock_bh(&sc->sc_resetlock);
1230 ath_update_txpow(sc);
1231 if (ath_startrecv(sc) != 0) {
1232 ath_print(common, ATH_DBG_FATAL,
1233 "Unable to restart recv logic\n");
1237 if (sc->sc_flags & SC_OP_BEACONS)
1238 ath_beacon_config(sc, NULL); /* restart beacons */
1240 /* Re-Enable interrupts */
1241 ath9k_hw_set_interrupts(ah, sc->imask);
1244 ath9k_hw_cfg_output(ah, ah->led_pin,
1245 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1246 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1248 ieee80211_wake_queues(hw);
1249 ath9k_ps_restore(sc);
1252 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1254 struct ath_hw *ah = sc->sc_ah;
1255 struct ieee80211_channel *channel = hw->conf.channel;
1258 ath9k_ps_wakeup(sc);
1259 ieee80211_stop_queues(hw);
1262 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1263 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1265 /* Disable interrupts */
1266 ath9k_hw_set_interrupts(ah, 0);
1268 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1269 ath_stoprecv(sc); /* turn off frame recv */
1270 ath_flushrecv(sc); /* flush recv queue */
1273 ah->curchan = ath_get_curchannel(sc, hw);
1275 spin_lock_bh(&sc->sc_resetlock);
1276 r = ath9k_hw_reset(ah, ah->curchan, false);
1278 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1279 "Unable to reset channel %u (%uMhz) "
1280 "reset status %d\n",
1281 channel->center_freq, r);
1283 spin_unlock_bh(&sc->sc_resetlock);
1285 ath9k_hw_phy_disable(ah);
1286 ath9k_hw_configpcipowersave(ah, 1, 1);
1287 ath9k_ps_restore(sc);
1288 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1291 /*******************/
1293 /*******************/
1295 static bool ath_is_rfkill_set(struct ath_softc *sc)
1297 struct ath_hw *ah = sc->sc_ah;
1299 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1300 ah->rfkill_polarity;
1303 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1305 struct ath_wiphy *aphy = hw->priv;
1306 struct ath_softc *sc = aphy->sc;
1307 bool blocked = !!ath_is_rfkill_set(sc);
1309 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1312 static void ath_start_rfkill_poll(struct ath_softc *sc)
1314 struct ath_hw *ah = sc->sc_ah;
1316 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1317 wiphy_rfkill_start_polling(sc->hw->wiphy);
1320 static void ath9k_uninit_hw(struct ath_softc *sc)
1322 struct ath_hw *ah = sc->sc_ah;
1326 ath9k_exit_debug(ah);
1327 ath9k_hw_detach(ah);
1331 static void ath_clean_core(struct ath_softc *sc)
1333 struct ieee80211_hw *hw = sc->hw;
1334 struct ath_hw *ah = sc->sc_ah;
1337 ath9k_ps_wakeup(sc);
1339 dev_dbg(sc->dev, "Detach ATH hw\n");
1341 ath_deinit_leds(sc);
1342 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1344 for (i = 0; i < sc->num_sec_wiphy; i++) {
1345 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1348 sc->sec_wiphy[i] = NULL;
1349 ieee80211_unregister_hw(aphy->hw);
1350 ieee80211_free_hw(aphy->hw);
1352 ieee80211_unregister_hw(hw);
1356 tasklet_kill(&sc->intr_tq);
1357 tasklet_kill(&sc->bcon_tasklet);
1359 if (!(sc->sc_flags & SC_OP_INVALID))
1360 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1362 /* cleanup tx queues */
1363 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1364 if (ATH_TXQ_SETUP(sc, i))
1365 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1367 if ((sc->btcoex.no_stomp_timer) &&
1368 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1369 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1372 void ath_detach(struct ath_softc *sc)
1375 ath9k_uninit_hw(sc);
1378 void ath_cleanup(struct ath_softc *sc)
1380 struct ath_hw *ah = sc->sc_ah;
1381 struct ath_common *common = ath9k_hw_common(ah);
1384 free_irq(sc->irq, sc);
1385 ath_bus_cleanup(common);
1386 kfree(sc->sec_wiphy);
1387 ieee80211_free_hw(sc->hw);
1389 ath9k_uninit_hw(sc);
1392 static int ath9k_reg_notifier(struct wiphy *wiphy,
1393 struct regulatory_request *request)
1395 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1396 struct ath_wiphy *aphy = hw->priv;
1397 struct ath_softc *sc = aphy->sc;
1398 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1400 return ath_reg_notifier_apply(wiphy, request, reg);
1404 * Detects if there is any priority bt traffic
1406 static void ath_detect_bt_priority(struct ath_softc *sc)
1408 struct ath_btcoex *btcoex = &sc->btcoex;
1409 struct ath_hw *ah = sc->sc_ah;
1411 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1412 btcoex->bt_priority_cnt++;
1414 if (time_after(jiffies, btcoex->bt_priority_time +
1415 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1416 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1417 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1418 "BT priority traffic detected");
1419 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1421 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1424 btcoex->bt_priority_cnt = 0;
1425 btcoex->bt_priority_time = jiffies;
1430 * Configures appropriate weight based on stomp type.
1432 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1433 enum ath_stomp_type stomp_type)
1435 struct ath_hw *ah = sc->sc_ah;
1437 switch (stomp_type) {
1438 case ATH_BTCOEX_STOMP_ALL:
1439 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1440 AR_STOMP_ALL_WLAN_WGHT);
1442 case ATH_BTCOEX_STOMP_LOW:
1443 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1444 AR_STOMP_LOW_WLAN_WGHT);
1446 case ATH_BTCOEX_STOMP_NONE:
1447 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1448 AR_STOMP_NONE_WLAN_WGHT);
1451 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1452 "Invalid Stomptype\n");
1456 ath9k_hw_btcoex_enable(ah);
1459 static void ath9k_gen_timer_start(struct ath_hw *ah,
1460 struct ath_gen_timer *timer,
1464 struct ath_common *common = ath9k_hw_common(ah);
1465 struct ath_softc *sc = (struct ath_softc *) common->priv;
1467 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1469 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1470 ath9k_hw_set_interrupts(ah, 0);
1471 sc->imask |= ATH9K_INT_GENTIMER;
1472 ath9k_hw_set_interrupts(ah, sc->imask);
1476 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1478 struct ath_common *common = ath9k_hw_common(ah);
1479 struct ath_softc *sc = (struct ath_softc *) common->priv;
1480 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1482 ath9k_hw_gen_timer_stop(ah, timer);
1484 /* if no timer is enabled, turn off interrupt mask */
1485 if (timer_table->timer_mask.val == 0) {
1486 ath9k_hw_set_interrupts(ah, 0);
1487 sc->imask &= ~ATH9K_INT_GENTIMER;
1488 ath9k_hw_set_interrupts(ah, sc->imask);
1493 * This is the master bt coex timer which runs for every
1494 * 45ms, bt traffic will be given priority during 55% of this
1495 * period while wlan gets remaining 45%
1497 static void ath_btcoex_period_timer(unsigned long data)
1499 struct ath_softc *sc = (struct ath_softc *) data;
1500 struct ath_hw *ah = sc->sc_ah;
1501 struct ath_btcoex *btcoex = &sc->btcoex;
1503 ath_detect_bt_priority(sc);
1505 spin_lock_bh(&btcoex->btcoex_lock);
1507 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1509 spin_unlock_bh(&btcoex->btcoex_lock);
1511 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1512 if (btcoex->hw_timer_enabled)
1513 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1515 ath9k_gen_timer_start(ah,
1516 btcoex->no_stomp_timer,
1517 (ath9k_hw_gettsf32(ah) +
1518 btcoex->btcoex_no_stomp),
1519 btcoex->btcoex_no_stomp * 10);
1520 btcoex->hw_timer_enabled = true;
1523 mod_timer(&btcoex->period_timer, jiffies +
1524 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1528 * Generic tsf based hw timer which configures weight
1529 * registers to time slice between wlan and bt traffic
1531 static void ath_btcoex_no_stomp_timer(void *arg)
1533 struct ath_softc *sc = (struct ath_softc *)arg;
1534 struct ath_hw *ah = sc->sc_ah;
1535 struct ath_btcoex *btcoex = &sc->btcoex;
1537 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1538 "no stomp timer running \n");
1540 spin_lock_bh(&btcoex->btcoex_lock);
1542 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1543 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1544 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1545 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1547 spin_unlock_bh(&btcoex->btcoex_lock);
1550 static int ath_init_btcoex_timer(struct ath_softc *sc)
1552 struct ath_btcoex *btcoex = &sc->btcoex;
1554 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1555 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1556 btcoex->btcoex_period / 100;
1558 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1559 (unsigned long) sc);
1561 spin_lock_init(&btcoex->btcoex_lock);
1563 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1564 ath_btcoex_no_stomp_timer,
1565 ath_btcoex_no_stomp_timer,
1566 (void *) sc, AR_FIRST_NDP_TIMER);
1568 if (!btcoex->no_stomp_timer)
1575 * Read and write, they both share the same lock. We do this to serialize
1576 * reads and writes on Atheros 802.11n PCI devices only. This is required
1577 * as the FIFO on these devices can only accept sanely 2 requests. After
1578 * that the device goes bananas. Serializing the reads/writes prevents this
1582 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1584 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1585 struct ath_common *common = ath9k_hw_common(ah);
1586 struct ath_softc *sc = (struct ath_softc *) common->priv;
1588 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1589 unsigned long flags;
1590 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1591 iowrite32(val, sc->mem + reg_offset);
1592 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1594 iowrite32(val, sc->mem + reg_offset);
1597 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1599 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1600 struct ath_common *common = ath9k_hw_common(ah);
1601 struct ath_softc *sc = (struct ath_softc *) common->priv;
1604 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1605 unsigned long flags;
1606 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1607 val = ioread32(sc->mem + reg_offset);
1608 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1610 val = ioread32(sc->mem + reg_offset);
1614 static const struct ath_ops ath9k_common_ops = {
1615 .read = ath9k_ioread32,
1616 .write = ath9k_iowrite32,
1620 * Initialize and fill ath_softc, ath_sofct is the
1621 * "Software Carrier" struct. Historically it has existed
1622 * to allow the separation between hardware specific
1623 * variables (now in ath_hw) and driver specific variables.
1625 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1626 const struct ath_bus_ops *bus_ops)
1628 struct ath_hw *ah = NULL;
1629 struct ath_common *common;
1634 /* XXX: hardware will not be ready until ath_open() being called */
1635 sc->sc_flags |= SC_OP_INVALID;
1637 spin_lock_init(&sc->wiphy_lock);
1638 spin_lock_init(&sc->sc_resetlock);
1639 spin_lock_init(&sc->sc_serial_rw);
1640 spin_lock_init(&sc->ani_lock);
1641 spin_lock_init(&sc->sc_pm_lock);
1642 mutex_init(&sc->mutex);
1643 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1644 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1647 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1651 ah->hw_version.devid = devid;
1652 ah->hw_version.subsysid = subsysid;
1655 common = ath9k_hw_common(ah);
1656 common->ops = &ath9k_common_ops;
1657 common->bus_ops = bus_ops;
1659 common->hw = sc->hw;
1661 common->debug_mask = ath9k_debug;
1664 * Cache line size is used to size and align various
1665 * structures used to communicate with the hardware.
1667 ath_read_cachesize(common, &csz);
1668 /* XXX assert csz is non-zero */
1669 common->cachelsz = csz << 2; /* convert to bytes */
1671 r = ath9k_hw_init(ah);
1673 ath_print(common, ATH_DBG_FATAL,
1674 "Unable to initialize hardware; "
1675 "initialization status: %d\n", r);
1679 if (ath9k_init_debug(ah) < 0) {
1680 ath_print(common, ATH_DBG_FATAL,
1681 "Unable to create debugfs files\n");
1685 /* Get the hardware key cache size. */
1686 common->keymax = ah->caps.keycache_size;
1687 if (common->keymax > ATH_KEYMAX) {
1688 ath_print(common, ATH_DBG_ANY,
1689 "Warning, using only %u entries in %u key cache\n",
1690 ATH_KEYMAX, common->keymax);
1691 common->keymax = ATH_KEYMAX;
1695 * Reset the key cache since some parts do not
1696 * reset the contents on initial power up.
1698 for (i = 0; i < common->keymax; i++)
1699 ath9k_hw_keyreset(ah, (u16) i);
1701 /* default to MONITOR mode */
1702 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1704 /* Setup rate tables */
1706 ath_rate_attach(sc);
1707 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1708 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1711 * Allocate hardware transmit queues: one queue for
1712 * beacon frames and one data queue for each QoS
1713 * priority. Note that the hal handles reseting
1714 * these queues at the needed time.
1716 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1717 if (sc->beacon.beaconq == -1) {
1718 ath_print(common, ATH_DBG_FATAL,
1719 "Unable to setup a beacon xmit queue\n");
1723 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1724 if (sc->beacon.cabq == NULL) {
1725 ath_print(common, ATH_DBG_FATAL,
1726 "Unable to setup CAB xmit queue\n");
1731 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1732 ath_cabq_update(sc);
1734 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1735 sc->tx.hwq_map[i] = -1;
1737 /* Setup data queues */
1738 /* NB: ensure BK queue is the lowest priority h/w queue */
1739 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1740 ath_print(common, ATH_DBG_FATAL,
1741 "Unable to setup xmit queue for BK traffic\n");
1746 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1747 ath_print(common, ATH_DBG_FATAL,
1748 "Unable to setup xmit queue for BE traffic\n");
1752 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1753 ath_print(common, ATH_DBG_FATAL,
1754 "Unable to setup xmit queue for VI traffic\n");
1758 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1759 ath_print(common, ATH_DBG_FATAL,
1760 "Unable to setup xmit queue for VO traffic\n");
1765 /* Initializes the noise floor to a reasonable default value.
1766 * Later on this will be updated during ANI processing. */
1768 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1769 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1771 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1772 ATH9K_CIPHER_TKIP, NULL)) {
1774 * Whether we should enable h/w TKIP MIC.
1775 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1776 * report WMM capable, so it's always safe to turn on
1777 * TKIP MIC in this case.
1779 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1784 * Check whether the separate key cache entries
1785 * are required to handle both tx+rx MIC keys.
1786 * With split mic keys the number of stations is limited
1787 * to 27 otherwise 59.
1789 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1790 ATH9K_CIPHER_TKIP, NULL)
1791 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1792 ATH9K_CIPHER_MIC, NULL)
1793 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1795 common->splitmic = 1;
1797 /* turn on mcast key search if possible */
1798 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1799 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1802 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1804 /* 11n Capabilities */
1805 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1806 sc->sc_flags |= SC_OP_TXAGGR;
1807 sc->sc_flags |= SC_OP_RXAGGR;
1810 common->tx_chainmask = ah->caps.tx_chainmask;
1811 common->rx_chainmask = ah->caps.rx_chainmask;
1813 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1814 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1816 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1817 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1819 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1821 /* initialize beacon slots */
1822 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1823 sc->beacon.bslot[i] = NULL;
1824 sc->beacon.bslot_aphy[i] = NULL;
1827 /* setup channels and rates */
1829 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1830 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1831 sc->rates[IEEE80211_BAND_2GHZ];
1832 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1833 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1834 ARRAY_SIZE(ath9k_2ghz_chantable);
1836 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1837 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1838 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1839 sc->rates[IEEE80211_BAND_5GHZ];
1840 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1841 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1842 ARRAY_SIZE(ath9k_5ghz_chantable);
1845 switch (ah->btcoex_hw.scheme) {
1846 case ATH_BTCOEX_CFG_NONE:
1848 case ATH_BTCOEX_CFG_2WIRE:
1849 ath9k_hw_btcoex_init_2wire(ah);
1851 case ATH_BTCOEX_CFG_3WIRE:
1852 ath9k_hw_btcoex_init_3wire(ah);
1853 r = ath_init_btcoex_timer(sc);
1856 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1857 ath9k_hw_init_btcoex_hw(ah, qnum);
1858 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1867 /* cleanup tx queues */
1868 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1869 if (ATH_TXQ_SETUP(sc, i))
1870 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1873 ath9k_uninit_hw(sc);
1877 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1879 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1880 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1881 IEEE80211_HW_SIGNAL_DBM |
1882 IEEE80211_HW_AMPDU_AGGREGATION |
1883 IEEE80211_HW_SUPPORTS_PS |
1884 IEEE80211_HW_PS_NULLFUNC_STACK |
1885 IEEE80211_HW_SPECTRUM_MGMT;
1887 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1888 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1890 hw->wiphy->interface_modes =
1891 BIT(NL80211_IFTYPE_AP) |
1892 BIT(NL80211_IFTYPE_STATION) |
1893 BIT(NL80211_IFTYPE_ADHOC) |
1894 BIT(NL80211_IFTYPE_MESH_POINT);
1898 hw->channel_change_time = 5000;
1899 hw->max_listen_interval = 10;
1900 /* Hardware supports 10 but we use 4 */
1901 hw->max_rate_tries = 4;
1902 hw->sta_data_size = sizeof(struct ath_node);
1903 hw->vif_data_size = sizeof(struct ath_vif);
1905 hw->rate_control_algorithm = "ath9k_rate_control";
1907 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1908 &sc->sbands[IEEE80211_BAND_2GHZ];
1909 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1910 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1911 &sc->sbands[IEEE80211_BAND_5GHZ];
1914 /* Device driver core initialization */
1915 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1916 const struct ath_bus_ops *bus_ops)
1918 struct ieee80211_hw *hw = sc->hw;
1919 struct ath_common *common;
1922 struct ath_regulatory *reg;
1924 dev_dbg(sc->dev, "Attach ATH hw\n");
1926 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1931 common = ath9k_hw_common(ah);
1933 /* get mac address from hardware and set in mac80211 */
1935 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1937 ath_set_hw_capab(sc, hw);
1939 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1940 ath9k_reg_notifier);
1944 reg = &common->regulatory;
1946 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1947 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1948 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1949 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1952 /* initialize tx/rx engine */
1953 error = ath_tx_init(sc, ATH_TXBUF);
1957 error = ath_rx_init(sc, ATH_RXBUF);
1961 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1962 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1963 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1965 error = ieee80211_register_hw(hw);
1967 if (!ath_is_world_regd(reg)) {
1968 error = regulatory_hint(hw->wiphy, reg->alpha2);
1973 /* Initialize LED control */
1976 ath_start_rfkill_poll(sc);
1981 /* cleanup tx queues */
1982 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1983 if (ATH_TXQ_SETUP(sc, i))
1984 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1986 ath9k_uninit_hw(sc);
1991 int ath_reset(struct ath_softc *sc, bool retry_tx)
1993 struct ath_hw *ah = sc->sc_ah;
1994 struct ath_common *common = ath9k_hw_common(ah);
1995 struct ieee80211_hw *hw = sc->hw;
1998 ath9k_hw_set_interrupts(ah, 0);
1999 ath_drain_all_txq(sc, retry_tx);
2003 spin_lock_bh(&sc->sc_resetlock);
2004 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
2006 ath_print(common, ATH_DBG_FATAL,
2007 "Unable to reset hardware; reset status %d\n", r);
2008 spin_unlock_bh(&sc->sc_resetlock);
2010 if (ath_startrecv(sc) != 0)
2011 ath_print(common, ATH_DBG_FATAL,
2012 "Unable to start recv logic\n");
2015 * We may be doing a reset in response to a request
2016 * that changes the channel so update any state that
2017 * might change as a result.
2019 ath_cache_conf_rate(sc, &hw->conf);
2021 ath_update_txpow(sc);
2023 if (sc->sc_flags & SC_OP_BEACONS)
2024 ath_beacon_config(sc, NULL); /* restart beacons */
2026 ath9k_hw_set_interrupts(ah, sc->imask);
2030 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2031 if (ATH_TXQ_SETUP(sc, i)) {
2032 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2033 ath_txq_schedule(sc, &sc->tx.txq[i]);
2034 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2043 * This function will allocate both the DMA descriptor structure, and the
2044 * buffers it contains. These are used to contain the descriptors used
2047 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2048 struct list_head *head, const char *name,
2049 int nbuf, int ndesc)
2051 #define DS2PHYS(_dd, _ds) \
2052 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2053 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2054 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2055 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2056 struct ath_desc *ds;
2058 int i, bsize, error;
2060 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2063 INIT_LIST_HEAD(head);
2064 /* ath_desc must be a multiple of DWORDs */
2065 if ((sizeof(struct ath_desc) % 4) != 0) {
2066 ath_print(common, ATH_DBG_FATAL,
2067 "ath_desc not DWORD aligned\n");
2068 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2073 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2076 * Need additional DMA memory because we can't use
2077 * descriptors that cross the 4K page boundary. Assume
2078 * one skipped descriptor per 4K page.
2080 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2082 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2085 while (ndesc_skipped) {
2086 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2087 dd->dd_desc_len += dma_len;
2089 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2093 /* allocate descriptors */
2094 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2095 &dd->dd_desc_paddr, GFP_KERNEL);
2096 if (dd->dd_desc == NULL) {
2101 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2102 name, ds, (u32) dd->dd_desc_len,
2103 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2105 /* allocate buffers */
2106 bsize = sizeof(struct ath_buf) * nbuf;
2107 bf = kzalloc(bsize, GFP_KERNEL);
2114 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2116 bf->bf_daddr = DS2PHYS(dd, ds);
2118 if (!(sc->sc_ah->caps.hw_caps &
2119 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2121 * Skip descriptor addresses which can cause 4KB
2122 * boundary crossing (addr + length) with a 32 dword
2125 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2126 BUG_ON((caddr_t) bf->bf_desc >=
2127 ((caddr_t) dd->dd_desc +
2132 bf->bf_daddr = DS2PHYS(dd, ds);
2135 list_add_tail(&bf->list, head);
2139 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2142 memset(dd, 0, sizeof(*dd));
2144 #undef ATH_DESC_4KB_BOUND_CHECK
2145 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2149 void ath_descdma_cleanup(struct ath_softc *sc,
2150 struct ath_descdma *dd,
2151 struct list_head *head)
2153 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2156 INIT_LIST_HEAD(head);
2157 kfree(dd->dd_bufptr);
2158 memset(dd, 0, sizeof(*dd));
2161 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2167 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2170 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2173 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2176 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2179 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2186 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2191 case ATH9K_WME_AC_VO:
2194 case ATH9K_WME_AC_VI:
2197 case ATH9K_WME_AC_BE:
2200 case ATH9K_WME_AC_BK:
2211 /* XXX: Remove me once we don't depend on ath9k_channel for all
2212 * this redundant data */
2213 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2214 struct ath9k_channel *ichan)
2216 struct ieee80211_channel *chan = hw->conf.channel;
2217 struct ieee80211_conf *conf = &hw->conf;
2219 ichan->channel = chan->center_freq;
2222 if (chan->band == IEEE80211_BAND_2GHZ) {
2223 ichan->chanmode = CHANNEL_G;
2224 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2226 ichan->chanmode = CHANNEL_A;
2227 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2230 if (conf_is_ht(conf))
2231 ichan->chanmode = ath_get_extchanmode(sc, chan,
2232 conf->channel_type);
2235 /**********************/
2236 /* mac80211 callbacks */
2237 /**********************/
2240 * (Re)start btcoex timers
2242 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2244 struct ath_btcoex *btcoex = &sc->btcoex;
2245 struct ath_hw *ah = sc->sc_ah;
2247 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2248 "Starting btcoex timers");
2250 /* make sure duty cycle timer is also stopped when resuming */
2251 if (btcoex->hw_timer_enabled)
2252 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2254 btcoex->bt_priority_cnt = 0;
2255 btcoex->bt_priority_time = jiffies;
2256 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2258 mod_timer(&btcoex->period_timer, jiffies);
2261 static int ath9k_start(struct ieee80211_hw *hw)
2263 struct ath_wiphy *aphy = hw->priv;
2264 struct ath_softc *sc = aphy->sc;
2265 struct ath_hw *ah = sc->sc_ah;
2266 struct ath_common *common = ath9k_hw_common(ah);
2267 struct ieee80211_channel *curchan = hw->conf.channel;
2268 struct ath9k_channel *init_channel;
2271 ath_print(common, ATH_DBG_CONFIG,
2272 "Starting driver with initial channel: %d MHz\n",
2273 curchan->center_freq);
2275 mutex_lock(&sc->mutex);
2277 if (ath9k_wiphy_started(sc)) {
2278 if (sc->chan_idx == curchan->hw_value) {
2280 * Already on the operational channel, the new wiphy
2281 * can be marked active.
2283 aphy->state = ATH_WIPHY_ACTIVE;
2284 ieee80211_wake_queues(hw);
2287 * Another wiphy is on another channel, start the new
2288 * wiphy in paused state.
2290 aphy->state = ATH_WIPHY_PAUSED;
2291 ieee80211_stop_queues(hw);
2293 mutex_unlock(&sc->mutex);
2296 aphy->state = ATH_WIPHY_ACTIVE;
2298 /* setup initial channel */
2300 sc->chan_idx = curchan->hw_value;
2302 init_channel = ath_get_curchannel(sc, hw);
2304 /* Reset SERDES registers */
2305 ath9k_hw_configpcipowersave(ah, 0, 0);
2308 * The basic interface to setting the hardware in a good
2309 * state is ``reset''. On return the hardware is known to
2310 * be powered up and with interrupts disabled. This must
2311 * be followed by initialization of the appropriate bits
2312 * and then setup of the interrupt mask.
2314 spin_lock_bh(&sc->sc_resetlock);
2315 r = ath9k_hw_reset(ah, init_channel, false);
2317 ath_print(common, ATH_DBG_FATAL,
2318 "Unable to reset hardware; reset status %d "
2319 "(freq %u MHz)\n", r,
2320 curchan->center_freq);
2321 spin_unlock_bh(&sc->sc_resetlock);
2324 spin_unlock_bh(&sc->sc_resetlock);
2327 * This is needed only to setup initial state
2328 * but it's best done after a reset.
2330 ath_update_txpow(sc);
2333 * Setup the hardware after reset:
2334 * The receive engine is set going.
2335 * Frame transmit is handled entirely
2336 * in the frame output path; there's nothing to do
2337 * here except setup the interrupt mask.
2339 if (ath_startrecv(sc) != 0) {
2340 ath_print(common, ATH_DBG_FATAL,
2341 "Unable to start recv logic\n");
2346 /* Setup our intr mask. */
2347 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2348 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2349 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2351 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2352 sc->imask |= ATH9K_INT_GTT;
2354 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2355 sc->imask |= ATH9K_INT_CST;
2357 ath_cache_conf_rate(sc, &hw->conf);
2359 sc->sc_flags &= ~SC_OP_INVALID;
2361 /* Disable BMISS interrupt when we're not associated */
2362 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2363 ath9k_hw_set_interrupts(ah, sc->imask);
2365 ieee80211_wake_queues(hw);
2367 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2369 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2370 !ah->btcoex_hw.enabled) {
2371 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2372 AR_STOMP_LOW_WLAN_WGHT);
2373 ath9k_hw_btcoex_enable(ah);
2375 if (common->bus_ops->bt_coex_prep)
2376 common->bus_ops->bt_coex_prep(common);
2377 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2378 ath9k_btcoex_timer_resume(sc);
2382 mutex_unlock(&sc->mutex);
2387 static int ath9k_tx(struct ieee80211_hw *hw,
2388 struct sk_buff *skb)
2390 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2391 struct ath_wiphy *aphy = hw->priv;
2392 struct ath_softc *sc = aphy->sc;
2393 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2394 struct ath_tx_control txctl;
2395 int hdrlen, padsize;
2397 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2398 ath_print(common, ATH_DBG_XMIT,
2399 "ath9k: %s: TX in unexpected wiphy state "
2400 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2404 if (sc->ps_enabled) {
2405 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2407 * mac80211 does not set PM field for normal data frames, so we
2408 * need to update that based on the current PS mode.
2410 if (ieee80211_is_data(hdr->frame_control) &&
2411 !ieee80211_is_nullfunc(hdr->frame_control) &&
2412 !ieee80211_has_pm(hdr->frame_control)) {
2413 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2414 "while in PS mode\n");
2415 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2419 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2421 * We are using PS-Poll and mac80211 can request TX while in
2422 * power save mode. Need to wake up hardware for the TX to be
2423 * completed and if needed, also for RX of buffered frames.
2425 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2426 ath9k_ps_wakeup(sc);
2427 ath9k_hw_setrxabort(sc->sc_ah, 0);
2428 if (ieee80211_is_pspoll(hdr->frame_control)) {
2429 ath_print(common, ATH_DBG_PS,
2430 "Sending PS-Poll to pick a buffered frame\n");
2431 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2433 ath_print(common, ATH_DBG_PS,
2434 "Wake up to complete TX\n");
2435 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2438 * The actual restore operation will happen only after
2439 * the sc_flags bit is cleared. We are just dropping
2440 * the ps_usecount here.
2442 ath9k_ps_restore(sc);
2445 memset(&txctl, 0, sizeof(struct ath_tx_control));
2448 * As a temporary workaround, assign seq# here; this will likely need
2449 * to be cleaned up to work better with Beacon transmission and virtual
2452 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2453 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2454 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2455 sc->tx.seq_no += 0x10;
2456 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2457 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2460 /* Add the padding after the header if this is not already done */
2461 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2463 padsize = hdrlen % 4;
2464 if (skb_headroom(skb) < padsize)
2466 skb_push(skb, padsize);
2467 memmove(skb->data, skb->data + padsize, hdrlen);
2470 /* Check if a tx queue is available */
2472 txctl.txq = ath_test_get_txq(sc, skb);
2476 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2478 if (ath_tx_start(hw, skb, &txctl) != 0) {
2479 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2485 dev_kfree_skb_any(skb);
2490 * Pause btcoex timer and bt duty cycle timer
2492 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2494 struct ath_btcoex *btcoex = &sc->btcoex;
2495 struct ath_hw *ah = sc->sc_ah;
2497 del_timer_sync(&btcoex->period_timer);
2499 if (btcoex->hw_timer_enabled)
2500 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2502 btcoex->hw_timer_enabled = false;
2505 static void ath9k_stop(struct ieee80211_hw *hw)
2507 struct ath_wiphy *aphy = hw->priv;
2508 struct ath_softc *sc = aphy->sc;
2509 struct ath_hw *ah = sc->sc_ah;
2510 struct ath_common *common = ath9k_hw_common(ah);
2512 mutex_lock(&sc->mutex);
2514 aphy->state = ATH_WIPHY_INACTIVE;
2516 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2517 cancel_delayed_work_sync(&sc->tx_complete_work);
2519 if (!sc->num_sec_wiphy) {
2520 cancel_delayed_work_sync(&sc->wiphy_work);
2521 cancel_work_sync(&sc->chan_work);
2524 if (sc->sc_flags & SC_OP_INVALID) {
2525 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2526 mutex_unlock(&sc->mutex);
2530 if (ath9k_wiphy_started(sc)) {
2531 mutex_unlock(&sc->mutex);
2532 return; /* another wiphy still in use */
2535 if (ah->btcoex_hw.enabled) {
2536 ath9k_hw_btcoex_disable(ah);
2537 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2538 ath9k_btcoex_timer_pause(sc);
2541 /* make sure h/w will not generate any interrupt
2542 * before setting the invalid flag. */
2543 ath9k_hw_set_interrupts(ah, 0);
2545 if (!(sc->sc_flags & SC_OP_INVALID)) {
2546 ath_drain_all_txq(sc, false);
2548 ath9k_hw_phy_disable(ah);
2550 sc->rx.rxlink = NULL;
2552 /* disable HAL and put h/w to sleep */
2553 ath9k_hw_disable(ah);
2554 ath9k_hw_configpcipowersave(ah, 1, 1);
2555 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2557 sc->sc_flags |= SC_OP_INVALID;
2559 mutex_unlock(&sc->mutex);
2561 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2564 static int ath9k_add_interface(struct ieee80211_hw *hw,
2565 struct ieee80211_if_init_conf *conf)
2567 struct ath_wiphy *aphy = hw->priv;
2568 struct ath_softc *sc = aphy->sc;
2569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2570 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2571 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2574 mutex_lock(&sc->mutex);
2576 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2582 switch (conf->type) {
2583 case NL80211_IFTYPE_STATION:
2584 ic_opmode = NL80211_IFTYPE_STATION;
2586 case NL80211_IFTYPE_ADHOC:
2587 case NL80211_IFTYPE_AP:
2588 case NL80211_IFTYPE_MESH_POINT:
2589 if (sc->nbcnvifs >= ATH_BCBUF) {
2593 ic_opmode = conf->type;
2596 ath_print(common, ATH_DBG_FATAL,
2597 "Interface type %d not yet supported\n", conf->type);
2602 ath_print(common, ATH_DBG_CONFIG,
2603 "Attach a VIF of type: %d\n", ic_opmode);
2605 /* Set the VIF opmode */
2606 avp->av_opmode = ic_opmode;
2611 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2612 ath9k_set_bssid_mask(hw);
2615 goto out; /* skip global settings for secondary vif */
2617 if (ic_opmode == NL80211_IFTYPE_AP) {
2618 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2619 sc->sc_flags |= SC_OP_TSF_RESET;
2622 /* Set the device opmode */
2623 sc->sc_ah->opmode = ic_opmode;
2626 * Enable MIB interrupts when there are hardware phy counters.
2627 * Note we only do this (at the moment) for station mode.
2629 if ((conf->type == NL80211_IFTYPE_STATION) ||
2630 (conf->type == NL80211_IFTYPE_ADHOC) ||
2631 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2632 sc->imask |= ATH9K_INT_MIB;
2633 sc->imask |= ATH9K_INT_TSFOOR;
2636 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2638 if (conf->type == NL80211_IFTYPE_AP ||
2639 conf->type == NL80211_IFTYPE_ADHOC ||
2640 conf->type == NL80211_IFTYPE_MONITOR)
2641 ath_start_ani(common);
2644 mutex_unlock(&sc->mutex);
2648 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2649 struct ieee80211_if_init_conf *conf)
2651 struct ath_wiphy *aphy = hw->priv;
2652 struct ath_softc *sc = aphy->sc;
2653 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2654 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2657 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2659 mutex_lock(&sc->mutex);
2662 del_timer_sync(&common->ani.timer);
2664 /* Reclaim beacon resources */
2665 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2666 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2667 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2668 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2669 ath_beacon_return(sc, avp);
2672 sc->sc_flags &= ~SC_OP_BEACONS;
2674 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2675 if (sc->beacon.bslot[i] == conf->vif) {
2676 printk(KERN_DEBUG "%s: vif had allocated beacon "
2677 "slot\n", __func__);
2678 sc->beacon.bslot[i] = NULL;
2679 sc->beacon.bslot_aphy[i] = NULL;
2685 mutex_unlock(&sc->mutex);
2688 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2690 struct ath_wiphy *aphy = hw->priv;
2691 struct ath_softc *sc = aphy->sc;
2692 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2693 struct ieee80211_conf *conf = &hw->conf;
2694 struct ath_hw *ah = sc->sc_ah;
2697 mutex_lock(&sc->mutex);
2700 * Leave this as the first check because we need to turn on the
2701 * radio if it was disabled before prior to processing the rest
2702 * of the changes. Likewise we must only disable the radio towards
2705 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2707 bool all_wiphys_idle;
2708 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2710 spin_lock_bh(&sc->wiphy_lock);
2711 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2712 ath9k_set_wiphy_idle(aphy, idle);
2714 if (!idle && all_wiphys_idle)
2715 enable_radio = true;
2718 * After we unlock here its possible another wiphy
2719 * can be re-renabled so to account for that we will
2720 * only disable the radio toward the end of this routine
2721 * if by then all wiphys are still idle.
2723 spin_unlock_bh(&sc->wiphy_lock);
2726 ath_radio_enable(sc, hw);
2727 ath_print(common, ATH_DBG_CONFIG,
2728 "not-idle: enabling radio\n");
2732 if (changed & IEEE80211_CONF_CHANGE_PS) {
2733 if (conf->flags & IEEE80211_CONF_PS) {
2734 if (!(ah->caps.hw_caps &
2735 ATH9K_HW_CAP_AUTOSLEEP)) {
2736 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2737 sc->imask |= ATH9K_INT_TIM_TIMER;
2738 ath9k_hw_set_interrupts(sc->sc_ah,
2741 ath9k_hw_setrxabort(sc->sc_ah, 1);
2743 sc->ps_enabled = true;
2745 sc->ps_enabled = false;
2746 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2747 if (!(ah->caps.hw_caps &
2748 ATH9K_HW_CAP_AUTOSLEEP)) {
2749 ath9k_hw_setrxabort(sc->sc_ah, 0);
2750 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2751 SC_OP_WAIT_FOR_CAB |
2752 SC_OP_WAIT_FOR_PSPOLL_DATA |
2753 SC_OP_WAIT_FOR_TX_ACK);
2754 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2755 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2756 ath9k_hw_set_interrupts(sc->sc_ah,
2763 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2764 struct ieee80211_channel *curchan = hw->conf.channel;
2765 int pos = curchan->hw_value;
2767 aphy->chan_idx = pos;
2768 aphy->chan_is_ht = conf_is_ht(conf);
2770 if (aphy->state == ATH_WIPHY_SCAN ||
2771 aphy->state == ATH_WIPHY_ACTIVE)
2772 ath9k_wiphy_pause_all_forced(sc, aphy);
2775 * Do not change operational channel based on a paused
2778 goto skip_chan_change;
2781 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2782 curchan->center_freq);
2784 /* XXX: remove me eventualy */
2785 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2787 ath_update_chainmask(sc, conf_is_ht(conf));
2789 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2790 ath_print(common, ATH_DBG_FATAL,
2791 "Unable to set channel\n");
2792 mutex_unlock(&sc->mutex);
2798 if (changed & IEEE80211_CONF_CHANGE_POWER)
2799 sc->config.txpowlimit = 2 * conf->power_level;
2801 spin_lock_bh(&sc->wiphy_lock);
2802 disable_radio = ath9k_all_wiphys_idle(sc);
2803 spin_unlock_bh(&sc->wiphy_lock);
2805 if (disable_radio) {
2806 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2807 ath_radio_disable(sc, hw);
2810 mutex_unlock(&sc->mutex);
2815 #define SUPPORTED_FILTERS \
2816 (FIF_PROMISC_IN_BSS | \
2821 FIF_BCN_PRBRESP_PROMISC | \
2824 /* FIXME: sc->sc_full_reset ? */
2825 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2826 unsigned int changed_flags,
2827 unsigned int *total_flags,
2830 struct ath_wiphy *aphy = hw->priv;
2831 struct ath_softc *sc = aphy->sc;
2834 changed_flags &= SUPPORTED_FILTERS;
2835 *total_flags &= SUPPORTED_FILTERS;
2837 sc->rx.rxfilter = *total_flags;
2838 ath9k_ps_wakeup(sc);
2839 rfilt = ath_calcrxfilter(sc);
2840 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2841 ath9k_ps_restore(sc);
2843 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2844 "Set HW RX filter: 0x%x\n", rfilt);
2847 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2848 struct ieee80211_vif *vif,
2849 enum sta_notify_cmd cmd,
2850 struct ieee80211_sta *sta)
2852 struct ath_wiphy *aphy = hw->priv;
2853 struct ath_softc *sc = aphy->sc;
2856 case STA_NOTIFY_ADD:
2857 ath_node_attach(sc, sta);
2859 case STA_NOTIFY_REMOVE:
2860 ath_node_detach(sc, sta);
2867 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2868 const struct ieee80211_tx_queue_params *params)
2870 struct ath_wiphy *aphy = hw->priv;
2871 struct ath_softc *sc = aphy->sc;
2872 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2873 struct ath9k_tx_queue_info qi;
2876 if (queue >= WME_NUM_AC)
2879 mutex_lock(&sc->mutex);
2881 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2883 qi.tqi_aifs = params->aifs;
2884 qi.tqi_cwmin = params->cw_min;
2885 qi.tqi_cwmax = params->cw_max;
2886 qi.tqi_burstTime = params->txop;
2887 qnum = ath_get_hal_qnum(queue, sc);
2889 ath_print(common, ATH_DBG_CONFIG,
2890 "Configure tx [queue/halq] [%d/%d], "
2891 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2892 queue, qnum, params->aifs, params->cw_min,
2893 params->cw_max, params->txop);
2895 ret = ath_txq_update(sc, qnum, &qi);
2897 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2899 mutex_unlock(&sc->mutex);
2904 static int ath9k_set_key(struct ieee80211_hw *hw,
2905 enum set_key_cmd cmd,
2906 struct ieee80211_vif *vif,
2907 struct ieee80211_sta *sta,
2908 struct ieee80211_key_conf *key)
2910 struct ath_wiphy *aphy = hw->priv;
2911 struct ath_softc *sc = aphy->sc;
2912 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2915 if (modparam_nohwcrypt)
2918 mutex_lock(&sc->mutex);
2919 ath9k_ps_wakeup(sc);
2920 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2924 ret = ath_key_config(common, vif, sta, key);
2926 key->hw_key_idx = ret;
2927 /* push IV and Michael MIC generation to stack */
2928 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2929 if (key->alg == ALG_TKIP)
2930 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2931 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2932 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2937 ath_key_delete(common, key);
2943 ath9k_ps_restore(sc);
2944 mutex_unlock(&sc->mutex);
2949 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2950 struct ieee80211_vif *vif,
2951 struct ieee80211_bss_conf *bss_conf,
2954 struct ath_wiphy *aphy = hw->priv;
2955 struct ath_softc *sc = aphy->sc;
2956 struct ath_hw *ah = sc->sc_ah;
2957 struct ath_common *common = ath9k_hw_common(ah);
2958 struct ath_vif *avp = (void *)vif->drv_priv;
2961 mutex_lock(&sc->mutex);
2963 if (changed & BSS_CHANGED_BSSID) {
2965 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2966 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2968 ath9k_hw_write_associd(ah);
2970 /* Set aggregation protection mode parameters */
2971 sc->config.ath_aggr_prot = 0;
2973 /* Only legacy IBSS for now */
2974 if (vif->type == NL80211_IFTYPE_ADHOC)
2975 ath_update_chainmask(sc, 0);
2977 ath_print(common, ATH_DBG_CONFIG,
2978 "BSSID: %pM aid: 0x%x\n",
2979 common->curbssid, common->curaid);
2981 /* need to reconfigure the beacon */
2982 sc->sc_flags &= ~SC_OP_BEACONS ;
2985 /* Enable transmission of beacons (AP, IBSS, MESH) */
2986 if ((changed & BSS_CHANGED_BEACON) ||
2987 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2988 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2989 error = ath_beacon_alloc(aphy, vif);
2991 ath_beacon_config(sc, vif);
2994 /* Disable transmission of beacons */
2995 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2996 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2998 if (changed & BSS_CHANGED_BEACON_INT) {
2999 sc->beacon_interval = bss_conf->beacon_int;
3001 * In case of AP mode, the HW TSF has to be reset
3002 * when the beacon interval changes.
3004 if (vif->type == NL80211_IFTYPE_AP) {
3005 sc->sc_flags |= SC_OP_TSF_RESET;
3006 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3007 error = ath_beacon_alloc(aphy, vif);
3009 ath_beacon_config(sc, vif);
3011 ath_beacon_config(sc, vif);
3015 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3016 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3017 bss_conf->use_short_preamble);
3018 if (bss_conf->use_short_preamble)
3019 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3021 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3024 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3025 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3026 bss_conf->use_cts_prot);
3027 if (bss_conf->use_cts_prot &&
3028 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3029 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3031 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3034 if (changed & BSS_CHANGED_ASSOC) {
3035 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3037 ath9k_bss_assoc_info(sc, vif, bss_conf);
3040 mutex_unlock(&sc->mutex);
3043 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3046 struct ath_wiphy *aphy = hw->priv;
3047 struct ath_softc *sc = aphy->sc;
3049 mutex_lock(&sc->mutex);
3050 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3051 mutex_unlock(&sc->mutex);
3056 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3058 struct ath_wiphy *aphy = hw->priv;
3059 struct ath_softc *sc = aphy->sc;
3061 mutex_lock(&sc->mutex);
3062 ath9k_hw_settsf64(sc->sc_ah, tsf);
3063 mutex_unlock(&sc->mutex);
3066 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3068 struct ath_wiphy *aphy = hw->priv;
3069 struct ath_softc *sc = aphy->sc;
3071 mutex_lock(&sc->mutex);
3073 ath9k_ps_wakeup(sc);
3074 ath9k_hw_reset_tsf(sc->sc_ah);
3075 ath9k_ps_restore(sc);
3077 mutex_unlock(&sc->mutex);
3080 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3081 struct ieee80211_vif *vif,
3082 enum ieee80211_ampdu_mlme_action action,
3083 struct ieee80211_sta *sta,
3086 struct ath_wiphy *aphy = hw->priv;
3087 struct ath_softc *sc = aphy->sc;
3091 case IEEE80211_AMPDU_RX_START:
3092 if (!(sc->sc_flags & SC_OP_RXAGGR))
3095 case IEEE80211_AMPDU_RX_STOP:
3097 case IEEE80211_AMPDU_TX_START:
3098 ath_tx_aggr_start(sc, sta, tid, ssn);
3099 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3101 case IEEE80211_AMPDU_TX_STOP:
3102 ath_tx_aggr_stop(sc, sta, tid);
3103 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3105 case IEEE80211_AMPDU_TX_OPERATIONAL:
3106 ath_tx_aggr_resume(sc, sta, tid);
3109 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3110 "Unknown AMPDU action\n");
3116 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3118 struct ath_wiphy *aphy = hw->priv;
3119 struct ath_softc *sc = aphy->sc;
3121 mutex_lock(&sc->mutex);
3122 if (ath9k_wiphy_scanning(sc)) {
3123 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3126 * Do not allow the concurrent scanning state for now. This
3127 * could be improved with scanning control moved into ath9k.
3129 mutex_unlock(&sc->mutex);
3133 aphy->state = ATH_WIPHY_SCAN;
3134 ath9k_wiphy_pause_all_forced(sc, aphy);
3136 spin_lock_bh(&sc->ani_lock);
3137 sc->sc_flags |= SC_OP_SCANNING;
3138 spin_unlock_bh(&sc->ani_lock);
3139 mutex_unlock(&sc->mutex);
3142 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3144 struct ath_wiphy *aphy = hw->priv;
3145 struct ath_softc *sc = aphy->sc;
3147 mutex_lock(&sc->mutex);
3148 spin_lock_bh(&sc->ani_lock);
3149 aphy->state = ATH_WIPHY_ACTIVE;
3150 sc->sc_flags &= ~SC_OP_SCANNING;
3151 sc->sc_flags |= SC_OP_FULL_RESET;
3152 spin_unlock_bh(&sc->ani_lock);
3153 ath_beacon_config(sc, NULL);
3154 mutex_unlock(&sc->mutex);
3157 struct ieee80211_ops ath9k_ops = {
3159 .start = ath9k_start,
3161 .add_interface = ath9k_add_interface,
3162 .remove_interface = ath9k_remove_interface,
3163 .config = ath9k_config,
3164 .configure_filter = ath9k_configure_filter,
3165 .sta_notify = ath9k_sta_notify,
3166 .conf_tx = ath9k_conf_tx,
3167 .bss_info_changed = ath9k_bss_info_changed,
3168 .set_key = ath9k_set_key,
3169 .get_tsf = ath9k_get_tsf,
3170 .set_tsf = ath9k_set_tsf,
3171 .reset_tsf = ath9k_reset_tsf,
3172 .ampdu_action = ath9k_ampdu_action,
3173 .sw_scan_start = ath9k_sw_scan_start,
3174 .sw_scan_complete = ath9k_sw_scan_complete,
3175 .rfkill_poll = ath9k_rfkill_poll_state,
3178 static int __init ath9k_init(void)
3182 /* Register rate control algorithm */
3183 error = ath_rate_control_register();
3186 "ath9k: Unable to register rate control "
3192 error = ath9k_debug_create_root();
3195 "ath9k: Unable to create debugfs root: %d\n",
3197 goto err_rate_unregister;
3200 error = ath_pci_init();
3203 "ath9k: No PCI devices found, driver not installed.\n");
3205 goto err_remove_root;
3208 error = ath_ahb_init();
3220 ath9k_debug_remove_root();
3221 err_rate_unregister:
3222 ath_rate_control_unregister();
3226 module_init(ath9k_init);
3228 static void __exit ath9k_exit(void)
3232 ath9k_debug_remove_root();
3233 ath_rate_control_unregister();
3234 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3236 module_exit(ath9k_exit);