drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static void ath_cache_conf_rate(struct ath_softc *sc,
  22                                 struct ieee80211_conf *conf)
  23 {
  24         switch (conf->channel->band) {
  25         case IEEE80211_BAND_2GHZ:
  26                 if (conf_is_ht20(conf))
  27                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  28                 else if (conf_is_ht40_minus(conf))
  29                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  30                 else if (conf_is_ht40_plus(conf))
  31                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  32                 else
  33                         sc->cur_rate_mode = ATH9K_MODE_11G;
  34                 break;
  35         case IEEE80211_BAND_5GHZ:
  36                 if (conf_is_ht20(conf))
  37                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  38                 else if (conf_is_ht40_minus(conf))
  39                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  40                 else if (conf_is_ht40_plus(conf))
  41                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  42                 else
  43                         sc->cur_rate_mode = ATH9K_MODE_11A;
  44                 break;
  45         default:
  46                 BUG_ON(1);
  47                 break;
  48         }
  49 }
  50
  51 static void ath_update_txpow(struct ath_softc *sc)
  52 {
  53         struct ath_hw *ah = sc->sc_ah;
  54
  55         if (sc->curtxpow != sc->config.txpowlimit) {
  56                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  57                 /* read back in case value is clamped */
  58                 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  59         }
  60 }
  61
  62 static u8 parse_mpdudensity(u8 mpdudensity)
  63 {
  64         /*
  65          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  66          *   0 for no restriction
  67          *   1 for 1/4 us
  68          *   2 for 1/2 us
  69          *   3 for 1 us
  70          *   4 for 2 us
  71          *   5 for 4 us
  72          *   6 for 8 us
  73          *   7 for 16 us
  74          */
  75         switch (mpdudensity) {
  76         case 0:
  77                 return 0;
  78         case 1:
  79         case 2:
  80         case 3:
  81                 /* Our lower layer calculations limit our precision to
  82                    1 microsecond */
  83                 return 1;
  84         case 4:
  85                 return 2;
  86         case 5:
  87                 return 4;
  88         case 6:
  89                 return 8;
  90         case 7:
  91                 return 16;
  92         default:
  93                 return 0;
  94         }
  95 }
  96
  97 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  98                                                 struct ieee80211_hw *hw)
  99 {
 100         struct ieee80211_channel *curchan = hw->conf.channel;
 101         struct ath9k_channel *channel;
 102         u8 chan_idx;
 103
 104         chan_idx = curchan->hw_value;
 105         channel = &sc->sc_ah->channels[chan_idx];
 106         ath9k_update_ichannel(sc, hw, channel);
 107         return channel;
 108 }
 109
 110 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 111 {
 112         unsigned long flags;
 113         bool ret;
 114
 115         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 116         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 117         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 118
 119         return ret;
 120 }
 121
 122 void ath9k_ps_wakeup(struct ath_softc *sc)
 123 {
 124         unsigned long flags;
 125
 126         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 127         if (++sc->ps_usecount != 1)
 128                 goto unlock;
 129
 130         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 131
 132  unlock:
 133         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 134 }
 135
 136 void ath9k_ps_restore(struct ath_softc *sc)
 137 {
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 141         if (--sc->ps_usecount != 0)
 142                 goto unlock;
 143
 144         if (sc->ps_idle)
 145                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 146         else if (sc->ps_enabled &&
 147                  !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 148                               PS_WAIT_FOR_CAB |
 149                               PS_WAIT_FOR_PSPOLL_DATA |
 150                               PS_WAIT_FOR_TX_ACK)))
 151                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 152
 153  unlock:
 154         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 155 }
 156
 157 static void ath_start_ani(struct ath_common *common)
 158 {
 159         struct ath_hw *ah = common->ah;
 160         unsigned long timestamp = jiffies_to_msecs(jiffies);
 161         struct ath_softc *sc = (struct ath_softc *) common->priv;
 162
 163         if (!(sc->sc_flags & SC_OP_ANI_RUN))
 164                 return;
 165
 166         if (sc->sc_flags & SC_OP_OFFCHANNEL)
 167                 return;
 168
 169         common->ani.longcal_timer = timestamp;
 170         common->ani.shortcal_timer = timestamp;
 171         common->ani.checkani_timer = timestamp;
 172
 173         mod_timer(&common->ani.timer,
 174                   jiffies +
 175                         msecs_to_jiffies((u32)ah->config.ani_poll_interval));
 176 }
 177
 178 /*
 179  * Set/change channels.  If the channel is really being changed, it's done
 180  * by reseting the chip.  To accomplish this we must first cleanup any pending
 181  * DMA, then restart stuff.
 182 */
 183 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 184                     struct ath9k_channel *hchan)
 185 {
 186         struct ath_wiphy *aphy = hw->priv;
 187         struct ath_hw *ah = sc->sc_ah;
 188         struct ath_common *common = ath9k_hw_common(ah);
 189         struct ieee80211_conf *conf = &common->hw->conf;
 190         bool fastcc = true, stopped;
 191         struct ieee80211_channel *channel = hw->conf.channel;
 192         struct ath9k_hw_cal_data *caldata = NULL;
 193         int r;
 194
 195         if (sc->sc_flags & SC_OP_INVALID)
 196                 return -EIO;
 197
 198         del_timer_sync(&common->ani.timer);
 199         cancel_work_sync(&sc->paprd_work);
 200         cancel_work_sync(&sc->hw_check_work);
 201         cancel_delayed_work_sync(&sc->tx_complete_work);
 202
 203         ath9k_ps_wakeup(sc);
 204
 205         /*
 206          * This is only performed if the channel settings have
 207          * actually changed.
 208          *
 209          * To switch channels clear any pending DMA operations;
 210          * wait long enough for the RX fifo to drain, reset the
 211          * hardware at the new frequency, and then re-enable
 212          * the relevant bits of the h/w.
 213          */
 214         ath9k_hw_set_interrupts(ah, 0);
 215         ath_drain_all_txq(sc, false);
 216         stopped = ath_stoprecv(sc);
 217
 218         /* XXX: do not flush receive queue here. We don't want
 219          * to flush data frames already in queue because of
 220          * changing channel. */
 221
 222         if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
 223                 fastcc = false;
 224
 225         if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
 226                 caldata = &aphy->caldata;
 227
 228         ath_print(common, ATH_DBG_CONFIG,
 229                   "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
 230                   sc->sc_ah->curchan->channel,
 231                   channel->center_freq, conf_is_ht40(conf),
 232                   fastcc);
 233
 234         spin_lock_bh(&sc->sc_resetlock);
 235
 236         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 237         if (r) {
 238                 ath_print(common, ATH_DBG_FATAL,
 239                           "Unable to reset channel (%u MHz), "
 240                           "reset status %d\n",
 241                           channel->center_freq, r);
 242                 spin_unlock_bh(&sc->sc_resetlock);
 243                 goto ps_restore;
 244         }
 245         spin_unlock_bh(&sc->sc_resetlock);
 246
 247         if (ath_startrecv(sc) != 0) {
 248                 ath_print(common, ATH_DBG_FATAL,
 249                           "Unable to restart recv logic\n");
 250                 r = -EIO;
 251                 goto ps_restore;
 252         }
 253
 254         ath_cache_conf_rate(sc, &hw->conf);
 255         ath_update_txpow(sc);
 256         ath9k_hw_set_interrupts(ah, ah->imask);
 257
 258         if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
 259                 ath_beacon_config(sc, NULL);
 260                 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
 261                 ath_start_ani(common);
 262         }
 263
 264  ps_restore:
 265         ath9k_ps_restore(sc);
 266         return r;
 267 }
 268
 269 static void ath_paprd_activate(struct ath_softc *sc)
 270 {
 271         struct ath_hw *ah = sc->sc_ah;
 272         struct ath9k_hw_cal_data *caldata = ah->caldata;
 273         struct ath_common *common = ath9k_hw_common(ah);
 274         int chain;
 275
 276         if (!caldata || !caldata->paprd_done)
 277                 return;
 278
 279         ath9k_ps_wakeup(sc);
 280         ar9003_paprd_enable(ah, false);
 281         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
 282                 if (!(common->tx_chainmask & BIT(chain)))
 283                         continue;
 284
 285                 ar9003_paprd_populate_single_table(ah, caldata, chain);
 286         }
 287
 288         ar9003_paprd_enable(ah, true);
 289         ath9k_ps_restore(sc);
 290 }
 291
 292 void ath_paprd_calibrate(struct work_struct *work)
 293 {
 294         struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
 295         struct ieee80211_hw *hw = sc->hw;
 296         struct ath_hw *ah = sc->sc_ah;
 297         struct ieee80211_hdr *hdr;
 298         struct sk_buff *skb = NULL;
 299         struct ieee80211_tx_info *tx_info;
 300         int band = hw->conf.channel->band;
 301         struct ieee80211_supported_band *sband = &sc->sbands[band];
 302         struct ath_tx_control txctl;
 303         struct ath9k_hw_cal_data *caldata = ah->caldata;
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         int qnum, ftype;
 306         int chain_ok = 0;
 307         int chain;
 308         int len = 1800;
 309         int time_left;
 310         int i;
 311
 312         if (!caldata)
 313                 return;
 314
 315         skb = alloc_skb(len, GFP_KERNEL);
 316         if (!skb)
 317                 return;
 318
 319         tx_info = IEEE80211_SKB_CB(skb);
 320
 321         skb_put(skb, len);
 322         memset(skb->data, 0, len);
 323         hdr = (struct ieee80211_hdr *)skb->data;
 324         ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
 325         hdr->frame_control = cpu_to_le16(ftype);
 326         hdr->duration_id = cpu_to_le16(10);
 327         memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
 328         memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
 329         memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
 330
 331         memset(&txctl, 0, sizeof(txctl));
 332         qnum = sc->tx.hwq_map[WME_AC_BE];
 333         txctl.txq = &sc->tx.txq[qnum];
 334
 335         ath9k_ps_wakeup(sc);
 336         ar9003_paprd_init_table(ah);
 337         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
 338                 if (!(common->tx_chainmask & BIT(chain)))
 339                         continue;
 340
 341                 chain_ok = 0;
 342                 memset(tx_info, 0, sizeof(*tx_info));
 343                 tx_info->band = band;
 344
 345                 for (i = 0; i < 4; i++) {
 346                         tx_info->control.rates[i].idx = sband->n_bitrates - 1;
 347                         tx_info->control.rates[i].count = 6;
 348                 }
 349
 350                 init_completion(&sc->paprd_complete);
 351                 ar9003_paprd_setup_gain_table(ah, chain);
 352                 txctl.paprd = BIT(chain);
 353                 if (ath_tx_start(hw, skb, &txctl) != 0)
 354                         break;
 355
 356                 time_left = wait_for_completion_timeout(&sc->paprd_complete,
 357                                 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
 358                 if (!time_left) {
 359                         ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 360                                   "Timeout waiting for paprd training on "
 361                                   "TX chain %d\n",
 362                                   chain);
 363                         goto fail_paprd;
 364                 }
 365
 366                 if (!ar9003_paprd_is_done(ah))
 367                         break;
 368
 369                 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
 370                         break;
 371
 372                 chain_ok = 1;
 373         }
 374         kfree_skb(skb);
 375
 376         if (chain_ok) {
 377                 caldata->paprd_done = true;
 378                 ath_paprd_activate(sc);
 379         }
 380
 381 fail_paprd:
 382         ath9k_ps_restore(sc);
 383 }
 384
 385 /*
 386  *  This routine performs the periodic noise floor calibration function
 387  *  that is used to adjust and optimize the chip performance.  This
 388  *  takes environmental changes (location, temperature) into account.
 389  *  When the task is complete, it reschedules itself depending on the
 390  *  appropriate interval that was calculated.
 391  */
 392 void ath_ani_calibrate(unsigned long data)
 393 {
 394         struct ath_softc *sc = (struct ath_softc *)data;
 395         struct ath_hw *ah = sc->sc_ah;
 396         struct ath_common *common = ath9k_hw_common(ah);
 397         bool longcal = false;
 398         bool shortcal = false;
 399         bool aniflag = false;
 400         unsigned int timestamp = jiffies_to_msecs(jiffies);
 401         u32 cal_interval, short_cal_interval, long_cal_interval;
 402
 403         if (ah->caldata && ah->caldata->nfcal_interference)
 404                 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
 405         else
 406                 long_cal_interval = ATH_LONG_CALINTERVAL;
 407
 408         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 409                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 410
 411         /* Only calibrate if awake */
 412         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 413                 goto set_timer;
 414
 415         ath9k_ps_wakeup(sc);
 416
 417         /* Long calibration runs independently of short calibration. */
 418         if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
 419                 longcal = true;
 420                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 421                 common->ani.longcal_timer = timestamp;
 422         }
 423
 424         /* Short calibration applies only while caldone is false */
 425         if (!common->ani.caldone) {
 426                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
 427                         shortcal = true;
 428                         ath_print(common, ATH_DBG_ANI,
 429                                   "shortcal @%lu\n", jiffies);
 430                         common->ani.shortcal_timer = timestamp;
 431                         common->ani.resetcal_timer = timestamp;
 432                 }
 433         } else {
 434                 if ((timestamp - common->ani.resetcal_timer) >=
 435                     ATH_RESTART_CALINTERVAL) {
 436                         common->ani.caldone = ath9k_hw_reset_calvalid(ah);
 437                         if (common->ani.caldone)
 438                                 common->ani.resetcal_timer = timestamp;
 439                 }
 440         }
 441
 442         /* Verify whether we must check ANI */
 443         if ((timestamp - common->ani.checkani_timer) >=
 444              ah->config.ani_poll_interval) {
 445                 aniflag = true;
 446                 common->ani.checkani_timer = timestamp;
 447         }
 448
 449         /* Skip all processing if there's nothing to do. */
 450         if (longcal || shortcal || aniflag) {
 451                 /* Call ANI routine if necessary */
 452                 if (aniflag)
 453                         ath9k_hw_ani_monitor(ah, ah->curchan);
 454
 455                 /* Perform calibration if necessary */
 456                 if (longcal || shortcal) {
 457                         common->ani.caldone =
 458                                 ath9k_hw_calibrate(ah,
 459                                                    ah->curchan,
 460                                                    common->rx_chainmask,
 461                                                    longcal);
 462                 }
 463         }
 464
 465         ath9k_ps_restore(sc);
 466
 467 set_timer:
 468         /*
 469         * Set timer interval based on previous results.
 470         * The interval must be the shortest necessary to satisfy ANI,
 471         * short calibration and long calibration.
 472         */
 473         cal_interval = ATH_LONG_CALINTERVAL;
 474         if (sc->sc_ah->config.enable_ani)
 475                 cal_interval = min(cal_interval,
 476                                    (u32)ah->config.ani_poll_interval);
 477         if (!common->ani.caldone)
 478                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 479
 480         mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 481         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
 482                 if (!ah->caldata->paprd_done)
 483                         ieee80211_queue_work(sc->hw, &sc->paprd_work);
 484                 else
 485                         ath_paprd_activate(sc);
 486         }
 487 }
 488
 489 /*
 490  * Update tx/rx chainmask. For legacy association,
 491  * hard code chainmask to 1x1, for 11n association, use
 492  * the chainmask configuration, for bt coexistence, use
 493  * the chainmask configuration even in legacy mode.
 494  */
 495 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 496 {
 497         struct ath_hw *ah = sc->sc_ah;
 498         struct ath_common *common = ath9k_hw_common(ah);
 499
 500         if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
 501             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 502                 common->tx_chainmask = ah->caps.tx_chainmask;
 503                 common->rx_chainmask = ah->caps.rx_chainmask;
 504         } else {
 505                 common->tx_chainmask = 1;
 506                 common->rx_chainmask = 1;
 507         }
 508
 509         ath_print(common, ATH_DBG_CONFIG,
 510                   "tx chmask: %d, rx chmask: %d\n",
 511                   common->tx_chainmask,
 512                   common->rx_chainmask);
 513 }
 514
 515 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 516 {
 517         struct ath_node *an;
 518
 519         an = (struct ath_node *)sta->drv_priv;
 520
 521         if (sc->sc_flags & SC_OP_TXAGGR) {
 522                 ath_tx_node_init(sc, an);
 523                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 524                                      sta->ht_cap.ampdu_factor);
 525                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 526                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 527         }
 528 }
 529
 530 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 531 {
 532         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 533
 534         if (sc->sc_flags & SC_OP_TXAGGR)
 535                 ath_tx_node_cleanup(sc, an);
 536 }
 537
 538 void ath_hw_check(struct work_struct *work)
 539 {
 540         struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
 541         int i;
 542
 543         ath9k_ps_wakeup(sc);
 544
 545         for (i = 0; i < 3; i++) {
 546                 if (ath9k_hw_check_alive(sc->sc_ah))
 547                         goto out;
 548
 549                 msleep(1);
 550         }
 551         ath_reset(sc, false);
 552
 553 out:
 554         ath9k_ps_restore(sc);
 555 }
 556
 557 void ath9k_tasklet(unsigned long data)
 558 {
 559         struct ath_softc *sc = (struct ath_softc *)data;
 560         struct ath_hw *ah = sc->sc_ah;
 561         struct ath_common *common = ath9k_hw_common(ah);
 562
 563         u32 status = sc->intrstatus;
 564         u32 rxmask;
 565
 566         ath9k_ps_wakeup(sc);
 567
 568         if (status & ATH9K_INT_FATAL) {
 569                 ath_reset(sc, false);
 570                 ath9k_ps_restore(sc);
 571                 return;
 572         }
 573
 574         if (!ath9k_hw_check_alive(ah))
 575                 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 576
 577         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 578                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 579                           ATH9K_INT_RXORN);
 580         else
 581                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 582
 583         if (status & rxmask) {
 584                 spin_lock_bh(&sc->rx.rxflushlock);
 585
 586                 /* Check for high priority Rx first */
 587                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 588                     (status & ATH9K_INT_RXHP))
 589                         ath_rx_tasklet(sc, 0, true);
 590
 591                 ath_rx_tasklet(sc, 0, false);
 592                 spin_unlock_bh(&sc->rx.rxflushlock);
 593         }
 594
 595         if (status & ATH9K_INT_TX) {
 596                 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 597                         ath_tx_edma_tasklet(sc);
 598                 else
 599                         ath_tx_tasklet(sc);
 600         }
 601
 602         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 603                 /*
 604                  * TSF sync does not look correct; remain awake to sync with
 605                  * the next Beacon.
 606                  */
 607                 ath_print(common, ATH_DBG_PS,
 608                           "TSFOOR - Sync with next Beacon\n");
 609                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 610         }
 611
 612         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 613                 if (status & ATH9K_INT_GENTIMER)
 614                         ath_gen_timer_isr(sc->sc_ah);
 615
 616         /* re-enable hardware interrupt */
 617         ath9k_hw_set_interrupts(ah, ah->imask);
 618         ath9k_ps_restore(sc);
 619 }
 620
 621 irqreturn_t ath_isr(int irq, void *dev)
 622 {
 623 #define SCHED_INTR (                            \
 624                 ATH9K_INT_FATAL |               \
 625                 ATH9K_INT_RXORN |               \
 626                 ATH9K_INT_RXEOL |               \
 627                 ATH9K_INT_RX |                  \
 628                 ATH9K_INT_RXLP |                \
 629                 ATH9K_INT_RXHP |                \
 630                 ATH9K_INT_TX |                  \
 631                 ATH9K_INT_BMISS |               \
 632                 ATH9K_INT_CST |                 \
 633                 ATH9K_INT_TSFOOR |              \
 634                 ATH9K_INT_GENTIMER)
 635
 636         struct ath_softc *sc = dev;
 637         struct ath_hw *ah = sc->sc_ah;
 638         enum ath9k_int status;
 639         bool sched = false;
 640
 641         /*
 642          * The hardware is not ready/present, don't
 643          * touch anything. Note this can happen early
 644          * on if the IRQ is shared.
 645          */
 646         if (sc->sc_flags & SC_OP_INVALID)
 647                 return IRQ_NONE;
 648
 649
 650         /* shared irq, not for us */
 651
 652         if (!ath9k_hw_intrpend(ah))
 653                 return IRQ_NONE;
 654
 655         /*
 656          * Figure out the reason(s) for the interrupt.  Note
 657          * that the hal returns a pseudo-ISR that may include
 658          * bits we haven't explicitly enabled so we mask the
 659          * value to insure we only process bits we requested.
 660          */
 661         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 662         status &= ah->imask;    /* discard unasked-for bits */
 663
 664         /*
 665          * If there are no status bits set, then this interrupt was not
 666          * for me (should have been caught above).
 667          */
 668         if (!status)
 669                 return IRQ_NONE;
 670
 671         /* Cache the status */
 672         sc->intrstatus = status;
 673
 674         if (status & SCHED_INTR)
 675                 sched = true;
 676
 677         /*
 678          * If a FATAL or RXORN interrupt is received, we have to reset the
 679          * chip immediately.
 680          */
 681         if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
 682             !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
 683                 goto chip_reset;
 684
 685         if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 686             (status & ATH9K_INT_BB_WATCHDOG)) {
 687                 ar9003_hw_bb_watchdog_dbg_info(ah);
 688                 goto chip_reset;
 689         }
 690
 691         if (status & ATH9K_INT_SWBA)
 692                 tasklet_schedule(&sc->bcon_tasklet);
 693
 694         if (status & ATH9K_INT_TXURN)
 695                 ath9k_hw_updatetxtriglevel(ah, true);
 696
 697         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 698                 if (status & ATH9K_INT_RXEOL) {
 699                         ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 700                         ath9k_hw_set_interrupts(ah, ah->imask);
 701                 }
 702         }
 703
 704         if (status & ATH9K_INT_MIB) {
 705                 /*
 706                  * Disable interrupts until we service the MIB
 707                  * interrupt; otherwise it will continue to
 708                  * fire.
 709                  */
 710                 ath9k_hw_set_interrupts(ah, 0);
 711                 /*
 712                  * Let the hal handle the event. We assume
 713                  * it will clear whatever condition caused
 714                  * the interrupt.
 715                  */
 716                 ath9k_hw_proc_mib_event(ah);
 717                 ath9k_hw_set_interrupts(ah, ah->imask);
 718         }
 719
 720         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 721                 if (status & ATH9K_INT_TIM_TIMER) {
 722                         /* Clear RxAbort bit so that we can
 723                          * receive frames */
 724                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 725                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 726                         sc->ps_flags |= PS_WAIT_FOR_BEACON;
 727                 }
 728
 729 chip_reset:
 730
 731         ath_debug_stat_interrupt(sc, status);
 732
 733         if (sched) {
 734                 /* turn off every interrupt except SWBA */
 735                 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
 736                 tasklet_schedule(&sc->intr_tq);
 737         }
 738
 739         return IRQ_HANDLED;
 740
 741 #undef SCHED_INTR
 742 }
 743
 744 static u32 ath_get_extchanmode(struct ath_softc *sc,
 745                                struct ieee80211_channel *chan,
 746                                enum nl80211_channel_type channel_type)
 747 {
 748         u32 chanmode = 0;
 749
 750         switch (chan->band) {
 751         case IEEE80211_BAND_2GHZ:
 752                 switch(channel_type) {
 753                 case NL80211_CHAN_NO_HT:
 754                 case NL80211_CHAN_HT20:
 755                         chanmode = CHANNEL_G_HT20;
 756                         break;
 757                 case NL80211_CHAN_HT40PLUS:
 758                         chanmode = CHANNEL_G_HT40PLUS;
 759                         break;
 760                 case NL80211_CHAN_HT40MINUS:
 761                         chanmode = CHANNEL_G_HT40MINUS;
 762                         break;
 763                 }
 764                 break;
 765         case IEEE80211_BAND_5GHZ:
 766                 switch(channel_type) {
 767                 case NL80211_CHAN_NO_HT:
 768                 case NL80211_CHAN_HT20:
 769                         chanmode = CHANNEL_A_HT20;
 770                         break;
 771                 case NL80211_CHAN_HT40PLUS:
 772                         chanmode = CHANNEL_A_HT40PLUS;
 773                         break;
 774                 case NL80211_CHAN_HT40MINUS:
 775                         chanmode = CHANNEL_A_HT40MINUS;
 776                         break;
 777                 }
 778                 break;
 779         default:
 780                 break;
 781         }
 782
 783         return chanmode;
 784 }
 785
 786 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 787                                  struct ieee80211_vif *vif,
 788                                  struct ieee80211_bss_conf *bss_conf)
 789 {
 790         struct ath_hw *ah = sc->sc_ah;
 791         struct ath_common *common = ath9k_hw_common(ah);
 792
 793         if (bss_conf->assoc) {
 794                 ath_print(common, ATH_DBG_CONFIG,
 795                           "Bss Info ASSOC %d, bssid: %pM\n",
 796                            bss_conf->aid, common->curbssid);
 797
 798                 /* New association, store aid */
 799                 common->curaid = bss_conf->aid;
 800                 ath9k_hw_write_associd(ah);
 801
 802                 /*
 803                  * Request a re-configuration of Beacon related timers
 804                  * on the receipt of the first Beacon frame (i.e.,
 805                  * after time sync with the AP).
 806                  */
 807                 sc->ps_flags |= PS_BEACON_SYNC;
 808
 809                 /* Configure the beacon */
 810                 ath_beacon_config(sc, vif);
 811
 812                 /* Reset rssi stats */
 813                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
 814
 815                 sc->sc_flags |= SC_OP_ANI_RUN;
 816                 ath_start_ani(common);
 817         } else {
 818                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 819                 common->curaid = 0;
 820                 /* Stop ANI */
 821                 sc->sc_flags &= ~SC_OP_ANI_RUN;
 822                 del_timer_sync(&common->ani.timer);
 823         }
 824 }
 825
 826 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
 827 {
 828         struct ath_hw *ah = sc->sc_ah;
 829         struct ath_common *common = ath9k_hw_common(ah);
 830         struct ieee80211_channel *channel = hw->conf.channel;
 831         int r;
 832
 833         ath9k_ps_wakeup(sc);
 834         ath9k_hw_configpcipowersave(ah, 0, 0);
 835
 836         if (!ah->curchan)
 837                 ah->curchan = ath_get_curchannel(sc, sc->hw);
 838
 839         spin_lock_bh(&sc->sc_resetlock);
 840         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 841         if (r) {
 842                 ath_print(common, ATH_DBG_FATAL,
 843                           "Unable to reset channel (%u MHz), "
 844                           "reset status %d\n",
 845                           channel->center_freq, r);
 846         }
 847         spin_unlock_bh(&sc->sc_resetlock);
 848
 849         ath_update_txpow(sc);
 850         if (ath_startrecv(sc) != 0) {
 851                 ath_print(common, ATH_DBG_FATAL,
 852                           "Unable to restart recv logic\n");
 853                 return;
 854         }
 855
 856         if (sc->sc_flags & SC_OP_BEACONS)
 857                 ath_beacon_config(sc, NULL);    /* restart beacons */
 858
 859         /* Re-Enable  interrupts */
 860         ath9k_hw_set_interrupts(ah, ah->imask);
 861
 862         /* Enable LED */
 863         ath9k_hw_cfg_output(ah, ah->led_pin,
 864                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 865         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 866
 867         ieee80211_wake_queues(hw);
 868         ath9k_ps_restore(sc);
 869 }
 870
 871 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
 872 {
 873         struct ath_hw *ah = sc->sc_ah;
 874         struct ieee80211_channel *channel = hw->conf.channel;
 875         int r;
 876
 877         ath9k_ps_wakeup(sc);
 878         ieee80211_stop_queues(hw);
 879
 880         /*
 881          * Keep the LED on when the radio is disabled
 882          * during idle unassociated state.
 883          */
 884         if (!sc->ps_idle) {
 885                 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
 886                 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
 887         }
 888
 889         /* Disable interrupts */
 890         ath9k_hw_set_interrupts(ah, 0);
 891
 892         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
 893         ath_stoprecv(sc);               /* turn off frame recv */
 894         ath_flushrecv(sc);              /* flush recv queue */
 895
 896         if (!ah->curchan)
 897                 ah->curchan = ath_get_curchannel(sc, hw);
 898
 899         spin_lock_bh(&sc->sc_resetlock);
 900         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 901         if (r) {
 902                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
 903                           "Unable to reset channel (%u MHz), "
 904                           "reset status %d\n",
 905                           channel->center_freq, r);
 906         }
 907         spin_unlock_bh(&sc->sc_resetlock);
 908
 909         ath9k_hw_phy_disable(ah);
 910         ath9k_hw_configpcipowersave(ah, 1, 1);
 911         ath9k_ps_restore(sc);
 912         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
 913 }
 914
 915 int ath_reset(struct ath_softc *sc, bool retry_tx)
 916 {
 917         struct ath_hw *ah = sc->sc_ah;
 918         struct ath_common *common = ath9k_hw_common(ah);
 919         struct ieee80211_hw *hw = sc->hw;
 920         int r;
 921
 922         /* Stop ANI */
 923         del_timer_sync(&common->ani.timer);
 924
 925         ieee80211_stop_queues(hw);
 926
 927         ath9k_hw_set_interrupts(ah, 0);
 928         ath_drain_all_txq(sc, retry_tx);
 929         ath_stoprecv(sc);
 930         ath_flushrecv(sc);
 931
 932         spin_lock_bh(&sc->sc_resetlock);
 933         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
 934         if (r)
 935                 ath_print(common, ATH_DBG_FATAL,
 936                           "Unable to reset hardware; reset status %d\n", r);
 937         spin_unlock_bh(&sc->sc_resetlock);
 938
 939         if (ath_startrecv(sc) != 0)
 940                 ath_print(common, ATH_DBG_FATAL,
 941                           "Unable to start recv logic\n");
 942
 943         /*
 944          * We may be doing a reset in response to a request
 945          * that changes the channel so update any state that
 946          * might change as a result.
 947          */
 948         ath_cache_conf_rate(sc, &hw->conf);
 949
 950         ath_update_txpow(sc);
 951
 952         if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
 953                 ath_beacon_config(sc, NULL);    /* restart beacons */
 954
 955         ath9k_hw_set_interrupts(ah, ah->imask);
 956
 957         if (retry_tx) {
 958                 int i;
 959                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 960                         if (ATH_TXQ_SETUP(sc, i)) {
 961                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
 962                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
 963                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
 964                         }
 965                 }
 966         }
 967
 968         ieee80211_wake_queues(hw);
 969
 970         /* Start ANI */
 971         ath_start_ani(common);
 972
 973         return r;
 974 }
 975
 976 static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 977 {
 978         int qnum;
 979
 980         switch (queue) {
 981         case 0:
 982                 qnum = sc->tx.hwq_map[WME_AC_VO];
 983                 break;
 984         case 1:
 985                 qnum = sc->tx.hwq_map[WME_AC_VI];
 986                 break;
 987         case 2:
 988                 qnum = sc->tx.hwq_map[WME_AC_BE];
 989                 break;
 990         case 3:
 991                 qnum = sc->tx.hwq_map[WME_AC_BK];
 992                 break;
 993         default:
 994                 qnum = sc->tx.hwq_map[WME_AC_BE];
 995                 break;
 996         }
 997
 998         return qnum;
 999 }
1000
1001 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1002 {
1003         int qnum;
1004
1005         switch (queue) {
1006         case WME_AC_VO:
1007                 qnum = 0;
1008                 break;
1009         case WME_AC_VI:
1010                 qnum = 1;
1011                 break;
1012         case WME_AC_BE:
1013                 qnum = 2;
1014                 break;
1015         case WME_AC_BK:
1016                 qnum = 3;
1017                 break;
1018         default:
1019                 qnum = -1;
1020                 break;
1021         }
1022
1023         return qnum;
1024 }
1025
1026 /* XXX: Remove me once we don't depend on ath9k_channel for all
1027  * this redundant data */
1028 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1029                            struct ath9k_channel *ichan)
1030 {
1031         struct ieee80211_channel *chan = hw->conf.channel;
1032         struct ieee80211_conf *conf = &hw->conf;
1033
1034         ichan->channel = chan->center_freq;
1035         ichan->chan = chan;
1036
1037         if (chan->band == IEEE80211_BAND_2GHZ) {
1038                 ichan->chanmode = CHANNEL_G;
1039                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
1040         } else {
1041                 ichan->chanmode = CHANNEL_A;
1042                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1043         }
1044
1045         if (conf_is_ht(conf))
1046                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1047                                             conf->channel_type);
1048 }
1049
1050 /**********************/
1051 /* mac80211 callbacks */
1052 /**********************/
1053
1054 static int ath9k_start(struct ieee80211_hw *hw)
1055 {
1056         struct ath_wiphy *aphy = hw->priv;
1057         struct ath_softc *sc = aphy->sc;
1058         struct ath_hw *ah = sc->sc_ah;
1059         struct ath_common *common = ath9k_hw_common(ah);
1060         struct ieee80211_channel *curchan = hw->conf.channel;
1061         struct ath9k_channel *init_channel;
1062         int r;
1063
1064         ath_print(common, ATH_DBG_CONFIG,
1065                   "Starting driver with initial channel: %d MHz\n",
1066                   curchan->center_freq);
1067
1068         mutex_lock(&sc->mutex);
1069
1070         if (ath9k_wiphy_started(sc)) {
1071                 if (sc->chan_idx == curchan->hw_value) {
1072                         /*
1073                          * Already on the operational channel, the new wiphy
1074                          * can be marked active.
1075                          */
1076                         aphy->state = ATH_WIPHY_ACTIVE;
1077                         ieee80211_wake_queues(hw);
1078                 } else {
1079                         /*
1080                          * Another wiphy is on another channel, start the new
1081                          * wiphy in paused state.
1082                          */
1083                         aphy->state = ATH_WIPHY_PAUSED;
1084                         ieee80211_stop_queues(hw);
1085                 }
1086                 mutex_unlock(&sc->mutex);
1087                 return 0;
1088         }
1089         aphy->state = ATH_WIPHY_ACTIVE;
1090
1091         /* setup initial channel */
1092
1093         sc->chan_idx = curchan->hw_value;
1094
1095         init_channel = ath_get_curchannel(sc, hw);
1096
1097         /* Reset SERDES registers */
1098         ath9k_hw_configpcipowersave(ah, 0, 0);
1099
1100         /*
1101          * The basic interface to setting the hardware in a good
1102          * state is ``reset''.  On return the hardware is known to
1103          * be powered up and with interrupts disabled.  This must
1104          * be followed by initialization of the appropriate bits
1105          * and then setup of the interrupt mask.
1106          */
1107         spin_lock_bh(&sc->sc_resetlock);
1108         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1109         if (r) {
1110                 ath_print(common, ATH_DBG_FATAL,
1111                           "Unable to reset hardware; reset status %d "
1112                           "(freq %u MHz)\n", r,
1113                           curchan->center_freq);
1114                 spin_unlock_bh(&sc->sc_resetlock);
1115                 goto mutex_unlock;
1116         }
1117         spin_unlock_bh(&sc->sc_resetlock);
1118
1119         /*
1120          * This is needed only to setup initial state
1121          * but it's best done after a reset.
1122          */
1123         ath_update_txpow(sc);
1124
1125         /*
1126          * Setup the hardware after reset:
1127          * The receive engine is set going.
1128          * Frame transmit is handled entirely
1129          * in the frame output path; there's nothing to do
1130          * here except setup the interrupt mask.
1131          */
1132         if (ath_startrecv(sc) != 0) {
1133                 ath_print(common, ATH_DBG_FATAL,
1134                           "Unable to start recv logic\n");
1135                 r = -EIO;
1136                 goto mutex_unlock;
1137         }
1138
1139         /* Setup our intr mask. */
1140         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1141                     ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1142                     ATH9K_INT_GLOBAL;
1143
1144         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1145                 ah->imask |= ATH9K_INT_RXHP |
1146                              ATH9K_INT_RXLP |
1147                              ATH9K_INT_BB_WATCHDOG;
1148         else
1149                 ah->imask |= ATH9K_INT_RX;
1150
1151         ah->imask |= ATH9K_INT_GTT;
1152
1153         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1154                 ah->imask |= ATH9K_INT_CST;
1155
1156         ath_cache_conf_rate(sc, &hw->conf);
1157
1158         sc->sc_flags &= ~SC_OP_INVALID;
1159
1160         /* Disable BMISS interrupt when we're not associated */
1161         ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1162         ath9k_hw_set_interrupts(ah, ah->imask);
1163
1164         ieee80211_wake_queues(hw);
1165
1166         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1167
1168         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1169             !ah->btcoex_hw.enabled) {
1170                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1171                                            AR_STOMP_LOW_WLAN_WGHT);
1172                 ath9k_hw_btcoex_enable(ah);
1173
1174                 if (common->bus_ops->bt_coex_prep)
1175                         common->bus_ops->bt_coex_prep(common);
1176                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1177                         ath9k_btcoex_timer_resume(sc);
1178         }
1179
1180 mutex_unlock:
1181         mutex_unlock(&sc->mutex);
1182
1183         return r;
1184 }
1185
1186 static int ath9k_tx(struct ieee80211_hw *hw,
1187                     struct sk_buff *skb)
1188 {
1189         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1190         struct ath_wiphy *aphy = hw->priv;
1191         struct ath_softc *sc = aphy->sc;
1192         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1193         struct ath_tx_control txctl;
1194         int padpos, padsize;
1195         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1196         int qnum;
1197
1198         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1199                 ath_print(common, ATH_DBG_XMIT,
1200                           "ath9k: %s: TX in unexpected wiphy state "
1201                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
1202                 goto exit;
1203         }
1204
1205         if (sc->ps_enabled) {
1206                 /*
1207                  * mac80211 does not set PM field for normal data frames, so we
1208                  * need to update that based on the current PS mode.
1209                  */
1210                 if (ieee80211_is_data(hdr->frame_control) &&
1211                     !ieee80211_is_nullfunc(hdr->frame_control) &&
1212                     !ieee80211_has_pm(hdr->frame_control)) {
1213                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1214                                   "while in PS mode\n");
1215                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1216                 }
1217         }
1218
1219         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1220                 /*
1221                  * We are using PS-Poll and mac80211 can request TX while in
1222                  * power save mode. Need to wake up hardware for the TX to be
1223                  * completed and if needed, also for RX of buffered frames.
1224                  */
1225                 ath9k_ps_wakeup(sc);
1226                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1227                         ath9k_hw_setrxabort(sc->sc_ah, 0);
1228                 if (ieee80211_is_pspoll(hdr->frame_control)) {
1229                         ath_print(common, ATH_DBG_PS,
1230                                   "Sending PS-Poll to pick a buffered frame\n");
1231                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1232                 } else {
1233                         ath_print(common, ATH_DBG_PS,
1234                                   "Wake up to complete TX\n");
1235                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1236                 }
1237                 /*
1238                  * The actual restore operation will happen only after
1239                  * the sc_flags bit is cleared. We are just dropping
1240                  * the ps_usecount here.
1241                  */
1242                 ath9k_ps_restore(sc);
1243         }
1244
1245         memset(&txctl, 0, sizeof(struct ath_tx_control));
1246
1247         /*
1248          * As a temporary workaround, assign seq# here; this will likely need
1249          * to be cleaned up to work better with Beacon transmission and virtual
1250          * BSSes.
1251          */
1252         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1253                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1254                         sc->tx.seq_no += 0x10;
1255                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1256                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1257         }
1258
1259         /* Add the padding after the header if this is not already done */
1260         padpos = ath9k_cmn_padpos(hdr->frame_control);
1261         padsize = padpos & 3;
1262         if (padsize && skb->len>padpos) {
1263                 if (skb_headroom(skb) < padsize)
1264                         return -1;
1265                 skb_push(skb, padsize);
1266                 memmove(skb->data, skb->data + padsize, padpos);
1267         }
1268
1269         qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1270         txctl.txq = &sc->tx.txq[qnum];
1271
1272         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1273
1274         if (ath_tx_start(hw, skb, &txctl) != 0) {
1275                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
1276                 goto exit;
1277         }
1278
1279         return 0;
1280 exit:
1281         dev_kfree_skb_any(skb);
1282         return 0;
1283 }
1284
1285 static void ath9k_stop(struct ieee80211_hw *hw)
1286 {
1287         struct ath_wiphy *aphy = hw->priv;
1288         struct ath_softc *sc = aphy->sc;
1289         struct ath_hw *ah = sc->sc_ah;
1290         struct ath_common *common = ath9k_hw_common(ah);
1291         int i;
1292
1293         mutex_lock(&sc->mutex);
1294
1295         aphy->state = ATH_WIPHY_INACTIVE;
1296
1297         if (led_blink)
1298                 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1299
1300         cancel_delayed_work_sync(&sc->tx_complete_work);
1301         cancel_work_sync(&sc->paprd_work);
1302         cancel_work_sync(&sc->hw_check_work);
1303
1304         for (i = 0; i < sc->num_sec_wiphy; i++) {
1305                 if (sc->sec_wiphy[i])
1306                         break;
1307         }
1308
1309         if (i == sc->num_sec_wiphy) {
1310                 cancel_delayed_work_sync(&sc->wiphy_work);
1311                 cancel_work_sync(&sc->chan_work);
1312         }
1313
1314         if (sc->sc_flags & SC_OP_INVALID) {
1315                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
1316                 mutex_unlock(&sc->mutex);
1317                 return;
1318         }
1319
1320         if (ath9k_wiphy_started(sc)) {
1321                 mutex_unlock(&sc->mutex);
1322                 return; /* another wiphy still in use */
1323         }
1324
1325         /* Ensure HW is awake when we try to shut it down. */
1326         ath9k_ps_wakeup(sc);
1327
1328         if (ah->btcoex_hw.enabled) {
1329                 ath9k_hw_btcoex_disable(ah);
1330                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1331                         ath9k_btcoex_timer_pause(sc);
1332         }
1333
1334         /* make sure h/w will not generate any interrupt
1335          * before setting the invalid flag. */
1336         ath9k_hw_set_interrupts(ah, 0);
1337
1338         if (!(sc->sc_flags & SC_OP_INVALID)) {
1339                 ath_drain_all_txq(sc, false);
1340                 ath_stoprecv(sc);
1341                 ath9k_hw_phy_disable(ah);
1342         } else
1343                 sc->rx.rxlink = NULL;
1344
1345         /* disable HAL and put h/w to sleep */
1346         ath9k_hw_disable(ah);
1347         ath9k_hw_configpcipowersave(ah, 1, 1);
1348         ath9k_ps_restore(sc);
1349
1350         /* Finally, put the chip in FULL SLEEP mode */
1351         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1352
1353         sc->sc_flags |= SC_OP_INVALID;
1354
1355         mutex_unlock(&sc->mutex);
1356
1357         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
1358 }
1359
1360 static int ath9k_add_interface(struct ieee80211_hw *hw,
1361                                struct ieee80211_vif *vif)
1362 {
1363         struct ath_wiphy *aphy = hw->priv;
1364         struct ath_softc *sc = aphy->sc;
1365         struct ath_hw *ah = sc->sc_ah;
1366         struct ath_common *common = ath9k_hw_common(ah);
1367         struct ath_vif *avp = (void *)vif->drv_priv;
1368         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
1369         int ret = 0;
1370
1371         mutex_lock(&sc->mutex);
1372
1373         switch (vif->type) {
1374         case NL80211_IFTYPE_STATION:
1375                 ic_opmode = NL80211_IFTYPE_STATION;
1376                 break;
1377         case NL80211_IFTYPE_WDS:
1378                 ic_opmode = NL80211_IFTYPE_WDS;
1379                 break;
1380         case NL80211_IFTYPE_ADHOC:
1381         case NL80211_IFTYPE_AP:
1382         case NL80211_IFTYPE_MESH_POINT:
1383                 if (sc->nbcnvifs >= ATH_BCBUF) {
1384                         ret = -ENOBUFS;
1385                         goto out;
1386                 }
1387                 ic_opmode = vif->type;
1388                 break;
1389         default:
1390                 ath_print(common, ATH_DBG_FATAL,
1391                         "Interface type %d not yet supported\n", vif->type);
1392                 ret = -EOPNOTSUPP;
1393                 goto out;
1394         }
1395
1396         ath_print(common, ATH_DBG_CONFIG,
1397                   "Attach a VIF of type: %d\n", ic_opmode);
1398
1399         /* Set the VIF opmode */
1400         avp->av_opmode = ic_opmode;
1401         avp->av_bslot = -1;
1402
1403         sc->nvifs++;
1404
1405         ath9k_set_bssid_mask(hw, vif);
1406
1407         if (sc->nvifs > 1)
1408                 goto out; /* skip global settings for secondary vif */
1409
1410         if (ic_opmode == NL80211_IFTYPE_AP) {
1411                 ath9k_hw_set_tsfadjust(ah, 1);
1412                 sc->sc_flags |= SC_OP_TSF_RESET;
1413         }
1414
1415         /* Set the device opmode */
1416         ah->opmode = ic_opmode;
1417
1418         /*
1419          * Enable MIB interrupts when there are hardware phy counters.
1420          * Note we only do this (at the moment) for station mode.
1421          */
1422         if ((vif->type == NL80211_IFTYPE_STATION) ||
1423             (vif->type == NL80211_IFTYPE_ADHOC) ||
1424             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1425                 if (ah->config.enable_ani)
1426                         ah->imask |= ATH9K_INT_MIB;
1427                 ah->imask |= ATH9K_INT_TSFOOR;
1428         }
1429
1430         ath9k_hw_set_interrupts(ah, ah->imask);
1431
1432         if (vif->type == NL80211_IFTYPE_AP    ||
1433             vif->type == NL80211_IFTYPE_ADHOC ||
1434             vif->type == NL80211_IFTYPE_MONITOR) {
1435                 sc->sc_flags |= SC_OP_ANI_RUN;
1436                 ath_start_ani(common);
1437         }
1438
1439 out:
1440         mutex_unlock(&sc->mutex);
1441         return ret;
1442 }
1443
1444 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1445                                    struct ieee80211_vif *vif)
1446 {
1447         struct ath_wiphy *aphy = hw->priv;
1448         struct ath_softc *sc = aphy->sc;
1449         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1450         struct ath_vif *avp = (void *)vif->drv_priv;
1451         int i;
1452
1453         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
1454
1455         mutex_lock(&sc->mutex);
1456
1457         /* Stop ANI */
1458         sc->sc_flags &= ~SC_OP_ANI_RUN;
1459         del_timer_sync(&common->ani.timer);
1460
1461         /* Reclaim beacon resources */
1462         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1463             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1464             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
1465                 ath9k_ps_wakeup(sc);
1466                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1467                 ath9k_ps_restore(sc);
1468         }
1469
1470         ath_beacon_return(sc, avp);
1471         sc->sc_flags &= ~SC_OP_BEACONS;
1472
1473         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1474                 if (sc->beacon.bslot[i] == vif) {
1475                         printk(KERN_DEBUG "%s: vif had allocated beacon "
1476                                "slot\n", __func__);
1477                         sc->beacon.bslot[i] = NULL;
1478                         sc->beacon.bslot_aphy[i] = NULL;
1479                 }
1480         }
1481
1482         sc->nvifs--;
1483
1484         mutex_unlock(&sc->mutex);
1485 }
1486
1487 static void ath9k_enable_ps(struct ath_softc *sc)
1488 {
1489         struct ath_hw *ah = sc->sc_ah;
1490
1491         sc->ps_enabled = true;
1492         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1493                 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1494                         ah->imask |= ATH9K_INT_TIM_TIMER;
1495                         ath9k_hw_set_interrupts(ah, ah->imask);
1496                 }
1497                 ath9k_hw_setrxabort(ah, 1);
1498         }
1499 }
1500
1501 static void ath9k_disable_ps(struct ath_softc *sc)
1502 {
1503         struct ath_hw *ah = sc->sc_ah;
1504
1505         sc->ps_enabled = false;
1506         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1507         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1508                 ath9k_hw_setrxabort(ah, 0);
1509                 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1510                                   PS_WAIT_FOR_CAB |
1511                                   PS_WAIT_FOR_PSPOLL_DATA |
1512                                   PS_WAIT_FOR_TX_ACK);
1513                 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1514                         ah->imask &= ~ATH9K_INT_TIM_TIMER;
1515                         ath9k_hw_set_interrupts(ah, ah->imask);
1516                 }
1517         }
1518
1519 }
1520
1521 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1522 {
1523         struct ath_wiphy *aphy = hw->priv;
1524         struct ath_softc *sc = aphy->sc;
1525         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1526         struct ieee80211_conf *conf = &hw->conf;
1527         bool disable_radio;
1528
1529         mutex_lock(&sc->mutex);
1530
1531         /*
1532          * Leave this as the first check because we need to turn on the
1533          * radio if it was disabled before prior to processing the rest
1534          * of the changes. Likewise we must only disable the radio towards
1535          * the end.
1536          */
1537         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1538                 bool enable_radio;
1539                 bool all_wiphys_idle;
1540                 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1541
1542                 spin_lock_bh(&sc->wiphy_lock);
1543                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
1544                 ath9k_set_wiphy_idle(aphy, idle);
1545
1546                 enable_radio = (!idle && all_wiphys_idle);
1547
1548                 /*
1549                  * After we unlock here its possible another wiphy
1550                  * can be re-renabled so to account for that we will
1551                  * only disable the radio toward the end of this routine
1552                  * if by then all wiphys are still idle.
1553                  */
1554                 spin_unlock_bh(&sc->wiphy_lock);
1555
1556                 if (enable_radio) {
1557                         sc->ps_idle = false;
1558                         ath_radio_enable(sc, hw);
1559                         ath_print(common, ATH_DBG_CONFIG,
1560                                   "not-idle: enabling radio\n");
1561                 }
1562         }
1563
1564         /*
1565          * We just prepare to enable PS. We have to wait until our AP has
1566          * ACK'd our null data frame to disable RX otherwise we'll ignore
1567          * those ACKs and end up retransmitting the same null data frames.
1568          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1569          */
1570         if (changed & IEEE80211_CONF_CHANGE_PS) {
1571                 unsigned long flags;
1572                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1573                 if (conf->flags & IEEE80211_CONF_PS)
1574                         ath9k_enable_ps(sc);
1575                 else
1576                         ath9k_disable_ps(sc);
1577                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1578         }
1579
1580         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1581                 if (conf->flags & IEEE80211_CONF_MONITOR) {
1582                         ath_print(common, ATH_DBG_CONFIG,
1583                                   "HW opmode set to Monitor mode\n");
1584                         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1585                 }
1586         }
1587
1588         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
1589                 struct ieee80211_channel *curchan = hw->conf.channel;
1590                 int pos = curchan->hw_value;
1591
1592                 aphy->chan_idx = pos;
1593                 aphy->chan_is_ht = conf_is_ht(conf);
1594                 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1595                         sc->sc_flags |= SC_OP_OFFCHANNEL;
1596                 else
1597                         sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1598
1599                 if (aphy->state == ATH_WIPHY_SCAN ||
1600                     aphy->state == ATH_WIPHY_ACTIVE)
1601                         ath9k_wiphy_pause_all_forced(sc, aphy);
1602                 else {
1603                         /*
1604                          * Do not change operational channel based on a paused
1605                          * wiphy changes.
1606                          */
1607                         goto skip_chan_change;
1608                 }
1609
1610                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1611                           curchan->center_freq);
1612
1613                 /* XXX: remove me eventualy */
1614                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
1615
1616                 ath_update_chainmask(sc, conf_is_ht(conf));
1617
1618                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1619                         ath_print(common, ATH_DBG_FATAL,
1620                                   "Unable to set channel\n");
1621                         mutex_unlock(&sc->mutex);
1622                         return -EINVAL;
1623                 }
1624         }
1625
1626 skip_chan_change:
1627         if (changed & IEEE80211_CONF_CHANGE_POWER) {
1628                 sc->config.txpowlimit = 2 * conf->power_level;
1629                 ath_update_txpow(sc);
1630         }
1631
1632         spin_lock_bh(&sc->wiphy_lock);
1633         disable_radio = ath9k_all_wiphys_idle(sc);
1634         spin_unlock_bh(&sc->wiphy_lock);
1635
1636         if (disable_radio) {
1637                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1638                 sc->ps_idle = true;
1639                 ath_radio_disable(sc, hw);
1640         }
1641
1642         mutex_unlock(&sc->mutex);
1643
1644         return 0;
1645 }
1646
1647 #define SUPPORTED_FILTERS                       \
1648         (FIF_PROMISC_IN_BSS |                   \
1649         FIF_ALLMULTI |                          \
1650         FIF_CONTROL |                           \
1651         FIF_PSPOLL |                            \
1652         FIF_OTHER_BSS |                         \
1653         FIF_BCN_PRBRESP_PROMISC |               \
1654         FIF_FCSFAIL)
1655
1656 /* FIXME: sc->sc_full_reset ? */
1657 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1658                                    unsigned int changed_flags,
1659                                    unsigned int *total_flags,
1660                                    u64 multicast)
1661 {
1662         struct ath_wiphy *aphy = hw->priv;
1663         struct ath_softc *sc = aphy->sc;
1664         u32 rfilt;
1665
1666         changed_flags &= SUPPORTED_FILTERS;
1667         *total_flags &= SUPPORTED_FILTERS;
1668
1669         sc->rx.rxfilter = *total_flags;
1670         ath9k_ps_wakeup(sc);
1671         rfilt = ath_calcrxfilter(sc);
1672         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1673         ath9k_ps_restore(sc);
1674
1675         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1676                   "Set HW RX filter: 0x%x\n", rfilt);
1677 }
1678
1679 static int ath9k_sta_add(struct ieee80211_hw *hw,
1680                          struct ieee80211_vif *vif,
1681                          struct ieee80211_sta *sta)
1682 {
1683         struct ath_wiphy *aphy = hw->priv;
1684         struct ath_softc *sc = aphy->sc;
1685
1686         ath_node_attach(sc, sta);
1687
1688         return 0;
1689 }
1690
1691 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1692                             struct ieee80211_vif *vif,
1693                             struct ieee80211_sta *sta)
1694 {
1695         struct ath_wiphy *aphy = hw->priv;
1696         struct ath_softc *sc = aphy->sc;
1697
1698         ath_node_detach(sc, sta);
1699
1700         return 0;
1701 }
1702
1703 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
1704                          const struct ieee80211_tx_queue_params *params)
1705 {
1706         struct ath_wiphy *aphy = hw->priv;
1707         struct ath_softc *sc = aphy->sc;
1708         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1709         struct ath9k_tx_queue_info qi;
1710         int ret = 0, qnum;
1711
1712         if (queue >= WME_NUM_AC)
1713                 return 0;
1714
1715         mutex_lock(&sc->mutex);
1716
1717         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1718
1719         qi.tqi_aifs = params->aifs;
1720         qi.tqi_cwmin = params->cw_min;
1721         qi.tqi_cwmax = params->cw_max;
1722         qi.tqi_burstTime = params->txop;
1723         qnum = ath_get_hal_qnum(queue, sc);
1724
1725         ath_print(common, ATH_DBG_CONFIG,
1726                   "Configure tx [queue/halq] [%d/%d],  "
1727                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1728                   queue, qnum, params->aifs, params->cw_min,
1729                   params->cw_max, params->txop);
1730
1731         ret = ath_txq_update(sc, qnum, &qi);
1732         if (ret)
1733                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
1734
1735         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1736                 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
1737                         ath_beaconq_config(sc);
1738
1739         mutex_unlock(&sc->mutex);
1740
1741         return ret;
1742 }
1743
1744 static int ath9k_set_key(struct ieee80211_hw *hw,
1745                          enum set_key_cmd cmd,
1746                          struct ieee80211_vif *vif,
1747                          struct ieee80211_sta *sta,
1748                          struct ieee80211_key_conf *key)
1749 {
1750         struct ath_wiphy *aphy = hw->priv;
1751         struct ath_softc *sc = aphy->sc;
1752         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1753         int ret = 0;
1754
1755         if (modparam_nohwcrypt)
1756                 return -ENOSPC;
1757
1758         mutex_lock(&sc->mutex);
1759         ath9k_ps_wakeup(sc);
1760         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
1761
1762         switch (cmd) {
1763         case SET_KEY:
1764                 ret = ath_key_config(common, vif, sta, key);
1765                 if (ret >= 0) {
1766                         key->hw_key_idx = ret;
1767                         /* push IV and Michael MIC generation to stack */
1768                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1769                         if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1770                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1771                         if (sc->sc_ah->sw_mgmt_crypto &&
1772                             key->cipher == WLAN_CIPHER_SUITE_CCMP)
1773                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1774                         ret = 0;
1775                 }
1776                 break;
1777         case DISABLE_KEY:
1778                 ath_key_delete(common, key);
1779                 break;
1780         default:
1781                 ret = -EINVAL;
1782         }
1783
1784         ath9k_ps_restore(sc);
1785         mutex_unlock(&sc->mutex);
1786
1787         return ret;
1788 }
1789
1790 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1791                                    struct ieee80211_vif *vif,
1792                                    struct ieee80211_bss_conf *bss_conf,
1793                                    u32 changed)
1794 {
1795         struct ath_wiphy *aphy = hw->priv;
1796         struct ath_softc *sc = aphy->sc;
1797         struct ath_hw *ah = sc->sc_ah;
1798         struct ath_common *common = ath9k_hw_common(ah);
1799         struct ath_vif *avp = (void *)vif->drv_priv;
1800         int slottime;
1801         int error;
1802
1803         mutex_lock(&sc->mutex);
1804
1805         if (changed & BSS_CHANGED_BSSID) {
1806                 /* Set BSSID */
1807                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1808                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1809                 common->curaid = 0;
1810                 ath9k_hw_write_associd(ah);
1811
1812                 /* Set aggregation protection mode parameters */
1813                 sc->config.ath_aggr_prot = 0;
1814
1815                 /* Only legacy IBSS for now */
1816                 if (vif->type == NL80211_IFTYPE_ADHOC)
1817                         ath_update_chainmask(sc, 0);
1818
1819                 ath_print(common, ATH_DBG_CONFIG,
1820                           "BSSID: %pM aid: 0x%x\n",
1821                           common->curbssid, common->curaid);
1822
1823                 /* need to reconfigure the beacon */
1824                 sc->sc_flags &= ~SC_OP_BEACONS ;
1825         }
1826
1827         /* Enable transmission of beacons (AP, IBSS, MESH) */
1828         if ((changed & BSS_CHANGED_BEACON) ||
1829             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1830                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1831                 error = ath_beacon_alloc(aphy, vif);
1832                 if (!error)
1833                         ath_beacon_config(sc, vif);
1834         }
1835
1836         if (changed & BSS_CHANGED_ERP_SLOT) {
1837                 if (bss_conf->use_short_slot)
1838                         slottime = 9;
1839                 else
1840                         slottime = 20;
1841                 if (vif->type == NL80211_IFTYPE_AP) {
1842                         /*
1843                          * Defer update, so that connected stations can adjust
1844                          * their settings at the same time.
1845                          * See beacon.c for more details
1846                          */
1847                         sc->beacon.slottime = slottime;
1848                         sc->beacon.updateslot = UPDATE;
1849                 } else {
1850                         ah->slottime = slottime;
1851                         ath9k_hw_init_global_settings(ah);
1852                 }
1853         }
1854
1855         /* Disable transmission of beacons */
1856         if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1857                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1858
1859         if (changed & BSS_CHANGED_BEACON_INT) {
1860                 sc->beacon_interval = bss_conf->beacon_int;
1861                 /*
1862                  * In case of AP mode, the HW TSF has to be reset
1863                  * when the beacon interval changes.
1864                  */
1865                 if (vif->type == NL80211_IFTYPE_AP) {
1866                         sc->sc_flags |= SC_OP_TSF_RESET;
1867                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1868                         error = ath_beacon_alloc(aphy, vif);
1869                         if (!error)
1870                                 ath_beacon_config(sc, vif);
1871                 } else {
1872                         ath_beacon_config(sc, vif);
1873                 }
1874         }
1875
1876         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1877                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1878                           bss_conf->use_short_preamble);
1879                 if (bss_conf->use_short_preamble)
1880                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1881                 else
1882                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1883         }
1884
1885         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1886                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1887                           bss_conf->use_cts_prot);
1888                 if (bss_conf->use_cts_prot &&
1889                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1890                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1891                 else
1892                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1893         }
1894
1895         if (changed & BSS_CHANGED_ASSOC) {
1896                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
1897                         bss_conf->assoc);
1898                 ath9k_bss_assoc_info(sc, vif, bss_conf);
1899         }
1900
1901         mutex_unlock(&sc->mutex);
1902 }
1903
1904 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1905 {
1906         u64 tsf;
1907         struct ath_wiphy *aphy = hw->priv;
1908         struct ath_softc *sc = aphy->sc;
1909
1910         mutex_lock(&sc->mutex);
1911         tsf = ath9k_hw_gettsf64(sc->sc_ah);
1912         mutex_unlock(&sc->mutex);
1913
1914         return tsf;
1915 }
1916
1917 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1918 {
1919         struct ath_wiphy *aphy = hw->priv;
1920         struct ath_softc *sc = aphy->sc;
1921
1922         mutex_lock(&sc->mutex);
1923         ath9k_hw_settsf64(sc->sc_ah, tsf);
1924         mutex_unlock(&sc->mutex);
1925 }
1926
1927 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1928 {
1929         struct ath_wiphy *aphy = hw->priv;
1930         struct ath_softc *sc = aphy->sc;
1931
1932         mutex_lock(&sc->mutex);
1933
1934         ath9k_ps_wakeup(sc);
1935         ath9k_hw_reset_tsf(sc->sc_ah);
1936         ath9k_ps_restore(sc);
1937
1938         mutex_unlock(&sc->mutex);
1939 }
1940
1941 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1942                               struct ieee80211_vif *vif,
1943                               enum ieee80211_ampdu_mlme_action action,
1944                               struct ieee80211_sta *sta,
1945                               u16 tid, u16 *ssn)
1946 {
1947         struct ath_wiphy *aphy = hw->priv;
1948         struct ath_softc *sc = aphy->sc;
1949         int ret = 0;
1950
1951         local_bh_disable();
1952
1953         switch (action) {
1954         case IEEE80211_AMPDU_RX_START:
1955                 if (!(sc->sc_flags & SC_OP_RXAGGR))
1956                         ret = -ENOTSUPP;
1957                 break;
1958         case IEEE80211_AMPDU_RX_STOP:
1959                 break;
1960         case IEEE80211_AMPDU_TX_START:
1961                 ath9k_ps_wakeup(sc);
1962                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1963                 if (!ret)
1964                         ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1965                 ath9k_ps_restore(sc);
1966                 break;
1967         case IEEE80211_AMPDU_TX_STOP:
1968                 ath9k_ps_wakeup(sc);
1969                 ath_tx_aggr_stop(sc, sta, tid);
1970                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1971                 ath9k_ps_restore(sc);
1972                 break;
1973         case IEEE80211_AMPDU_TX_OPERATIONAL:
1974                 ath9k_ps_wakeup(sc);
1975                 ath_tx_aggr_resume(sc, sta, tid);
1976                 ath9k_ps_restore(sc);
1977                 break;
1978         default:
1979                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1980                           "Unknown AMPDU action\n");
1981         }
1982
1983         local_bh_enable();
1984
1985         return ret;
1986 }
1987
1988 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1989                              struct survey_info *survey)
1990 {
1991         struct ath_wiphy *aphy = hw->priv;
1992         struct ath_softc *sc = aphy->sc;
1993         struct ath_hw *ah = sc->sc_ah;
1994         struct ieee80211_supported_band *sband;
1995         struct ath9k_channel *chan;
1996
1997         sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1998         if (sband && idx >= sband->n_channels) {
1999                 idx -= sband->n_channels;
2000                 sband = NULL;
2001         }
2002
2003         if (!sband)
2004                 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2005
2006         if (!sband || idx >= sband->n_channels)
2007             return -ENOENT;
2008
2009         survey->channel = &sband->channels[idx];
2010         chan = &ah->channels[survey->channel->hw_value];
2011         survey->filled = 0;
2012
2013         if (chan == ah->curchan)
2014                 survey->filled |= SURVEY_INFO_IN_USE;
2015
2016         if (chan->noisefloor) {
2017                 survey->filled |= SURVEY_INFO_NOISE_DBM;
2018                 survey->noise = chan->noisefloor;
2019         }
2020
2021         return 0;
2022 }
2023
2024 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2025 {
2026         struct ath_wiphy *aphy = hw->priv;
2027         struct ath_softc *sc = aphy->sc;
2028
2029         mutex_lock(&sc->mutex);
2030         if (ath9k_wiphy_scanning(sc)) {
2031                 /*
2032                  * There is a race here in mac80211 but fixing it requires
2033                  * we revisit how we handle the scan complete callback.
2034                  * After mac80211 fixes we will not have configured hardware
2035                  * to the home channel nor would we have configured the RX
2036                  * filter yet.
2037                  */
2038                 mutex_unlock(&sc->mutex);
2039                 return;
2040         }
2041
2042         aphy->state = ATH_WIPHY_SCAN;
2043         ath9k_wiphy_pause_all_forced(sc, aphy);
2044         mutex_unlock(&sc->mutex);
2045 }
2046
2047 /*
2048  * XXX: this requires a revisit after the driver
2049  * scan_complete gets moved to another place/removed in mac80211.
2050  */
2051 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2052 {
2053         struct ath_wiphy *aphy = hw->priv;
2054         struct ath_softc *sc = aphy->sc;
2055
2056         mutex_lock(&sc->mutex);
2057         aphy->state = ATH_WIPHY_ACTIVE;
2058         mutex_unlock(&sc->mutex);
2059 }
2060
2061 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2062 {
2063         struct ath_wiphy *aphy = hw->priv;
2064         struct ath_softc *sc = aphy->sc;
2065         struct ath_hw *ah = sc->sc_ah;
2066
2067         mutex_lock(&sc->mutex);
2068         ah->coverage_class = coverage_class;
2069         ath9k_hw_init_global_settings(ah);
2070         mutex_unlock(&sc->mutex);
2071 }
2072
2073 struct ieee80211_ops ath9k_ops = {
2074         .tx                 = ath9k_tx,
2075         .start              = ath9k_start,
2076         .stop               = ath9k_stop,
2077         .add_interface      = ath9k_add_interface,
2078         .remove_interface   = ath9k_remove_interface,
2079         .config             = ath9k_config,
2080         .configure_filter   = ath9k_configure_filter,
2081         .sta_add            = ath9k_sta_add,
2082         .sta_remove         = ath9k_sta_remove,
2083         .conf_tx            = ath9k_conf_tx,
2084         .bss_info_changed   = ath9k_bss_info_changed,
2085         .set_key            = ath9k_set_key,
2086         .get_tsf            = ath9k_get_tsf,
2087         .set_tsf            = ath9k_set_tsf,
2088         .reset_tsf          = ath9k_reset_tsf,
2089         .ampdu_action       = ath9k_ampdu_action,
2090         .get_survey         = ath9k_get_survey,
2091         .sw_scan_start      = ath9k_sw_scan_start,
2092         .sw_scan_complete   = ath9k_sw_scan_complete,
2093         .rfkill_poll        = ath9k_rfkill_poll_state,
2094         .set_coverage_class = ath9k_set_coverage_class,
2095 };