2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
19 #include <linux/ath9k_platform.h>
22 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
23 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
24 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
25 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
27 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
30 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
32 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
36 /* return bus cachesize in 4B word units */
37 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
39 struct ath_softc *sc = (struct ath_softc *) common->priv;
42 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
46 * This check was put in to avoid "unplesant" consequences if
47 * the bootrom has not fully initialized all PCI devices.
48 * Sometimes the cache line size register is not set
52 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
55 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
57 struct ath_softc *sc = (struct ath_softc *) common->priv;
58 struct ath9k_platform_data *pdata = sc->dev->platform_data;
61 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
63 "%s: eeprom read failed, offset %08x is out of range\n",
67 *data = pdata->eeprom_data[off];
69 struct ath_hw *ah = (struct ath_hw *) common->ah;
71 common->ops->read(ah, AR5416_EEPROM_OFFSET +
72 (off << AR5416_EEPROM_S));
74 if (!ath9k_hw_wait(ah,
75 AR_EEPROM_STATUS_DATA,
76 AR_EEPROM_STATUS_DATA_BUSY |
77 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
82 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
83 AR_EEPROM_STATUS_DATA_VAL);
90 * Bluetooth coexistance requires disabling ASPM.
92 static void ath_pci_bt_coex_prep(struct ath_common *common)
94 struct ath_softc *sc = (struct ath_softc *) common->priv;
95 struct pci_dev *pdev = to_pci_dev(sc->dev);
101 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
102 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
103 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
106 static const struct ath_bus_ops ath_pci_bus_ops = {
107 .ath_bus_type = ATH_PCI,
108 .read_cachesize = ath_pci_read_cachesize,
109 .eeprom_read = ath_pci_eeprom_read,
110 .bt_coex_prep = ath_pci_bt_coex_prep,
113 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
116 struct ath_wiphy *aphy;
117 struct ath_softc *sc;
118 struct ieee80211_hw *hw;
125 if (pci_enable_device(pdev))
128 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
130 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
134 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
136 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
137 "DMA enable failed\n");
142 * Cache line size is used to size and align various
143 * structures used to communicate with the hardware.
145 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
148 * Linux 2.4.18 (at least) writes the cache line size
149 * register as a 16-bit wide register which is wrong.
150 * We must have this setup properly for rx buffer
151 * DMA to work so force a reasonable value here if it
154 csz = L1_CACHE_BYTES / sizeof(u32);
155 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
158 * The default setting of latency timer yields poor results,
159 * set it to the value used by other systems. It may be worth
160 * tweaking this setting more.
162 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
164 pci_set_master(pdev);
167 * Disable the RETRY_TIMEOUT register (0x41) to keep
168 * PCI Tx retries from interfering with C3 CPU state.
170 pci_read_config_dword(pdev, 0x40, &val);
171 if ((val & 0x0000ff00) != 0)
172 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
174 ret = pci_request_region(pdev, 0, "ath9k");
176 dev_err(&pdev->dev, "PCI memory region reserve error\n");
181 mem = pci_iomap(pdev, 0, 0);
183 printk(KERN_ERR "PCI memory map error\n") ;
188 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
189 sizeof(struct ath_softc), &ath9k_ops);
191 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
196 SET_IEEE80211_DEV(hw, &pdev->dev);
197 pci_set_drvdata(pdev, hw);
200 sc = (struct ath_softc *) (aphy + 1);
203 sc->pri_wiphy = aphy;
205 sc->dev = &pdev->dev;
208 /* Will be cleared in ath9k_start() */
209 sc->sc_flags |= SC_OP_INVALID;
211 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
213 dev_err(&pdev->dev, "request_irq failed\n");
219 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
220 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
222 dev_err(&pdev->dev, "Failed to initialize device\n");
226 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
227 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
228 hw_name, (unsigned long)mem, pdev->irq);
233 free_irq(sc->irq, sc);
235 ieee80211_free_hw(hw);
237 pci_iounmap(pdev, mem);
239 pci_release_region(pdev, 0);
243 pci_disable_device(pdev);
247 static void ath_pci_remove(struct pci_dev *pdev)
249 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
250 struct ath_wiphy *aphy = hw->priv;
251 struct ath_softc *sc = aphy->sc;
252 void __iomem *mem = sc->mem;
254 ath9k_deinit_device(sc);
255 free_irq(sc->irq, sc);
256 ieee80211_free_hw(sc->hw);
258 pci_iounmap(pdev, mem);
259 pci_disable_device(pdev);
260 pci_release_region(pdev, 0);
265 static int ath_pci_suspend(struct device *device)
267 struct pci_dev *pdev = to_pci_dev(device);
268 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
269 struct ath_wiphy *aphy = hw->priv;
270 struct ath_softc *sc = aphy->sc;
272 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
277 static int ath_pci_resume(struct device *device)
279 struct pci_dev *pdev = to_pci_dev(device);
280 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
281 struct ath_wiphy *aphy = hw->priv;
282 struct ath_softc *sc = aphy->sc;
286 * Suspend/Resume resets the PCI configuration space, so we have to
287 * re-disable the RETRY_TIMEOUT register (0x41) to keep
288 * PCI Tx retries from interfering with C3 CPU state
290 pci_read_config_dword(pdev, 0x40, &val);
291 if ((val & 0x0000ff00) != 0)
292 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
295 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
296 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
297 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
302 static const struct dev_pm_ops ath9k_pm_ops = {
303 .suspend = ath_pci_suspend,
304 .resume = ath_pci_resume,
305 .freeze = ath_pci_suspend,
306 .thaw = ath_pci_resume,
307 .poweroff = ath_pci_suspend,
308 .restore = ath_pci_resume,
311 #define ATH9K_PM_OPS (&ath9k_pm_ops)
313 #else /* !CONFIG_PM */
315 #define ATH9K_PM_OPS NULL
317 #endif /* !CONFIG_PM */
320 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
322 static struct pci_driver ath_pci_driver = {
324 .id_table = ath_pci_id_table,
325 .probe = ath_pci_probe,
326 .remove = ath_pci_remove,
327 .driver.pm = ATH9K_PM_OPS,
330 int ath_pci_init(void)
332 return pci_register_driver(&ath_pci_driver);
335 void ath_pci_exit(void)
337 pci_unregister_driver(&ath_pci_driver);