2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
21 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
29 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
33 /* return bus cachesize in 4B word units */
34 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
36 struct ath_softc *sc = (struct ath_softc *) common->priv;
39 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
43 * This check was put in to avoid "unplesant" consequences if
44 * the bootrom has not fully initialized all PCI devices.
45 * Sometimes the cache line size register is not set
49 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
52 static void ath_pci_cleanup(struct ath_common *common)
54 struct ath_softc *sc = (struct ath_softc *) common->priv;
55 struct pci_dev *pdev = to_pci_dev(sc->dev);
57 pci_iounmap(pdev, sc->mem);
58 pci_disable_device(pdev);
59 pci_release_region(pdev, 0);
62 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
64 struct ath_hw *ah = (struct ath_hw *) common->ah;
66 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
68 if (!ath9k_hw_wait(ah,
69 AR_EEPROM_STATUS_DATA,
70 AR_EEPROM_STATUS_DATA_BUSY |
71 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
76 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
77 AR_EEPROM_STATUS_DATA_VAL);
83 * Bluetooth coexistance requires disabling ASPM.
85 static void ath_pci_bt_coex_prep(struct ath_common *common)
87 struct ath_softc *sc = (struct ath_softc *) common->priv;
88 struct pci_dev *pdev = to_pci_dev(sc->dev);
94 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
95 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
96 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
99 static const struct ath_bus_ops ath_pci_bus_ops = {
100 .read_cachesize = ath_pci_read_cachesize,
101 .cleanup = ath_pci_cleanup,
102 .eeprom_read = ath_pci_eeprom_read,
103 .bt_coex_prep = ath_pci_bt_coex_prep,
106 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
109 struct ath_wiphy *aphy;
110 struct ath_softc *sc;
111 struct ieee80211_hw *hw;
118 if (pci_enable_device(pdev))
121 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
123 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
127 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
129 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
130 "DMA enable failed\n");
135 * Cache line size is used to size and align various
136 * structures used to communicate with the hardware.
138 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
141 * Linux 2.4.18 (at least) writes the cache line size
142 * register as a 16-bit wide register which is wrong.
143 * We must have this setup properly for rx buffer
144 * DMA to work so force a reasonable value here if it
147 csz = L1_CACHE_BYTES / sizeof(u32);
148 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
151 * The default setting of latency timer yields poor results,
152 * set it to the value used by other systems. It may be worth
153 * tweaking this setting more.
155 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
157 pci_set_master(pdev);
160 * Disable the RETRY_TIMEOUT register (0x41) to keep
161 * PCI Tx retries from interfering with C3 CPU state.
163 pci_read_config_dword(pdev, 0x40, &val);
164 if ((val & 0x0000ff00) != 0)
165 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
167 ret = pci_request_region(pdev, 0, "ath9k");
169 dev_err(&pdev->dev, "PCI memory region reserve error\n");
174 mem = pci_iomap(pdev, 0, 0);
176 printk(KERN_ERR "PCI memory map error\n") ;
181 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
182 sizeof(struct ath_softc), &ath9k_ops);
184 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
189 SET_IEEE80211_DEV(hw, &pdev->dev);
190 pci_set_drvdata(pdev, hw);
193 sc = (struct ath_softc *) (aphy + 1);
196 sc->pri_wiphy = aphy;
198 sc->dev = &pdev->dev;
201 /* Will be cleared in ath9k_start() */
202 sc->sc_flags |= SC_OP_INVALID;
204 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
206 dev_err(&pdev->dev, "request_irq failed\n");
212 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
213 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
215 dev_err(&pdev->dev, "Failed to initialize device\n");
219 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
221 "%s: %s mem=0x%lx, irq=%d\n",
222 wiphy_name(hw->wiphy),
224 (unsigned long)mem, pdev->irq);
229 free_irq(sc->irq, sc);
231 ieee80211_free_hw(hw);
233 pci_iounmap(pdev, mem);
235 pci_release_region(pdev, 0);
239 pci_disable_device(pdev);
243 static void ath_pci_remove(struct pci_dev *pdev)
245 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
246 struct ath_wiphy *aphy = hw->priv;
247 struct ath_softc *sc = aphy->sc;
248 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
250 ath9k_deinit_device(sc);
251 free_irq(sc->irq, sc);
252 ieee80211_free_hw(sc->hw);
253 ath_bus_cleanup(common);
258 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
260 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
261 struct ath_wiphy *aphy = hw->priv;
262 struct ath_softc *sc = aphy->sc;
264 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
266 pci_save_state(pdev);
267 pci_disable_device(pdev);
268 pci_set_power_state(pdev, PCI_D3hot);
273 static int ath_pci_resume(struct pci_dev *pdev)
275 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
276 struct ath_wiphy *aphy = hw->priv;
277 struct ath_softc *sc = aphy->sc;
281 pci_restore_state(pdev);
283 err = pci_enable_device(pdev);
288 * Suspend/Resume resets the PCI configuration space, so we have to
289 * re-disable the RETRY_TIMEOUT register (0x41) to keep
290 * PCI Tx retries from interfering with C3 CPU state
292 pci_read_config_dword(pdev, 0x40, &val);
293 if ((val & 0x0000ff00) != 0)
294 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
297 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
298 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
299 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
304 #endif /* CONFIG_PM */
306 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
308 static struct pci_driver ath_pci_driver = {
310 .id_table = ath_pci_id_table,
311 .probe = ath_pci_probe,
312 .remove = ath_pci_remove,
314 .suspend = ath_pci_suspend,
315 .resume = ath_pci_resume,
316 #endif /* CONFIG_PM */
319 int ath_pci_init(void)
321 return pci_register_driver(&ath_pci_driver);
324 void ath_pci_exit(void)
326 pci_unregister_driver(&ath_pci_driver);