2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
23 int mindelta, int main_rssi_avg,
24 int alt_rssi_avg, int pkt_count)
26 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
27 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
28 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
33 return sc->ps_enabled &&
34 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
38 struct ieee80211_hdr *hdr)
40 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
43 spin_lock_bh(&sc->wiphy_lock);
44 for (i = 0; i < sc->num_sec_wiphy; i++) {
45 struct ath_wiphy *aphy = sc->sec_wiphy[i];
48 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
54 spin_unlock_bh(&sc->wiphy_lock);
59 * Setup and link descriptors.
61 * 11N: we can no longer afford to self link the last descriptor.
62 * MAC acknowledges BA status as long as it copies frames to host
63 * buffer (or rx fifo). This can incorrectly acknowledge packets
64 * to a sender if last desc is self-linked.
66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
68 struct ath_hw *ah = sc->sc_ah;
69 struct ath_common *common = ath9k_hw_common(ah);
76 ds->ds_link = 0; /* link to null */
77 ds->ds_data = bf->bf_buf_addr;
79 /* virtual addr of the beginning of the buffer. */
82 ds->ds_vdata = skb->data;
85 * setup rx descriptors. The rx_bufsize here tells the hardware
86 * how much data it can DMA to us and that we are prepared
89 ath9k_hw_setuprxdesc(ah, ds,
93 if (sc->rx.rxlink == NULL)
94 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
96 *sc->rx.rxlink = bf->bf_daddr;
98 sc->rx.rxlink = &ds->ds_link;
102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
104 /* XXX block beacon interrupts */
105 ath9k_hw_setantenna(sc->sc_ah, antenna);
106 sc->rx.defant = antenna;
107 sc->rx.rxotherant = 0;
110 static void ath_opmode_init(struct ath_softc *sc)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_common *common = ath9k_hw_common(ah);
117 /* configure rx filter */
118 rfilt = ath_calcrxfilter(sc);
119 ath9k_hw_setrxfilter(ah, rfilt);
121 /* configure bssid mask */
122 ath_hw_setbssidmask(common);
124 /* configure operational mode */
125 ath9k_hw_setopmode(ah);
127 /* calculate and install multicast filter */
128 mfilt[0] = mfilt[1] = ~0;
129 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
133 enum ath9k_rx_qtype qtype)
135 struct ath_hw *ah = sc->sc_ah;
136 struct ath_rx_edma *rx_edma;
140 rx_edma = &sc->rx.rx_edma[qtype];
141 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
144 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
145 list_del_init(&bf->list);
150 memset(skb->data, 0, ah->caps.rx_status_len);
151 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
152 ah->caps.rx_status_len, DMA_TO_DEVICE);
154 SKB_CB_ATHBUF(skb) = bf;
155 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
156 skb_queue_tail(&rx_edma->rx_fifo, skb);
161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
162 enum ath9k_rx_qtype qtype, int size)
164 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
167 if (list_empty(&sc->rx.rxbuf)) {
168 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
172 while (!list_empty(&sc->rx.rxbuf)) {
175 if (!ath_rx_edma_buf_link(sc, qtype))
183 static void ath_rx_remove_buffer(struct ath_softc *sc,
184 enum ath9k_rx_qtype qtype)
187 struct ath_rx_edma *rx_edma;
190 rx_edma = &sc->rx.rx_edma[qtype];
192 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
193 bf = SKB_CB_ATHBUF(skb);
195 list_add_tail(&bf->list, &sc->rx.rxbuf);
199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
203 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
204 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
206 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
208 dev_kfree_skb_any(bf->bf_mpdu);
211 INIT_LIST_HEAD(&sc->rx.rxbuf);
213 kfree(sc->rx.rx_bufptr);
214 sc->rx.rx_bufptr = NULL;
217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
219 skb_queue_head_init(&rx_edma->rx_fifo);
220 skb_queue_head_init(&rx_edma->rx_buffers);
221 rx_edma->rx_fifo_hwsize = size;
224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
226 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227 struct ath_hw *ah = sc->sc_ah;
234 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
235 ah->caps.rx_status_len,
236 min(common->cachelsz, (u16)64));
238 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
239 ah->caps.rx_status_len);
241 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
242 ah->caps.rx_lp_qdepth);
243 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
244 ah->caps.rx_hp_qdepth);
246 size = sizeof(struct ath_buf) * nbufs;
247 bf = kzalloc(size, GFP_KERNEL);
251 INIT_LIST_HEAD(&sc->rx.rxbuf);
252 sc->rx.rx_bufptr = bf;
254 for (i = 0; i < nbufs; i++, bf++) {
255 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
261 memset(skb->data, 0, common->rx_bufsize);
264 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
267 if (unlikely(dma_mapping_error(sc->dev,
269 dev_kfree_skb_any(skb);
272 ath_print(common, ATH_DBG_FATAL,
273 "dma_mapping_error() on RX init\n");
278 list_add_tail(&bf->list, &sc->rx.rxbuf);
284 ath_rx_edma_cleanup(sc);
288 static void ath_edma_start_recv(struct ath_softc *sc)
290 spin_lock_bh(&sc->rx.rxbuflock);
292 ath9k_hw_rxena(sc->sc_ah);
294 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
295 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
297 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
298 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
302 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
304 spin_unlock_bh(&sc->rx.rxbuflock);
307 static void ath_edma_stop_recv(struct ath_softc *sc)
309 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
310 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
313 int ath_rx_init(struct ath_softc *sc, int nbufs)
315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
320 spin_lock_init(&sc->rx.pcu_lock);
321 sc->sc_flags &= ~SC_OP_RXFLUSH;
322 spin_lock_init(&sc->rx.rxbuflock);
324 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
325 return ath_rx_edma_init(sc, nbufs);
327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
328 min(common->cachelsz, (u16)64));
330 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
331 common->cachelsz, common->rx_bufsize);
333 /* Initialize rx descriptors */
335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
338 ath_print(common, ATH_DBG_FATAL,
339 "failed to allocate rx descriptors: %d\n",
344 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
353 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
356 if (unlikely(dma_mapping_error(sc->dev,
358 dev_kfree_skb_any(skb);
361 ath_print(common, ATH_DBG_FATAL,
362 "dma_mapping_error() on RX init\n");
367 sc->rx.rxlink = NULL;
377 void ath_rx_cleanup(struct ath_softc *sc)
379 struct ath_hw *ah = sc->sc_ah;
380 struct ath_common *common = ath9k_hw_common(ah);
384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
385 ath_rx_edma_cleanup(sc);
388 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
391 dma_unmap_single(sc->dev, bf->bf_buf_addr,
400 if (sc->rx.rxdma.dd_desc_len != 0)
401 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
406 * Calculate the receive filter according to the
407 * operating mode and state:
409 * o always accept unicast, broadcast, and multicast traffic
410 * o maintain current state of phy error reception (the hal
411 * may enable phy error frames for noise immunity work)
412 * o probe request frames are accepted only when operating in
413 * hostap, adhoc, or monitor modes
414 * o enable promiscuous mode according to the interface state
416 * - when operating in adhoc mode so the 802.11 layer creates
417 * node table entries for peers,
418 * - when operating in station mode for collecting rssi data when
419 * the station is otherwise quiet, or
420 * - when operating as a repeater so we see repeater-sta beacons
424 u32 ath_calcrxfilter(struct ath_softc *sc)
426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
430 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
431 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
432 | ATH9K_RX_FILTER_MCAST;
434 if (sc->rx.rxfilter & FIF_PROBE_REQ)
435 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
438 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
439 * mode interface or when in monitor mode. AP mode does not need this
440 * since it receives all in-BSS frames anyway.
442 if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
443 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
444 (sc->sc_ah->is_monitoring))
445 rfilt |= ATH9K_RX_FILTER_PROM;
447 if (sc->rx.rxfilter & FIF_CONTROL)
448 rfilt |= ATH9K_RX_FILTER_CONTROL;
450 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
452 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
453 rfilt |= ATH9K_RX_FILTER_MYBEACON;
455 rfilt |= ATH9K_RX_FILTER_BEACON;
457 if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
458 AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
459 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
460 (sc->rx.rxfilter & FIF_PSPOLL))
461 rfilt |= ATH9K_RX_FILTER_PSPOLL;
463 if (conf_is_ht(&sc->hw->conf))
464 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
466 if (sc->sec_wiphy || (sc->nvifs > 1) ||
467 (sc->rx.rxfilter & FIF_OTHER_BSS)) {
468 /* The following may also be needed for other older chips */
469 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
470 rfilt |= ATH9K_RX_FILTER_PROM;
471 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
476 #undef RX_FILTER_PRESERVE
479 int ath_startrecv(struct ath_softc *sc)
481 struct ath_hw *ah = sc->sc_ah;
482 struct ath_buf *bf, *tbf;
484 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
485 ath_edma_start_recv(sc);
489 spin_lock_bh(&sc->rx.rxbuflock);
490 if (list_empty(&sc->rx.rxbuf))
493 sc->rx.rxlink = NULL;
494 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
495 ath_rx_buf_link(sc, bf);
498 /* We could have deleted elements so the list may be empty now */
499 if (list_empty(&sc->rx.rxbuf))
502 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
503 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
508 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
510 spin_unlock_bh(&sc->rx.rxbuflock);
515 bool ath_stoprecv(struct ath_softc *sc)
517 struct ath_hw *ah = sc->sc_ah;
520 spin_lock_bh(&sc->rx.rxbuflock);
521 ath9k_hw_abortpcurecv(ah);
522 ath9k_hw_setrxfilter(ah, 0);
523 stopped = ath9k_hw_stopdmarecv(ah);
525 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
526 ath_edma_stop_recv(sc);
528 sc->rx.rxlink = NULL;
529 spin_unlock_bh(&sc->rx.rxbuflock);
534 void ath_flushrecv(struct ath_softc *sc)
536 sc->sc_flags |= SC_OP_RXFLUSH;
537 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
538 ath_rx_tasklet(sc, 1, true);
539 ath_rx_tasklet(sc, 1, false);
540 sc->sc_flags &= ~SC_OP_RXFLUSH;
543 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
545 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
546 struct ieee80211_mgmt *mgmt;
547 u8 *pos, *end, id, elen;
548 struct ieee80211_tim_ie *tim;
550 mgmt = (struct ieee80211_mgmt *)skb->data;
551 pos = mgmt->u.beacon.variable;
552 end = skb->data + skb->len;
554 while (pos + 2 < end) {
557 if (pos + elen > end)
560 if (id == WLAN_EID_TIM) {
561 if (elen < sizeof(*tim))
563 tim = (struct ieee80211_tim_ie *) pos;
564 if (tim->dtim_count != 0)
566 return tim->bitmap_ctrl & 0x01;
575 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
577 struct ieee80211_mgmt *mgmt;
578 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
580 if (skb->len < 24 + 8 + 2 + 2)
583 mgmt = (struct ieee80211_mgmt *)skb->data;
584 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
585 return; /* not from our current AP */
587 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
589 if (sc->ps_flags & PS_BEACON_SYNC) {
590 sc->ps_flags &= ~PS_BEACON_SYNC;
591 ath_print(common, ATH_DBG_PS,
592 "Reconfigure Beacon timers based on "
593 "timestamp from the AP\n");
594 ath_beacon_config(sc, NULL);
597 if (ath_beacon_dtim_pending_cab(skb)) {
599 * Remain awake waiting for buffered broadcast/multicast
600 * frames. If the last broadcast/multicast frame is not
601 * received properly, the next beacon frame will work as
602 * a backup trigger for returning into NETWORK SLEEP state,
603 * so we are waiting for it as well.
605 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
606 "buffered broadcast/multicast frame(s)\n");
607 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
611 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
613 * This can happen if a broadcast frame is dropped or the AP
614 * fails to send a frame indicating that all CAB frames have
617 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
618 ath_print(common, ATH_DBG_PS,
619 "PS wait for CAB frames timed out\n");
623 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
625 struct ieee80211_hdr *hdr;
626 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
628 hdr = (struct ieee80211_hdr *)skb->data;
630 /* Process Beacon and CAB receive in PS state */
631 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
632 && ieee80211_is_beacon(hdr->frame_control))
633 ath_rx_ps_beacon(sc, skb);
634 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
635 (ieee80211_is_data(hdr->frame_control) ||
636 ieee80211_is_action(hdr->frame_control)) &&
637 is_multicast_ether_addr(hdr->addr1) &&
638 !ieee80211_has_moredata(hdr->frame_control)) {
640 * No more broadcast/multicast frames to be received at this
643 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
644 ath_print(common, ATH_DBG_PS,
645 "All PS CAB frames received, back to sleep\n");
646 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
647 !is_multicast_ether_addr(hdr->addr1) &&
648 !ieee80211_has_morefrags(hdr->frame_control)) {
649 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
650 ath_print(common, ATH_DBG_PS,
651 "Going back to sleep after having received "
652 "PS-Poll data (0x%lx)\n",
653 sc->ps_flags & (PS_WAIT_FOR_BEACON |
655 PS_WAIT_FOR_PSPOLL_DATA |
656 PS_WAIT_FOR_TX_ACK));
660 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
661 struct ath_softc *sc, struct sk_buff *skb,
662 struct ieee80211_rx_status *rxs)
664 struct ieee80211_hdr *hdr;
666 hdr = (struct ieee80211_hdr *)skb->data;
668 /* Send the frame to mac80211 */
669 if (is_multicast_ether_addr(hdr->addr1)) {
672 * Deliver broadcast/multicast frames to all suitable
675 /* TODO: filter based on channel configuration */
676 for (i = 0; i < sc->num_sec_wiphy; i++) {
677 struct ath_wiphy *aphy = sc->sec_wiphy[i];
678 struct sk_buff *nskb;
681 nskb = skb_copy(skb, GFP_ATOMIC);
684 ieee80211_rx(aphy->hw, nskb);
686 ieee80211_rx(sc->hw, skb);
688 /* Deliver unicast frames based on receiver address */
689 ieee80211_rx(hw, skb);
692 static bool ath_edma_get_buffers(struct ath_softc *sc,
693 enum ath9k_rx_qtype qtype)
695 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
696 struct ath_hw *ah = sc->sc_ah;
697 struct ath_common *common = ath9k_hw_common(ah);
702 skb = skb_peek(&rx_edma->rx_fifo);
706 bf = SKB_CB_ATHBUF(skb);
709 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
710 common->rx_bufsize, DMA_FROM_DEVICE);
712 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
713 if (ret == -EINPROGRESS) {
714 /*let device gain the buffer again*/
715 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
716 common->rx_bufsize, DMA_FROM_DEVICE);
720 __skb_unlink(skb, &rx_edma->rx_fifo);
721 if (ret == -EINVAL) {
722 /* corrupt descriptor, skip this one and the following one */
723 list_add_tail(&bf->list, &sc->rx.rxbuf);
724 ath_rx_edma_buf_link(sc, qtype);
725 skb = skb_peek(&rx_edma->rx_fifo);
729 bf = SKB_CB_ATHBUF(skb);
732 __skb_unlink(skb, &rx_edma->rx_fifo);
733 list_add_tail(&bf->list, &sc->rx.rxbuf);
734 ath_rx_edma_buf_link(sc, qtype);
737 skb_queue_tail(&rx_edma->rx_buffers, skb);
742 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
743 struct ath_rx_status *rs,
744 enum ath9k_rx_qtype qtype)
746 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
750 while (ath_edma_get_buffers(sc, qtype));
751 skb = __skb_dequeue(&rx_edma->rx_buffers);
755 bf = SKB_CB_ATHBUF(skb);
756 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
760 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
761 struct ath_rx_status *rs)
763 struct ath_hw *ah = sc->sc_ah;
764 struct ath_common *common = ath9k_hw_common(ah);
769 if (list_empty(&sc->rx.rxbuf)) {
770 sc->rx.rxlink = NULL;
774 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
778 * Must provide the virtual address of the current
779 * descriptor, the physical address, and the virtual
780 * address of the next descriptor in the h/w chain.
781 * This allows the HAL to look ahead to see if the
782 * hardware is done with a descriptor by checking the
783 * done bit in the following descriptor and the address
784 * of the current descriptor the DMA engine is working
785 * on. All this is necessary because of our use of
786 * a self-linked list to avoid rx overruns.
788 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
789 if (ret == -EINPROGRESS) {
790 struct ath_rx_status trs;
792 struct ath_desc *tds;
794 memset(&trs, 0, sizeof(trs));
795 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
796 sc->rx.rxlink = NULL;
800 tbf = list_entry(bf->list.next, struct ath_buf, list);
803 * On some hardware the descriptor status words could
804 * get corrupted, including the done bit. Because of
805 * this, check if the next descriptor's done bit is
808 * If the next descriptor's done bit is set, the current
809 * descriptor has been corrupted. Force s/w to discard
810 * this descriptor and continue...
814 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
815 if (ret == -EINPROGRESS)
823 * Synchronize the DMA transfer with CPU before
824 * 1. accessing the frame
825 * 2. requeueing the same buffer to h/w
827 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
834 /* Assumes you've already done the endian to CPU conversion */
835 static bool ath9k_rx_accept(struct ath_common *common,
836 struct ieee80211_hdr *hdr,
837 struct ieee80211_rx_status *rxs,
838 struct ath_rx_status *rx_stats,
841 struct ath_hw *ah = common->ah;
843 u8 rx_status_len = ah->caps.rx_status_len;
845 fc = hdr->frame_control;
847 if (!rx_stats->rs_datalen)
850 * rs_status follows rs_datalen so if rs_datalen is too large
851 * we can take a hint that hardware corrupted it, so ignore
854 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
858 * rs_more indicates chained descriptors which can be used
859 * to link buffers together for a sort of scatter-gather
861 * reject the frame, we don't support scatter-gather yet and
862 * the frame is probably corrupt anyway
864 if (rx_stats->rs_more)
868 * The rx_stats->rs_status will not be set until the end of the
869 * chained descriptors so it can be ignored if rs_more is set. The
870 * rs_more will be false at the last element of the chained
873 if (rx_stats->rs_status != 0) {
874 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
875 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
876 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
879 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
880 *decrypt_error = true;
881 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
883 * The MIC error bit is only valid if the frame
884 * is not a control frame or fragment, and it was
885 * decrypted using a valid TKIP key.
887 if (!ieee80211_is_ctl(fc) &&
888 !ieee80211_has_morefrags(fc) &&
889 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
890 test_bit(rx_stats->rs_keyix, common->tkip_keymap))
891 rxs->flag |= RX_FLAG_MMIC_ERROR;
893 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
896 * Reject error frames with the exception of
897 * decryption and MIC failures. For monitor mode,
898 * we also ignore the CRC error.
900 if (ah->is_monitoring) {
901 if (rx_stats->rs_status &
902 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
906 if (rx_stats->rs_status &
907 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
915 static int ath9k_process_rate(struct ath_common *common,
916 struct ieee80211_hw *hw,
917 struct ath_rx_status *rx_stats,
918 struct ieee80211_rx_status *rxs)
920 struct ieee80211_supported_band *sband;
921 enum ieee80211_band band;
924 band = hw->conf.channel->band;
925 sband = hw->wiphy->bands[band];
927 if (rx_stats->rs_rate & 0x80) {
929 rxs->flag |= RX_FLAG_HT;
930 if (rx_stats->rs_flags & ATH9K_RX_2040)
931 rxs->flag |= RX_FLAG_40MHZ;
932 if (rx_stats->rs_flags & ATH9K_RX_GI)
933 rxs->flag |= RX_FLAG_SHORT_GI;
934 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
938 for (i = 0; i < sband->n_bitrates; i++) {
939 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
943 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
944 rxs->flag |= RX_FLAG_SHORTPRE;
951 * No valid hardware bitrate found -- we should not get here
952 * because hardware has already validated this frame as OK.
954 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
955 "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
960 static void ath9k_process_rssi(struct ath_common *common,
961 struct ieee80211_hw *hw,
962 struct ieee80211_hdr *hdr,
963 struct ath_rx_status *rx_stats)
965 struct ath_hw *ah = common->ah;
966 struct ieee80211_sta *sta;
968 int last_rssi = ATH_RSSI_DUMMY_MARKER;
971 fc = hdr->frame_control;
975 * XXX: use ieee80211_find_sta! This requires quite a bit of work
976 * under the current ath9k virtual wiphy implementation as we have
977 * no way of tying a vif to wiphy. Typically vifs are attached to
978 * at least one sdata of a wiphy on mac80211 but with ath9k virtual
979 * wiphy you'd have to iterate over every wiphy and each sdata.
981 if (is_multicast_ether_addr(hdr->addr1))
982 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, NULL);
984 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, hdr->addr1);
987 an = (struct ath_node *) sta->drv_priv;
988 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
989 !rx_stats->rs_moreaggr)
990 ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
991 last_rssi = an->last_rssi;
995 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
996 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
997 ATH_RSSI_EP_MULTIPLIER);
998 if (rx_stats->rs_rssi < 0)
999 rx_stats->rs_rssi = 0;
1001 /* Update Beacon RSSI, this is used by ANI. */
1002 if (ieee80211_is_beacon(fc))
1003 ah->stats.avgbrssi = rx_stats->rs_rssi;
1007 * For Decrypt or Demic errors, we only mark packet status here and always push
1008 * up the frame up to let mac80211 handle the actual error case, be it no
1009 * decryption key or real decryption error. This let us keep statistics there.
1011 static int ath9k_rx_skb_preprocess(struct ath_common *common,
1012 struct ieee80211_hw *hw,
1013 struct ieee80211_hdr *hdr,
1014 struct ath_rx_status *rx_stats,
1015 struct ieee80211_rx_status *rx_status,
1016 bool *decrypt_error)
1018 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1021 * everything but the rate is checked here, the rate check is done
1022 * separately to avoid doing two lookups for a rate for each frame.
1024 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1027 ath9k_process_rssi(common, hw, hdr, rx_stats);
1029 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1032 rx_status->band = hw->conf.channel->band;
1033 rx_status->freq = hw->conf.channel->center_freq;
1034 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1035 rx_status->antenna = rx_stats->rs_antenna;
1036 rx_status->flag |= RX_FLAG_TSFT;
1041 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1042 struct sk_buff *skb,
1043 struct ath_rx_status *rx_stats,
1044 struct ieee80211_rx_status *rxs,
1047 struct ath_hw *ah = common->ah;
1048 struct ieee80211_hdr *hdr;
1049 int hdrlen, padpos, padsize;
1053 /* see if any padding is done by the hw and remove it */
1054 hdr = (struct ieee80211_hdr *) skb->data;
1055 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1056 fc = hdr->frame_control;
1057 padpos = ath9k_cmn_padpos(hdr->frame_control);
1059 /* The MAC header is padded to have 32-bit boundary if the
1060 * packet payload is non-zero. The general calculation for
1061 * padsize would take into account odd header lengths:
1062 * padsize = (4 - padpos % 4) % 4; However, since only
1063 * even-length headers are used, padding can only be 0 or 2
1064 * bytes and we can optimize this a bit. In addition, we must
1065 * not try to remove padding from short control frames that do
1066 * not have payload. */
1067 padsize = padpos & 3;
1068 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1069 memmove(skb->data + padsize, skb->data, padpos);
1070 skb_pull(skb, padsize);
1073 keyix = rx_stats->rs_keyix;
1075 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1076 ieee80211_has_protected(fc)) {
1077 rxs->flag |= RX_FLAG_DECRYPTED;
1078 } else if (ieee80211_has_protected(fc)
1079 && !decrypt_error && skb->len >= hdrlen + 4) {
1080 keyix = skb->data[hdrlen + 3] >> 6;
1082 if (test_bit(keyix, common->keymap))
1083 rxs->flag |= RX_FLAG_DECRYPTED;
1085 if (ah->sw_mgmt_crypto &&
1086 (rxs->flag & RX_FLAG_DECRYPTED) &&
1087 ieee80211_is_mgmt(fc))
1088 /* Use software decrypt for management frames. */
1089 rxs->flag &= ~RX_FLAG_DECRYPTED;
1092 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1093 struct ath_hw_antcomb_conf ant_conf,
1096 antcomb->quick_scan_cnt = 0;
1098 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1099 antcomb->rssi_lna2 = main_rssi_avg;
1100 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1101 antcomb->rssi_lna1 = main_rssi_avg;
1103 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1104 case (0x10): /* LNA2 A-B */
1105 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1106 antcomb->first_quick_scan_conf =
1107 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1108 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1110 case (0x20): /* LNA1 A-B */
1111 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1112 antcomb->first_quick_scan_conf =
1113 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1114 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1116 case (0x21): /* LNA1 LNA2 */
1117 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1118 antcomb->first_quick_scan_conf =
1119 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1120 antcomb->second_quick_scan_conf =
1121 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1123 case (0x12): /* LNA2 LNA1 */
1124 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1125 antcomb->first_quick_scan_conf =
1126 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1127 antcomb->second_quick_scan_conf =
1128 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1130 case (0x13): /* LNA2 A+B */
1131 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1132 antcomb->first_quick_scan_conf =
1133 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1134 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1136 case (0x23): /* LNA1 A+B */
1137 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1138 antcomb->first_quick_scan_conf =
1139 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1140 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1147 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1148 struct ath_hw_antcomb_conf *div_ant_conf,
1149 int main_rssi_avg, int alt_rssi_avg,
1153 switch (antcomb->quick_scan_cnt) {
1155 /* set alt to main, and alt to first conf */
1156 div_ant_conf->main_lna_conf = antcomb->main_conf;
1157 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1160 /* set alt to main, and alt to first conf */
1161 div_ant_conf->main_lna_conf = antcomb->main_conf;
1162 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1163 antcomb->rssi_first = main_rssi_avg;
1164 antcomb->rssi_second = alt_rssi_avg;
1166 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1168 if (ath_is_alt_ant_ratio_better(alt_ratio,
1169 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1170 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1171 main_rssi_avg, alt_rssi_avg,
1172 antcomb->total_pkt_count))
1173 antcomb->first_ratio = true;
1175 antcomb->first_ratio = false;
1176 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1177 if (ath_is_alt_ant_ratio_better(alt_ratio,
1178 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1179 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1180 main_rssi_avg, alt_rssi_avg,
1181 antcomb->total_pkt_count))
1182 antcomb->first_ratio = true;
1184 antcomb->first_ratio = false;
1186 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1187 (alt_rssi_avg > main_rssi_avg +
1188 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1189 (alt_rssi_avg > main_rssi_avg)) &&
1190 (antcomb->total_pkt_count > 50))
1191 antcomb->first_ratio = true;
1193 antcomb->first_ratio = false;
1197 antcomb->alt_good = false;
1198 antcomb->scan_not_start = false;
1199 antcomb->scan = false;
1200 antcomb->rssi_first = main_rssi_avg;
1201 antcomb->rssi_third = alt_rssi_avg;
1203 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1204 antcomb->rssi_lna1 = alt_rssi_avg;
1205 else if (antcomb->second_quick_scan_conf ==
1206 ATH_ANT_DIV_COMB_LNA2)
1207 antcomb->rssi_lna2 = alt_rssi_avg;
1208 else if (antcomb->second_quick_scan_conf ==
1209 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1210 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1211 antcomb->rssi_lna2 = main_rssi_avg;
1212 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1213 antcomb->rssi_lna1 = main_rssi_avg;
1216 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1217 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1218 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1220 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1222 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1223 if (ath_is_alt_ant_ratio_better(alt_ratio,
1224 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1225 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1226 main_rssi_avg, alt_rssi_avg,
1227 antcomb->total_pkt_count))
1228 antcomb->second_ratio = true;
1230 antcomb->second_ratio = false;
1231 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1232 if (ath_is_alt_ant_ratio_better(alt_ratio,
1233 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1234 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1235 main_rssi_avg, alt_rssi_avg,
1236 antcomb->total_pkt_count))
1237 antcomb->second_ratio = true;
1239 antcomb->second_ratio = false;
1241 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1242 (alt_rssi_avg > main_rssi_avg +
1243 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1244 (alt_rssi_avg > main_rssi_avg)) &&
1245 (antcomb->total_pkt_count > 50))
1246 antcomb->second_ratio = true;
1248 antcomb->second_ratio = false;
1251 /* set alt to the conf with maximun ratio */
1252 if (antcomb->first_ratio && antcomb->second_ratio) {
1253 if (antcomb->rssi_second > antcomb->rssi_third) {
1255 if ((antcomb->first_quick_scan_conf ==
1256 ATH_ANT_DIV_COMB_LNA1) ||
1257 (antcomb->first_quick_scan_conf ==
1258 ATH_ANT_DIV_COMB_LNA2))
1259 /* Set alt LNA1 or LNA2*/
1260 if (div_ant_conf->main_lna_conf ==
1261 ATH_ANT_DIV_COMB_LNA2)
1262 div_ant_conf->alt_lna_conf =
1263 ATH_ANT_DIV_COMB_LNA1;
1265 div_ant_conf->alt_lna_conf =
1266 ATH_ANT_DIV_COMB_LNA2;
1268 /* Set alt to A+B or A-B */
1269 div_ant_conf->alt_lna_conf =
1270 antcomb->first_quick_scan_conf;
1271 } else if ((antcomb->second_quick_scan_conf ==
1272 ATH_ANT_DIV_COMB_LNA1) ||
1273 (antcomb->second_quick_scan_conf ==
1274 ATH_ANT_DIV_COMB_LNA2)) {
1275 /* Set alt LNA1 or LNA2 */
1276 if (div_ant_conf->main_lna_conf ==
1277 ATH_ANT_DIV_COMB_LNA2)
1278 div_ant_conf->alt_lna_conf =
1279 ATH_ANT_DIV_COMB_LNA1;
1281 div_ant_conf->alt_lna_conf =
1282 ATH_ANT_DIV_COMB_LNA2;
1284 /* Set alt to A+B or A-B */
1285 div_ant_conf->alt_lna_conf =
1286 antcomb->second_quick_scan_conf;
1288 } else if (antcomb->first_ratio) {
1290 if ((antcomb->first_quick_scan_conf ==
1291 ATH_ANT_DIV_COMB_LNA1) ||
1292 (antcomb->first_quick_scan_conf ==
1293 ATH_ANT_DIV_COMB_LNA2))
1294 /* Set alt LNA1 or LNA2 */
1295 if (div_ant_conf->main_lna_conf ==
1296 ATH_ANT_DIV_COMB_LNA2)
1297 div_ant_conf->alt_lna_conf =
1298 ATH_ANT_DIV_COMB_LNA1;
1300 div_ant_conf->alt_lna_conf =
1301 ATH_ANT_DIV_COMB_LNA2;
1303 /* Set alt to A+B or A-B */
1304 div_ant_conf->alt_lna_conf =
1305 antcomb->first_quick_scan_conf;
1306 } else if (antcomb->second_ratio) {
1308 if ((antcomb->second_quick_scan_conf ==
1309 ATH_ANT_DIV_COMB_LNA1) ||
1310 (antcomb->second_quick_scan_conf ==
1311 ATH_ANT_DIV_COMB_LNA2))
1312 /* Set alt LNA1 or LNA2 */
1313 if (div_ant_conf->main_lna_conf ==
1314 ATH_ANT_DIV_COMB_LNA2)
1315 div_ant_conf->alt_lna_conf =
1316 ATH_ANT_DIV_COMB_LNA1;
1318 div_ant_conf->alt_lna_conf =
1319 ATH_ANT_DIV_COMB_LNA2;
1321 /* Set alt to A+B or A-B */
1322 div_ant_conf->alt_lna_conf =
1323 antcomb->second_quick_scan_conf;
1325 /* main is largest */
1326 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1327 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1328 /* Set alt LNA1 or LNA2 */
1329 if (div_ant_conf->main_lna_conf ==
1330 ATH_ANT_DIV_COMB_LNA2)
1331 div_ant_conf->alt_lna_conf =
1332 ATH_ANT_DIV_COMB_LNA1;
1334 div_ant_conf->alt_lna_conf =
1335 ATH_ANT_DIV_COMB_LNA2;
1337 /* Set alt to A+B or A-B */
1338 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1346 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1348 /* Adjust the fast_div_bias based on main and alt lna conf */
1349 switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1350 case (0x01): /* A-B LNA2 */
1351 ant_conf->fast_div_bias = 0x3b;
1353 case (0x02): /* A-B LNA1 */
1354 ant_conf->fast_div_bias = 0x3d;
1356 case (0x03): /* A-B A+B */
1357 ant_conf->fast_div_bias = 0x1;
1359 case (0x10): /* LNA2 A-B */
1360 ant_conf->fast_div_bias = 0x7;
1362 case (0x12): /* LNA2 LNA1 */
1363 ant_conf->fast_div_bias = 0x2;
1365 case (0x13): /* LNA2 A+B */
1366 ant_conf->fast_div_bias = 0x7;
1368 case (0x20): /* LNA1 A-B */
1369 ant_conf->fast_div_bias = 0x6;
1371 case (0x21): /* LNA1 LNA2 */
1372 ant_conf->fast_div_bias = 0x0;
1374 case (0x23): /* LNA1 A+B */
1375 ant_conf->fast_div_bias = 0x6;
1377 case (0x30): /* A+B A-B */
1378 ant_conf->fast_div_bias = 0x1;
1380 case (0x31): /* A+B LNA2 */
1381 ant_conf->fast_div_bias = 0x3b;
1383 case (0x32): /* A+B LNA1 */
1384 ant_conf->fast_div_bias = 0x3d;
1391 /* Antenna diversity and combining */
1392 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1394 struct ath_hw_antcomb_conf div_ant_conf;
1395 struct ath_ant_comb *antcomb = &sc->ant_comb;
1396 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1397 int curr_main_set, curr_bias;
1398 int main_rssi = rs->rs_rssi_ctl0;
1399 int alt_rssi = rs->rs_rssi_ctl1;
1400 int rx_ant_conf, main_ant_conf;
1401 bool short_scan = false;
1403 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1405 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1408 /* Record packet only when alt_rssi is positive */
1410 antcomb->total_pkt_count++;
1411 antcomb->main_total_rssi += main_rssi;
1412 antcomb->alt_total_rssi += alt_rssi;
1413 if (main_ant_conf == rx_ant_conf)
1414 antcomb->main_recv_cnt++;
1416 antcomb->alt_recv_cnt++;
1419 /* Short scan check */
1420 if (antcomb->scan && antcomb->alt_good) {
1421 if (time_after(jiffies, antcomb->scan_start_time +
1422 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1425 if (antcomb->total_pkt_count ==
1426 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1427 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1428 antcomb->total_pkt_count);
1429 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1434 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1435 rs->rs_moreaggr) && !short_scan)
1438 if (antcomb->total_pkt_count) {
1439 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1440 antcomb->total_pkt_count);
1441 main_rssi_avg = (antcomb->main_total_rssi /
1442 antcomb->total_pkt_count);
1443 alt_rssi_avg = (antcomb->alt_total_rssi /
1444 antcomb->total_pkt_count);
1448 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1449 curr_alt_set = div_ant_conf.alt_lna_conf;
1450 curr_main_set = div_ant_conf.main_lna_conf;
1451 curr_bias = div_ant_conf.fast_div_bias;
1455 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1456 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1457 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1459 antcomb->alt_good = true;
1461 antcomb->alt_good = false;
1465 antcomb->scan = true;
1466 antcomb->scan_not_start = true;
1469 if (!antcomb->scan) {
1470 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1471 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1472 /* Switch main and alt LNA */
1473 div_ant_conf.main_lna_conf =
1474 ATH_ANT_DIV_COMB_LNA2;
1475 div_ant_conf.alt_lna_conf =
1476 ATH_ANT_DIV_COMB_LNA1;
1477 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1478 div_ant_conf.main_lna_conf =
1479 ATH_ANT_DIV_COMB_LNA1;
1480 div_ant_conf.alt_lna_conf =
1481 ATH_ANT_DIV_COMB_LNA2;
1485 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1486 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1487 /* Set alt to another LNA */
1488 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1489 div_ant_conf.alt_lna_conf =
1490 ATH_ANT_DIV_COMB_LNA1;
1491 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1492 div_ant_conf.alt_lna_conf =
1493 ATH_ANT_DIV_COMB_LNA2;
1498 if ((alt_rssi_avg < (main_rssi_avg +
1499 ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1503 if (!antcomb->scan_not_start) {
1504 switch (curr_alt_set) {
1505 case ATH_ANT_DIV_COMB_LNA2:
1506 antcomb->rssi_lna2 = alt_rssi_avg;
1507 antcomb->rssi_lna1 = main_rssi_avg;
1508 antcomb->scan = true;
1510 div_ant_conf.main_lna_conf =
1511 ATH_ANT_DIV_COMB_LNA1;
1512 div_ant_conf.alt_lna_conf =
1513 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1515 case ATH_ANT_DIV_COMB_LNA1:
1516 antcomb->rssi_lna1 = alt_rssi_avg;
1517 antcomb->rssi_lna2 = main_rssi_avg;
1518 antcomb->scan = true;
1520 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1521 div_ant_conf.alt_lna_conf =
1522 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1524 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1525 antcomb->rssi_add = alt_rssi_avg;
1526 antcomb->scan = true;
1528 div_ant_conf.alt_lna_conf =
1529 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1531 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1532 antcomb->rssi_sub = alt_rssi_avg;
1533 antcomb->scan = false;
1534 if (antcomb->rssi_lna2 >
1535 (antcomb->rssi_lna1 +
1536 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1537 /* use LNA2 as main LNA */
1538 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1539 (antcomb->rssi_add > antcomb->rssi_sub)) {
1541 div_ant_conf.main_lna_conf =
1542 ATH_ANT_DIV_COMB_LNA2;
1543 div_ant_conf.alt_lna_conf =
1544 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1545 } else if (antcomb->rssi_sub >
1546 antcomb->rssi_lna1) {
1548 div_ant_conf.main_lna_conf =
1549 ATH_ANT_DIV_COMB_LNA2;
1550 div_ant_conf.alt_lna_conf =
1551 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1554 div_ant_conf.main_lna_conf =
1555 ATH_ANT_DIV_COMB_LNA2;
1556 div_ant_conf.alt_lna_conf =
1557 ATH_ANT_DIV_COMB_LNA1;
1560 /* use LNA1 as main LNA */
1561 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1562 (antcomb->rssi_add > antcomb->rssi_sub)) {
1564 div_ant_conf.main_lna_conf =
1565 ATH_ANT_DIV_COMB_LNA1;
1566 div_ant_conf.alt_lna_conf =
1567 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1568 } else if (antcomb->rssi_sub >
1569 antcomb->rssi_lna1) {
1571 div_ant_conf.main_lna_conf =
1572 ATH_ANT_DIV_COMB_LNA1;
1573 div_ant_conf.alt_lna_conf =
1574 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1577 div_ant_conf.main_lna_conf =
1578 ATH_ANT_DIV_COMB_LNA1;
1579 div_ant_conf.alt_lna_conf =
1580 ATH_ANT_DIV_COMB_LNA2;
1588 if (!antcomb->alt_good) {
1589 antcomb->scan_not_start = false;
1590 /* Set alt to another LNA */
1591 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1592 div_ant_conf.main_lna_conf =
1593 ATH_ANT_DIV_COMB_LNA2;
1594 div_ant_conf.alt_lna_conf =
1595 ATH_ANT_DIV_COMB_LNA1;
1596 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1597 div_ant_conf.main_lna_conf =
1598 ATH_ANT_DIV_COMB_LNA1;
1599 div_ant_conf.alt_lna_conf =
1600 ATH_ANT_DIV_COMB_LNA2;
1606 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1607 main_rssi_avg, alt_rssi_avg,
1610 antcomb->quick_scan_cnt++;
1613 ath_ant_div_conf_fast_divbias(&div_ant_conf);
1615 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1617 antcomb->scan_start_time = jiffies;
1618 antcomb->total_pkt_count = 0;
1619 antcomb->main_total_rssi = 0;
1620 antcomb->alt_total_rssi = 0;
1621 antcomb->main_recv_cnt = 0;
1622 antcomb->alt_recv_cnt = 0;
1625 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1628 struct sk_buff *skb = NULL, *requeue_skb;
1629 struct ieee80211_rx_status *rxs;
1630 struct ath_hw *ah = sc->sc_ah;
1631 struct ath_common *common = ath9k_hw_common(ah);
1633 * The hw can techncically differ from common->hw when using ath9k
1634 * virtual wiphy so to account for that we iterate over the active
1635 * wiphys and find the appropriate wiphy and therefore hw.
1637 struct ieee80211_hw *hw = NULL;
1638 struct ieee80211_hdr *hdr;
1640 bool decrypt_error = false;
1641 struct ath_rx_status rs;
1642 enum ath9k_rx_qtype qtype;
1643 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1645 u8 rx_status_len = ah->caps.rx_status_len;
1648 unsigned long flags;
1651 dma_type = DMA_BIDIRECTIONAL;
1653 dma_type = DMA_FROM_DEVICE;
1655 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1656 spin_lock_bh(&sc->rx.rxbuflock);
1658 tsf = ath9k_hw_gettsf64(ah);
1659 tsf_lower = tsf & 0xffffffff;
1662 /* If handling rx interrupt and flush is in progress => exit */
1663 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1666 memset(&rs, 0, sizeof(rs));
1668 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1670 bf = ath_get_next_rx_buf(sc, &rs);
1679 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1680 rxs = IEEE80211_SKB_RXCB(skb);
1682 hw = ath_get_virt_hw(sc, hdr);
1684 ath_debug_stat_rx(sc, &rs);
1687 * If we're asked to flush receive queue, directly
1688 * chain it back at the queue without processing it.
1693 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1694 rxs, &decrypt_error);
1698 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1699 if (rs.rs_tstamp > tsf_lower &&
1700 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1701 rxs->mactime -= 0x100000000ULL;
1703 if (rs.rs_tstamp < tsf_lower &&
1704 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1705 rxs->mactime += 0x100000000ULL;
1707 /* Ensure we always have an skb to requeue once we are done
1708 * processing the current buffer's skb */
1709 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1711 /* If there is no memory we ignore the current RX'd frame,
1712 * tell hardware it can give us a new frame using the old
1713 * skb and put it at the tail of the sc->rx.rxbuf list for
1718 /* Unmap the frame */
1719 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1723 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1724 if (ah->caps.rx_status_len)
1725 skb_pull(skb, ah->caps.rx_status_len);
1727 ath9k_rx_skb_postprocess(common, skb, &rs,
1728 rxs, decrypt_error);
1730 /* We will now give hardware our shiny new allocated skb */
1731 bf->bf_mpdu = requeue_skb;
1732 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1735 if (unlikely(dma_mapping_error(sc->dev,
1736 bf->bf_buf_addr))) {
1737 dev_kfree_skb_any(requeue_skb);
1739 bf->bf_buf_addr = 0;
1740 ath_print(common, ATH_DBG_FATAL,
1741 "dma_mapping_error() on RX\n");
1742 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1747 * change the default rx antenna if rx diversity chooses the
1748 * other antenna 3 times in a row.
1750 if (sc->rx.defant != rs.rs_antenna) {
1751 if (++sc->rx.rxotherant >= 3)
1752 ath_setdefantenna(sc, rs.rs_antenna);
1754 sc->rx.rxotherant = 0;
1757 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1758 if (unlikely(ath9k_check_auto_sleep(sc) ||
1759 (sc->ps_flags & (PS_WAIT_FOR_BEACON |
1761 PS_WAIT_FOR_PSPOLL_DATA))))
1763 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1765 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1766 ath_ant_comb_scan(sc, &rs);
1768 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1772 list_add_tail(&bf->list, &sc->rx.rxbuf);
1773 ath_rx_edma_buf_link(sc, qtype);
1775 list_move_tail(&bf->list, &sc->rx.rxbuf);
1776 ath_rx_buf_link(sc, bf);
1780 spin_unlock_bh(&sc->rx.rxbuflock);