2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
24 return sc->ps_enabled &&
25 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
28 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
29 struct ieee80211_hdr *hdr)
31 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
34 spin_lock_bh(&sc->wiphy_lock);
35 for (i = 0; i < sc->num_sec_wiphy; i++) {
36 struct ath_wiphy *aphy = sc->sec_wiphy[i];
39 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
45 spin_unlock_bh(&sc->wiphy_lock);
50 * Setup and link descriptors.
52 * 11N: we can no longer afford to self link the last descriptor.
53 * MAC acknowledges BA status as long as it copies frames to host
54 * buffer (or rx fifo). This can incorrectly acknowledge packets
55 * to a sender if last desc is self-linked.
57 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
59 struct ath_hw *ah = sc->sc_ah;
60 struct ath_common *common = ath9k_hw_common(ah);
67 ds->ds_link = 0; /* link to null */
68 ds->ds_data = bf->bf_buf_addr;
70 /* virtual addr of the beginning of the buffer. */
73 ds->ds_vdata = skb->data;
76 * setup rx descriptors. The rx_bufsize here tells the hardware
77 * how much data it can DMA to us and that we are prepared
80 ath9k_hw_setuprxdesc(ah, ds,
84 if (sc->rx.rxlink == NULL)
85 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
87 *sc->rx.rxlink = bf->bf_daddr;
89 sc->rx.rxlink = &ds->ds_link;
93 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
95 /* XXX block beacon interrupts */
96 ath9k_hw_setantenna(sc->sc_ah, antenna);
97 sc->rx.defant = antenna;
98 sc->rx.rxotherant = 0;
101 static void ath_opmode_init(struct ath_softc *sc)
103 struct ath_hw *ah = sc->sc_ah;
104 struct ath_common *common = ath9k_hw_common(ah);
108 /* configure rx filter */
109 rfilt = ath_calcrxfilter(sc);
110 ath9k_hw_setrxfilter(ah, rfilt);
112 /* configure bssid mask */
113 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
114 ath_hw_setbssidmask(common);
116 /* configure operational mode */
117 ath9k_hw_setopmode(ah);
119 /* calculate and install multicast filter */
120 mfilt[0] = mfilt[1] = ~0;
121 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
124 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
125 enum ath9k_rx_qtype qtype)
127 struct ath_hw *ah = sc->sc_ah;
128 struct ath_rx_edma *rx_edma;
132 rx_edma = &sc->rx.rx_edma[qtype];
133 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
136 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
137 list_del_init(&bf->list);
142 memset(skb->data, 0, ah->caps.rx_status_len);
143 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
144 ah->caps.rx_status_len, DMA_TO_DEVICE);
146 SKB_CB_ATHBUF(skb) = bf;
147 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
148 skb_queue_tail(&rx_edma->rx_fifo, skb);
153 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
154 enum ath9k_rx_qtype qtype, int size)
156 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
159 if (list_empty(&sc->rx.rxbuf)) {
160 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
164 while (!list_empty(&sc->rx.rxbuf)) {
167 if (!ath_rx_edma_buf_link(sc, qtype))
175 static void ath_rx_remove_buffer(struct ath_softc *sc,
176 enum ath9k_rx_qtype qtype)
179 struct ath_rx_edma *rx_edma;
182 rx_edma = &sc->rx.rx_edma[qtype];
184 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
185 bf = SKB_CB_ATHBUF(skb);
187 list_add_tail(&bf->list, &sc->rx.rxbuf);
191 static void ath_rx_edma_cleanup(struct ath_softc *sc)
195 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
196 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
198 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
200 dev_kfree_skb_any(bf->bf_mpdu);
203 INIT_LIST_HEAD(&sc->rx.rxbuf);
205 kfree(sc->rx.rx_bufptr);
206 sc->rx.rx_bufptr = NULL;
209 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
211 skb_queue_head_init(&rx_edma->rx_fifo);
212 skb_queue_head_init(&rx_edma->rx_buffers);
213 rx_edma->rx_fifo_hwsize = size;
216 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
218 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
219 struct ath_hw *ah = sc->sc_ah;
226 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
227 ah->caps.rx_status_len,
228 min(common->cachelsz, (u16)64));
230 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
231 ah->caps.rx_status_len);
233 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
234 ah->caps.rx_lp_qdepth);
235 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
236 ah->caps.rx_hp_qdepth);
238 size = sizeof(struct ath_buf) * nbufs;
239 bf = kzalloc(size, GFP_KERNEL);
243 INIT_LIST_HEAD(&sc->rx.rxbuf);
244 sc->rx.rx_bufptr = bf;
246 for (i = 0; i < nbufs; i++, bf++) {
247 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
253 memset(skb->data, 0, common->rx_bufsize);
256 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
259 if (unlikely(dma_mapping_error(sc->dev,
261 dev_kfree_skb_any(skb);
263 ath_print(common, ATH_DBG_FATAL,
264 "dma_mapping_error() on RX init\n");
269 list_add_tail(&bf->list, &sc->rx.rxbuf);
275 ath_rx_edma_cleanup(sc);
279 static void ath_edma_start_recv(struct ath_softc *sc)
281 spin_lock_bh(&sc->rx.rxbuflock);
283 ath9k_hw_rxena(sc->sc_ah);
285 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
286 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
288 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
289 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
291 spin_unlock_bh(&sc->rx.rxbuflock);
295 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_SCANNING));
298 static void ath_edma_stop_recv(struct ath_softc *sc)
300 spin_lock_bh(&sc->rx.rxbuflock);
301 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
302 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
303 spin_unlock_bh(&sc->rx.rxbuflock);
306 int ath_rx_init(struct ath_softc *sc, int nbufs)
308 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
313 spin_lock_init(&sc->rx.rxflushlock);
314 sc->sc_flags &= ~SC_OP_RXFLUSH;
315 spin_lock_init(&sc->rx.rxbuflock);
317 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
318 return ath_rx_edma_init(sc, nbufs);
320 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
321 min(common->cachelsz, (u16)64));
323 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
324 common->cachelsz, common->rx_bufsize);
326 /* Initialize rx descriptors */
328 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
331 ath_print(common, ATH_DBG_FATAL,
332 "failed to allocate rx descriptors: %d\n",
337 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
338 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
346 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
349 if (unlikely(dma_mapping_error(sc->dev,
351 dev_kfree_skb_any(skb);
353 ath_print(common, ATH_DBG_FATAL,
354 "dma_mapping_error() on RX init\n");
358 bf->bf_dmacontext = bf->bf_buf_addr;
360 sc->rx.rxlink = NULL;
370 void ath_rx_cleanup(struct ath_softc *sc)
372 struct ath_hw *ah = sc->sc_ah;
373 struct ath_common *common = ath9k_hw_common(ah);
377 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
378 ath_rx_edma_cleanup(sc);
381 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
384 dma_unmap_single(sc->dev, bf->bf_buf_addr,
391 if (sc->rx.rxdma.dd_desc_len != 0)
392 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
397 * Calculate the receive filter according to the
398 * operating mode and state:
400 * o always accept unicast, broadcast, and multicast traffic
401 * o maintain current state of phy error reception (the hal
402 * may enable phy error frames for noise immunity work)
403 * o probe request frames are accepted only when operating in
404 * hostap, adhoc, or monitor modes
405 * o enable promiscuous mode according to the interface state
407 * - when operating in adhoc mode so the 802.11 layer creates
408 * node table entries for peers,
409 * - when operating in station mode for collecting rssi data when
410 * the station is otherwise quiet, or
411 * - when operating as a repeater so we see repeater-sta beacons
415 u32 ath_calcrxfilter(struct ath_softc *sc)
417 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
421 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
422 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
423 | ATH9K_RX_FILTER_MCAST;
425 /* If not a STA, enable processing of Probe Requests */
426 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
427 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
430 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
431 * mode interface or when in monitor mode. AP mode does not need this
432 * since it receives all in-BSS frames anyway.
434 if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
435 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
436 (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
437 rfilt |= ATH9K_RX_FILTER_PROM;
439 if (sc->rx.rxfilter & FIF_CONTROL)
440 rfilt |= ATH9K_RX_FILTER_CONTROL;
442 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
443 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
444 rfilt |= ATH9K_RX_FILTER_MYBEACON;
446 rfilt |= ATH9K_RX_FILTER_BEACON;
448 if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
449 AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
450 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
451 (sc->rx.rxfilter & FIF_PSPOLL))
452 rfilt |= ATH9K_RX_FILTER_PSPOLL;
454 if (conf_is_ht(&sc->hw->conf))
455 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
457 if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
458 /* TODO: only needed if more than one BSSID is in use in
459 * station/adhoc mode */
460 /* The following may also be needed for other older chips */
461 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
462 rfilt |= ATH9K_RX_FILTER_PROM;
463 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
468 #undef RX_FILTER_PRESERVE
471 int ath_startrecv(struct ath_softc *sc)
473 struct ath_hw *ah = sc->sc_ah;
474 struct ath_buf *bf, *tbf;
476 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
477 ath_edma_start_recv(sc);
481 spin_lock_bh(&sc->rx.rxbuflock);
482 if (list_empty(&sc->rx.rxbuf))
485 sc->rx.rxlink = NULL;
486 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
487 ath_rx_buf_link(sc, bf);
490 /* We could have deleted elements so the list may be empty now */
491 if (list_empty(&sc->rx.rxbuf))
494 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
495 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
499 spin_unlock_bh(&sc->rx.rxbuflock);
501 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_SCANNING));
506 bool ath_stoprecv(struct ath_softc *sc)
508 struct ath_hw *ah = sc->sc_ah;
511 ath9k_hw_stoppcurecv(ah);
512 ath9k_hw_setrxfilter(ah, 0);
513 stopped = ath9k_hw_stopdmarecv(ah);
515 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
516 ath_edma_stop_recv(sc);
518 sc->rx.rxlink = NULL;
523 void ath_flushrecv(struct ath_softc *sc)
525 spin_lock_bh(&sc->rx.rxflushlock);
526 sc->sc_flags |= SC_OP_RXFLUSH;
527 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
528 ath_rx_tasklet(sc, 1, true);
529 ath_rx_tasklet(sc, 1, false);
530 sc->sc_flags &= ~SC_OP_RXFLUSH;
531 spin_unlock_bh(&sc->rx.rxflushlock);
534 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
536 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
537 struct ieee80211_mgmt *mgmt;
538 u8 *pos, *end, id, elen;
539 struct ieee80211_tim_ie *tim;
541 mgmt = (struct ieee80211_mgmt *)skb->data;
542 pos = mgmt->u.beacon.variable;
543 end = skb->data + skb->len;
545 while (pos + 2 < end) {
548 if (pos + elen > end)
551 if (id == WLAN_EID_TIM) {
552 if (elen < sizeof(*tim))
554 tim = (struct ieee80211_tim_ie *) pos;
555 if (tim->dtim_count != 0)
557 return tim->bitmap_ctrl & 0x01;
566 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
568 struct ieee80211_mgmt *mgmt;
569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
571 if (skb->len < 24 + 8 + 2 + 2)
574 mgmt = (struct ieee80211_mgmt *)skb->data;
575 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
576 return; /* not from our current AP */
578 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
580 if (sc->ps_flags & PS_BEACON_SYNC) {
581 sc->ps_flags &= ~PS_BEACON_SYNC;
582 ath_print(common, ATH_DBG_PS,
583 "Reconfigure Beacon timers based on "
584 "timestamp from the AP\n");
585 ath_beacon_config(sc, NULL);
588 if (ath_beacon_dtim_pending_cab(skb)) {
590 * Remain awake waiting for buffered broadcast/multicast
591 * frames. If the last broadcast/multicast frame is not
592 * received properly, the next beacon frame will work as
593 * a backup trigger for returning into NETWORK SLEEP state,
594 * so we are waiting for it as well.
596 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
597 "buffered broadcast/multicast frame(s)\n");
598 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
602 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
604 * This can happen if a broadcast frame is dropped or the AP
605 * fails to send a frame indicating that all CAB frames have
608 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
609 ath_print(common, ATH_DBG_PS,
610 "PS wait for CAB frames timed out\n");
614 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
616 struct ieee80211_hdr *hdr;
617 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
619 hdr = (struct ieee80211_hdr *)skb->data;
621 /* Process Beacon and CAB receive in PS state */
622 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
623 && ieee80211_is_beacon(hdr->frame_control))
624 ath_rx_ps_beacon(sc, skb);
625 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
626 (ieee80211_is_data(hdr->frame_control) ||
627 ieee80211_is_action(hdr->frame_control)) &&
628 is_multicast_ether_addr(hdr->addr1) &&
629 !ieee80211_has_moredata(hdr->frame_control)) {
631 * No more broadcast/multicast frames to be received at this
634 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
635 ath_print(common, ATH_DBG_PS,
636 "All PS CAB frames received, back to sleep\n");
637 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
638 !is_multicast_ether_addr(hdr->addr1) &&
639 !ieee80211_has_morefrags(hdr->frame_control)) {
640 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
641 ath_print(common, ATH_DBG_PS,
642 "Going back to sleep after having received "
643 "PS-Poll data (0x%lx)\n",
644 sc->ps_flags & (PS_WAIT_FOR_BEACON |
646 PS_WAIT_FOR_PSPOLL_DATA |
647 PS_WAIT_FOR_TX_ACK));
651 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
652 struct ath_softc *sc, struct sk_buff *skb,
653 struct ieee80211_rx_status *rxs)
655 struct ieee80211_hdr *hdr;
657 hdr = (struct ieee80211_hdr *)skb->data;
659 /* Send the frame to mac80211 */
660 if (is_multicast_ether_addr(hdr->addr1)) {
663 * Deliver broadcast/multicast frames to all suitable
666 /* TODO: filter based on channel configuration */
667 for (i = 0; i < sc->num_sec_wiphy; i++) {
668 struct ath_wiphy *aphy = sc->sec_wiphy[i];
669 struct sk_buff *nskb;
672 nskb = skb_copy(skb, GFP_ATOMIC);
675 ieee80211_rx(aphy->hw, nskb);
677 ieee80211_rx(sc->hw, skb);
679 /* Deliver unicast frames based on receiver address */
680 ieee80211_rx(hw, skb);
683 static bool ath_edma_get_buffers(struct ath_softc *sc,
684 enum ath9k_rx_qtype qtype)
686 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
687 struct ath_hw *ah = sc->sc_ah;
688 struct ath_common *common = ath9k_hw_common(ah);
693 skb = skb_peek(&rx_edma->rx_fifo);
697 bf = SKB_CB_ATHBUF(skb);
700 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
701 common->rx_bufsize, DMA_FROM_DEVICE);
703 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
704 if (ret == -EINPROGRESS) {
705 /*let device gain the buffer again*/
706 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
707 common->rx_bufsize, DMA_FROM_DEVICE);
711 __skb_unlink(skb, &rx_edma->rx_fifo);
712 if (ret == -EINVAL) {
713 /* corrupt descriptor, skip this one and the following one */
714 list_add_tail(&bf->list, &sc->rx.rxbuf);
715 ath_rx_edma_buf_link(sc, qtype);
716 skb = skb_peek(&rx_edma->rx_fifo);
720 bf = SKB_CB_ATHBUF(skb);
723 __skb_unlink(skb, &rx_edma->rx_fifo);
724 list_add_tail(&bf->list, &sc->rx.rxbuf);
725 ath_rx_edma_buf_link(sc, qtype);
728 skb_queue_tail(&rx_edma->rx_buffers, skb);
733 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
734 struct ath_rx_status *rs,
735 enum ath9k_rx_qtype qtype)
737 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
741 while (ath_edma_get_buffers(sc, qtype));
742 skb = __skb_dequeue(&rx_edma->rx_buffers);
746 bf = SKB_CB_ATHBUF(skb);
747 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
751 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
752 struct ath_rx_status *rs)
754 struct ath_hw *ah = sc->sc_ah;
755 struct ath_common *common = ath9k_hw_common(ah);
760 if (list_empty(&sc->rx.rxbuf)) {
761 sc->rx.rxlink = NULL;
765 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
769 * Must provide the virtual address of the current
770 * descriptor, the physical address, and the virtual
771 * address of the next descriptor in the h/w chain.
772 * This allows the HAL to look ahead to see if the
773 * hardware is done with a descriptor by checking the
774 * done bit in the following descriptor and the address
775 * of the current descriptor the DMA engine is working
776 * on. All this is necessary because of our use of
777 * a self-linked list to avoid rx overruns.
779 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
780 if (ret == -EINPROGRESS) {
781 struct ath_rx_status trs;
783 struct ath_desc *tds;
785 memset(&trs, 0, sizeof(trs));
786 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
787 sc->rx.rxlink = NULL;
791 tbf = list_entry(bf->list.next, struct ath_buf, list);
794 * On some hardware the descriptor status words could
795 * get corrupted, including the done bit. Because of
796 * this, check if the next descriptor's done bit is
799 * If the next descriptor's done bit is set, the current
800 * descriptor has been corrupted. Force s/w to discard
801 * this descriptor and continue...
805 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
806 if (ret == -EINPROGRESS)
814 * Synchronize the DMA transfer with CPU before
815 * 1. accessing the frame
816 * 2. requeueing the same buffer to h/w
818 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
825 /* Assumes you've already done the endian to CPU conversion */
826 static bool ath9k_rx_accept(struct ath_common *common,
827 struct ieee80211_hdr *hdr,
828 struct ieee80211_rx_status *rxs,
829 struct ath_rx_status *rx_stats,
832 struct ath_hw *ah = common->ah;
834 u8 rx_status_len = ah->caps.rx_status_len;
836 fc = hdr->frame_control;
838 if (!rx_stats->rs_datalen)
841 * rs_status follows rs_datalen so if rs_datalen is too large
842 * we can take a hint that hardware corrupted it, so ignore
845 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
849 * rs_more indicates chained descriptors which can be used
850 * to link buffers together for a sort of scatter-gather
852 * reject the frame, we don't support scatter-gather yet and
853 * the frame is probably corrupt anyway
855 if (rx_stats->rs_more)
859 * The rx_stats->rs_status will not be set until the end of the
860 * chained descriptors so it can be ignored if rs_more is set. The
861 * rs_more will be false at the last element of the chained
864 if (rx_stats->rs_status != 0) {
865 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
866 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
867 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
870 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
871 *decrypt_error = true;
872 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
874 * The MIC error bit is only valid if the frame
875 * is not a control frame or fragment, and it was
876 * decrypted using a valid TKIP key.
878 if (!ieee80211_is_ctl(fc) &&
879 !ieee80211_has_morefrags(fc) &&
880 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
881 test_bit(rx_stats->rs_keyix, common->tkip_keymap))
882 rxs->flag |= RX_FLAG_MMIC_ERROR;
884 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
887 * Reject error frames with the exception of
888 * decryption and MIC failures. For monitor mode,
889 * we also ignore the CRC error.
891 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
892 if (rx_stats->rs_status &
893 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
897 if (rx_stats->rs_status &
898 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
906 static int ath9k_process_rate(struct ath_common *common,
907 struct ieee80211_hw *hw,
908 struct ath_rx_status *rx_stats,
909 struct ieee80211_rx_status *rxs)
911 struct ieee80211_supported_band *sband;
912 enum ieee80211_band band;
915 band = hw->conf.channel->band;
916 sband = hw->wiphy->bands[band];
918 if (rx_stats->rs_rate & 0x80) {
920 rxs->flag |= RX_FLAG_HT;
921 if (rx_stats->rs_flags & ATH9K_RX_2040)
922 rxs->flag |= RX_FLAG_40MHZ;
923 if (rx_stats->rs_flags & ATH9K_RX_GI)
924 rxs->flag |= RX_FLAG_SHORT_GI;
925 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
929 for (i = 0; i < sband->n_bitrates; i++) {
930 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
934 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
935 rxs->flag |= RX_FLAG_SHORTPRE;
942 * No valid hardware bitrate found -- we should not get here
943 * because hardware has already validated this frame as OK.
945 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
946 "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
951 static void ath9k_process_rssi(struct ath_common *common,
952 struct ieee80211_hw *hw,
953 struct ieee80211_hdr *hdr,
954 struct ath_rx_status *rx_stats)
956 struct ath_hw *ah = common->ah;
957 struct ieee80211_sta *sta;
959 int last_rssi = ATH_RSSI_DUMMY_MARKER;
962 fc = hdr->frame_control;
966 * XXX: use ieee80211_find_sta! This requires quite a bit of work
967 * under the current ath9k virtual wiphy implementation as we have
968 * no way of tying a vif to wiphy. Typically vifs are attached to
969 * at least one sdata of a wiphy on mac80211 but with ath9k virtual
970 * wiphy you'd have to iterate over every wiphy and each sdata.
972 sta = ieee80211_find_sta_by_hw(hw, hdr->addr2);
974 an = (struct ath_node *) sta->drv_priv;
975 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
976 !rx_stats->rs_moreaggr)
977 ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
978 last_rssi = an->last_rssi;
982 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
983 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
984 ATH_RSSI_EP_MULTIPLIER);
985 if (rx_stats->rs_rssi < 0)
986 rx_stats->rs_rssi = 0;
988 /* Update Beacon RSSI, this is used by ANI. */
989 if (ieee80211_is_beacon(fc))
990 ah->stats.avgbrssi = rx_stats->rs_rssi;
994 * For Decrypt or Demic errors, we only mark packet status here and always push
995 * up the frame up to let mac80211 handle the actual error case, be it no
996 * decryption key or real decryption error. This let us keep statistics there.
998 static int ath9k_rx_skb_preprocess(struct ath_common *common,
999 struct ieee80211_hw *hw,
1000 struct ieee80211_hdr *hdr,
1001 struct ath_rx_status *rx_stats,
1002 struct ieee80211_rx_status *rx_status,
1003 bool *decrypt_error)
1005 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1008 * everything but the rate is checked here, the rate check is done
1009 * separately to avoid doing two lookups for a rate for each frame.
1011 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1014 ath9k_process_rssi(common, hw, hdr, rx_stats);
1016 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1019 rx_status->band = hw->conf.channel->band;
1020 rx_status->freq = hw->conf.channel->center_freq;
1021 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1022 rx_status->antenna = rx_stats->rs_antenna;
1023 rx_status->flag |= RX_FLAG_TSFT;
1028 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1029 struct sk_buff *skb,
1030 struct ath_rx_status *rx_stats,
1031 struct ieee80211_rx_status *rxs,
1034 struct ath_hw *ah = common->ah;
1035 struct ieee80211_hdr *hdr;
1036 int hdrlen, padpos, padsize;
1040 /* see if any padding is done by the hw and remove it */
1041 hdr = (struct ieee80211_hdr *) skb->data;
1042 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1043 fc = hdr->frame_control;
1044 padpos = ath9k_cmn_padpos(hdr->frame_control);
1046 /* The MAC header is padded to have 32-bit boundary if the
1047 * packet payload is non-zero. The general calculation for
1048 * padsize would take into account odd header lengths:
1049 * padsize = (4 - padpos % 4) % 4; However, since only
1050 * even-length headers are used, padding can only be 0 or 2
1051 * bytes and we can optimize this a bit. In addition, we must
1052 * not try to remove padding from short control frames that do
1053 * not have payload. */
1054 padsize = padpos & 3;
1055 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1056 memmove(skb->data + padsize, skb->data, padpos);
1057 skb_pull(skb, padsize);
1060 keyix = rx_stats->rs_keyix;
1062 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1063 ieee80211_has_protected(fc)) {
1064 rxs->flag |= RX_FLAG_DECRYPTED;
1065 } else if (ieee80211_has_protected(fc)
1066 && !decrypt_error && skb->len >= hdrlen + 4) {
1067 keyix = skb->data[hdrlen + 3] >> 6;
1069 if (test_bit(keyix, common->keymap))
1070 rxs->flag |= RX_FLAG_DECRYPTED;
1072 if (ah->sw_mgmt_crypto &&
1073 (rxs->flag & RX_FLAG_DECRYPTED) &&
1074 ieee80211_is_mgmt(fc))
1075 /* Use software decrypt for management frames. */
1076 rxs->flag &= ~RX_FLAG_DECRYPTED;
1079 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1082 struct sk_buff *skb = NULL, *requeue_skb;
1083 struct ieee80211_rx_status *rxs;
1084 struct ath_hw *ah = sc->sc_ah;
1085 struct ath_common *common = ath9k_hw_common(ah);
1087 * The hw can techncically differ from common->hw when using ath9k
1088 * virtual wiphy so to account for that we iterate over the active
1089 * wiphys and find the appropriate wiphy and therefore hw.
1091 struct ieee80211_hw *hw = NULL;
1092 struct ieee80211_hdr *hdr;
1094 bool decrypt_error = false;
1095 struct ath_rx_status rs;
1096 enum ath9k_rx_qtype qtype;
1097 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1099 u8 rx_status_len = ah->caps.rx_status_len;
1104 dma_type = DMA_BIDIRECTIONAL;
1106 dma_type = DMA_FROM_DEVICE;
1108 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1109 spin_lock_bh(&sc->rx.rxbuflock);
1111 tsf = ath9k_hw_gettsf64(ah);
1112 tsf_lower = tsf & 0xffffffff;
1115 /* If handling rx interrupt and flush is in progress => exit */
1116 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1119 memset(&rs, 0, sizeof(rs));
1121 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1123 bf = ath_get_next_rx_buf(sc, &rs);
1132 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1133 rxs = IEEE80211_SKB_RXCB(skb);
1135 hw = ath_get_virt_hw(sc, hdr);
1137 ath_debug_stat_rx(sc, &rs);
1140 * If we're asked to flush receive queue, directly
1141 * chain it back at the queue without processing it.
1146 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1147 rxs, &decrypt_error);
1151 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1152 if (rs.rs_tstamp > tsf_lower &&
1153 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1154 rxs->mactime -= 0x100000000ULL;
1156 if (rs.rs_tstamp < tsf_lower &&
1157 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1158 rxs->mactime += 0x100000000ULL;
1160 /* Ensure we always have an skb to requeue once we are done
1161 * processing the current buffer's skb */
1162 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1164 /* If there is no memory we ignore the current RX'd frame,
1165 * tell hardware it can give us a new frame using the old
1166 * skb and put it at the tail of the sc->rx.rxbuf list for
1171 /* Unmap the frame */
1172 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1176 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1177 if (ah->caps.rx_status_len)
1178 skb_pull(skb, ah->caps.rx_status_len);
1180 ath9k_rx_skb_postprocess(common, skb, &rs,
1181 rxs, decrypt_error);
1183 /* We will now give hardware our shiny new allocated skb */
1184 bf->bf_mpdu = requeue_skb;
1185 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1188 if (unlikely(dma_mapping_error(sc->dev,
1189 bf->bf_buf_addr))) {
1190 dev_kfree_skb_any(requeue_skb);
1192 ath_print(common, ATH_DBG_FATAL,
1193 "dma_mapping_error() on RX\n");
1194 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1197 bf->bf_dmacontext = bf->bf_buf_addr;
1200 * change the default rx antenna if rx diversity chooses the
1201 * other antenna 3 times in a row.
1203 if (sc->rx.defant != rs.rs_antenna) {
1204 if (++sc->rx.rxotherant >= 3)
1205 ath_setdefantenna(sc, rs.rs_antenna);
1207 sc->rx.rxotherant = 0;
1210 if (unlikely(ath9k_check_auto_sleep(sc) ||
1211 (sc->ps_flags & (PS_WAIT_FOR_BEACON |
1213 PS_WAIT_FOR_PSPOLL_DATA))))
1216 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1220 list_add_tail(&bf->list, &sc->rx.rxbuf);
1221 ath_rx_edma_buf_link(sc, qtype);
1223 list_move_tail(&bf->list, &sc->rx.rxbuf);
1224 ath_rx_buf_link(sc, bf);
1228 spin_unlock_bh(&sc->rx.rxbuflock);