drivers/net/wireless/ath/ath9k/recv.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18 #include "ar9003_mac.h"
  19
  20 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
  21
  22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
  23                                                int mindelta, int main_rssi_avg,
  24                                                int alt_rssi_avg, int pkt_count)
  25 {
  26         return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  27                 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
  28                 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
  29 }
  30
  31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  32 {
  33         return sc->ps_enabled &&
  34                (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  35 }
  36
  37 /*
  38  * Setup and link descriptors.
  39  *
  40  * 11N: we can no longer afford to self link the last descriptor.
  41  * MAC acknowledges BA status as long as it copies frames to host
  42  * buffer (or rx fifo). This can incorrectly acknowledge packets
  43  * to a sender if last desc is self-linked.
  44  */
  45 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  46 {
  47         struct ath_hw *ah = sc->sc_ah;
  48         struct ath_common *common = ath9k_hw_common(ah);
  49         struct ath_desc *ds;
  50         struct sk_buff *skb;
  51
  52         ATH_RXBUF_RESET(bf);
  53
  54         ds = bf->bf_desc;
  55         ds->ds_link = 0; /* link to null */
  56         ds->ds_data = bf->bf_buf_addr;
  57
  58         /* virtual addr of the beginning of the buffer. */
  59         skb = bf->bf_mpdu;
  60         BUG_ON(skb == NULL);
  61         ds->ds_vdata = skb->data;
  62
  63         /*
  64          * setup rx descriptors. The rx_bufsize here tells the hardware
  65          * how much data it can DMA to us and that we are prepared
  66          * to process
  67          */
  68         ath9k_hw_setuprxdesc(ah, ds,
  69                              common->rx_bufsize,
  70                              0);
  71
  72         if (sc->rx.rxlink == NULL)
  73                 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  74         else
  75                 *sc->rx.rxlink = bf->bf_daddr;
  76
  77         sc->rx.rxlink = &ds->ds_link;
  78 }
  79
  80 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  81 {
  82         /* XXX block beacon interrupts */
  83         ath9k_hw_setantenna(sc->sc_ah, antenna);
  84         sc->rx.defant = antenna;
  85         sc->rx.rxotherant = 0;
  86 }
  87
  88 static void ath_opmode_init(struct ath_softc *sc)
  89 {
  90         struct ath_hw *ah = sc->sc_ah;
  91         struct ath_common *common = ath9k_hw_common(ah);
  92
  93         u32 rfilt, mfilt[2];
  94
  95         /* configure rx filter */
  96         rfilt = ath_calcrxfilter(sc);
  97         ath9k_hw_setrxfilter(ah, rfilt);
  98
  99         /* configure bssid mask */
 100         ath_hw_setbssidmask(common);
 101
 102         /* configure operational mode */
 103         ath9k_hw_setopmode(ah);
 104
 105         /* calculate and install multicast filter */
 106         mfilt[0] = mfilt[1] = ~0;
 107         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
 108 }
 109
 110 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
 111                                  enum ath9k_rx_qtype qtype)
 112 {
 113         struct ath_hw *ah = sc->sc_ah;
 114         struct ath_rx_edma *rx_edma;
 115         struct sk_buff *skb;
 116         struct ath_buf *bf;
 117
 118         rx_edma = &sc->rx.rx_edma[qtype];
 119         if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
 120                 return false;
 121
 122         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 123         list_del_init(&bf->list);
 124
 125         skb = bf->bf_mpdu;
 126
 127         ATH_RXBUF_RESET(bf);
 128         memset(skb->data, 0, ah->caps.rx_status_len);
 129         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 130                                 ah->caps.rx_status_len, DMA_TO_DEVICE);
 131
 132         SKB_CB_ATHBUF(skb) = bf;
 133         ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
 134         skb_queue_tail(&rx_edma->rx_fifo, skb);
 135
 136         return true;
 137 }
 138
 139 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
 140                                   enum ath9k_rx_qtype qtype, int size)
 141 {
 142         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 143         u32 nbuf = 0;
 144
 145         if (list_empty(&sc->rx.rxbuf)) {
 146                 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
 147                 return;
 148         }
 149
 150         while (!list_empty(&sc->rx.rxbuf)) {
 151                 nbuf++;
 152
 153                 if (!ath_rx_edma_buf_link(sc, qtype))
 154                         break;
 155
 156                 if (nbuf >= size)
 157                         break;
 158         }
 159 }
 160
 161 static void ath_rx_remove_buffer(struct ath_softc *sc,
 162                                  enum ath9k_rx_qtype qtype)
 163 {
 164         struct ath_buf *bf;
 165         struct ath_rx_edma *rx_edma;
 166         struct sk_buff *skb;
 167
 168         rx_edma = &sc->rx.rx_edma[qtype];
 169
 170         while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
 171                 bf = SKB_CB_ATHBUF(skb);
 172                 BUG_ON(!bf);
 173                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 174         }
 175 }
 176
 177 static void ath_rx_edma_cleanup(struct ath_softc *sc)
 178 {
 179         struct ath_buf *bf;
 180
 181         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 182         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 183
 184         list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 185                 if (bf->bf_mpdu)
 186                         dev_kfree_skb_any(bf->bf_mpdu);
 187         }
 188
 189         INIT_LIST_HEAD(&sc->rx.rxbuf);
 190
 191         kfree(sc->rx.rx_bufptr);
 192         sc->rx.rx_bufptr = NULL;
 193 }
 194
 195 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
 196 {
 197         skb_queue_head_init(&rx_edma->rx_fifo);
 198         skb_queue_head_init(&rx_edma->rx_buffers);
 199         rx_edma->rx_fifo_hwsize = size;
 200 }
 201
 202 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
 203 {
 204         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 205         struct ath_hw *ah = sc->sc_ah;
 206         struct sk_buff *skb;
 207         struct ath_buf *bf;
 208         int error = 0, i;
 209         u32 size;
 210
 211         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 212                                     ah->caps.rx_status_len);
 213
 214         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
 215                                ah->caps.rx_lp_qdepth);
 216         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
 217                                ah->caps.rx_hp_qdepth);
 218
 219         size = sizeof(struct ath_buf) * nbufs;
 220         bf = kzalloc(size, GFP_KERNEL);
 221         if (!bf)
 222                 return -ENOMEM;
 223
 224         INIT_LIST_HEAD(&sc->rx.rxbuf);
 225         sc->rx.rx_bufptr = bf;
 226
 227         for (i = 0; i < nbufs; i++, bf++) {
 228                 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
 229                 if (!skb) {
 230                         error = -ENOMEM;
 231                         goto rx_init_fail;
 232                 }
 233
 234                 memset(skb->data, 0, common->rx_bufsize);
 235                 bf->bf_mpdu = skb;
 236
 237                 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 238                                                  common->rx_bufsize,
 239                                                  DMA_BIDIRECTIONAL);
 240                 if (unlikely(dma_mapping_error(sc->dev,
 241                                                 bf->bf_buf_addr))) {
 242                                 dev_kfree_skb_any(skb);
 243                                 bf->bf_mpdu = NULL;
 244                                 bf->bf_buf_addr = 0;
 245                                 ath_err(common,
 246                                         "dma_mapping_error() on RX init\n");
 247                                 error = -ENOMEM;
 248                                 goto rx_init_fail;
 249                 }
 250
 251                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 252         }
 253
 254         return 0;
 255
 256 rx_init_fail:
 257         ath_rx_edma_cleanup(sc);
 258         return error;
 259 }
 260
 261 static void ath_edma_start_recv(struct ath_softc *sc)
 262 {
 263         spin_lock_bh(&sc->rx.rxbuflock);
 264
 265         ath9k_hw_rxena(sc->sc_ah);
 266
 267         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
 268                               sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
 269
 270         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
 271                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
 272
 273         ath_opmode_init(sc);
 274
 275         ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
 276
 277         spin_unlock_bh(&sc->rx.rxbuflock);
 278 }
 279
 280 static void ath_edma_stop_recv(struct ath_softc *sc)
 281 {
 282         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 283         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 284 }
 285
 286 int ath_rx_init(struct ath_softc *sc, int nbufs)
 287 {
 288         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 289         struct sk_buff *skb;
 290         struct ath_buf *bf;
 291         int error = 0;
 292
 293         spin_lock_init(&sc->sc_pcu_lock);
 294         sc->sc_flags &= ~SC_OP_RXFLUSH;
 295         spin_lock_init(&sc->rx.rxbuflock);
 296
 297         common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
 298                              sc->sc_ah->caps.rx_status_len;
 299
 300         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 301                 return ath_rx_edma_init(sc, nbufs);
 302         } else {
 303                 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
 304                         common->cachelsz, common->rx_bufsize);
 305
 306                 /* Initialize rx descriptors */
 307
 308                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
 309                                 "rx", nbufs, 1, 0);
 310                 if (error != 0) {
 311                         ath_err(common,
 312                                 "failed to allocate rx descriptors: %d\n",
 313                                 error);
 314                         goto err;
 315                 }
 316
 317                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 318                         skb = ath_rxbuf_alloc(common, common->rx_bufsize,
 319                                               GFP_KERNEL);
 320                         if (skb == NULL) {
 321                                 error = -ENOMEM;
 322                                 goto err;
 323                         }
 324
 325                         bf->bf_mpdu = skb;
 326                         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 327                                         common->rx_bufsize,
 328                                         DMA_FROM_DEVICE);
 329                         if (unlikely(dma_mapping_error(sc->dev,
 330                                                         bf->bf_buf_addr))) {
 331                                 dev_kfree_skb_any(skb);
 332                                 bf->bf_mpdu = NULL;
 333                                 bf->bf_buf_addr = 0;
 334                                 ath_err(common,
 335                                         "dma_mapping_error() on RX init\n");
 336                                 error = -ENOMEM;
 337                                 goto err;
 338                         }
 339                 }
 340                 sc->rx.rxlink = NULL;
 341         }
 342
 343 err:
 344         if (error)
 345                 ath_rx_cleanup(sc);
 346
 347         return error;
 348 }
 349
 350 void ath_rx_cleanup(struct ath_softc *sc)
 351 {
 352         struct ath_hw *ah = sc->sc_ah;
 353         struct ath_common *common = ath9k_hw_common(ah);
 354         struct sk_buff *skb;
 355         struct ath_buf *bf;
 356
 357         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 358                 ath_rx_edma_cleanup(sc);
 359                 return;
 360         } else {
 361                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 362                         skb = bf->bf_mpdu;
 363                         if (skb) {
 364                                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
 365                                                 common->rx_bufsize,
 366                                                 DMA_FROM_DEVICE);
 367                                 dev_kfree_skb(skb);
 368                                 bf->bf_buf_addr = 0;
 369                                 bf->bf_mpdu = NULL;
 370                         }
 371                 }
 372
 373                 if (sc->rx.rxdma.dd_desc_len != 0)
 374                         ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
 375         }
 376 }
 377
 378 /*
 379  * Calculate the receive filter according to the
 380  * operating mode and state:
 381  *
 382  * o always accept unicast, broadcast, and multicast traffic
 383  * o maintain current state of phy error reception (the hal
 384  *   may enable phy error frames for noise immunity work)
 385  * o probe request frames are accepted only when operating in
 386  *   hostap, adhoc, or monitor modes
 387  * o enable promiscuous mode according to the interface state
 388  * o accept beacons:
 389  *   - when operating in adhoc mode so the 802.11 layer creates
 390  *     node table entries for peers,
 391  *   - when operating in station mode for collecting rssi data when
 392  *     the station is otherwise quiet, or
 393  *   - when operating as a repeater so we see repeater-sta beacons
 394  *   - when scanning
 395  */
 396
 397 u32 ath_calcrxfilter(struct ath_softc *sc)
 398 {
 399 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
 400
 401         u32 rfilt;
 402
 403         rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
 404                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
 405                 | ATH9K_RX_FILTER_MCAST;
 406
 407         if (sc->rx.rxfilter & FIF_PROBE_REQ)
 408                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 409
 410         /*
 411          * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
 412          * mode interface or when in monitor mode. AP mode does not need this
 413          * since it receives all in-BSS frames anyway.
 414          */
 415         if (sc->sc_ah->is_monitoring)
 416                 rfilt |= ATH9K_RX_FILTER_PROM;
 417
 418         if (sc->rx.rxfilter & FIF_CONTROL)
 419                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 420
 421         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
 422             (sc->nvifs <= 1) &&
 423             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
 424                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
 425         else
 426                 rfilt |= ATH9K_RX_FILTER_BEACON;
 427
 428         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
 429             (sc->rx.rxfilter & FIF_PSPOLL))
 430                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 431
 432         if (conf_is_ht(&sc->hw->conf))
 433                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
 434
 435         if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
 436                 /* The following may also be needed for other older chips */
 437                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
 438                         rfilt |= ATH9K_RX_FILTER_PROM;
 439                 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
 440         }
 441
 442         return rfilt;
 443
 444 #undef RX_FILTER_PRESERVE
 445 }
 446
 447 int ath_startrecv(struct ath_softc *sc)
 448 {
 449         struct ath_hw *ah = sc->sc_ah;
 450         struct ath_buf *bf, *tbf;
 451
 452         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 453                 ath_edma_start_recv(sc);
 454                 return 0;
 455         }
 456
 457         spin_lock_bh(&sc->rx.rxbuflock);
 458         if (list_empty(&sc->rx.rxbuf))
 459                 goto start_recv;
 460
 461         sc->rx.rxlink = NULL;
 462         list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
 463                 ath_rx_buf_link(sc, bf);
 464         }
 465
 466         /* We could have deleted elements so the list may be empty now */
 467         if (list_empty(&sc->rx.rxbuf))
 468                 goto start_recv;
 469
 470         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 471         ath9k_hw_putrxbuf(ah, bf->bf_daddr);
 472         ath9k_hw_rxena(ah);
 473
 474 start_recv:
 475         ath_opmode_init(sc);
 476         ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
 477
 478         spin_unlock_bh(&sc->rx.rxbuflock);
 479
 480         return 0;
 481 }
 482
 483 bool ath_stoprecv(struct ath_softc *sc)
 484 {
 485         struct ath_hw *ah = sc->sc_ah;
 486         bool stopped;
 487
 488         spin_lock_bh(&sc->rx.rxbuflock);
 489         ath9k_hw_abortpcurecv(ah);
 490         ath9k_hw_setrxfilter(ah, 0);
 491         stopped = ath9k_hw_stopdmarecv(ah);
 492
 493         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 494                 ath_edma_stop_recv(sc);
 495         else
 496                 sc->rx.rxlink = NULL;
 497         spin_unlock_bh(&sc->rx.rxbuflock);
 498
 499         if (!(ah->ah_flags & AH_UNPLUGGED) &&
 500             unlikely(!stopped)) {
 501                 ath_err(ath9k_hw_common(sc->sc_ah),
 502                         "Could not stop RX, we could be "
 503                         "confusing the DMA engine when we start RX up\n");
 504                 ATH_DBG_WARN_ON_ONCE(!stopped);
 505         }
 506         return stopped;
 507 }
 508
 509 void ath_flushrecv(struct ath_softc *sc)
 510 {
 511         sc->sc_flags |= SC_OP_RXFLUSH;
 512         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 513                 ath_rx_tasklet(sc, 1, true);
 514         ath_rx_tasklet(sc, 1, false);
 515         sc->sc_flags &= ~SC_OP_RXFLUSH;
 516 }
 517
 518 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
 519 {
 520         /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
 521         struct ieee80211_mgmt *mgmt;
 522         u8 *pos, *end, id, elen;
 523         struct ieee80211_tim_ie *tim;
 524
 525         mgmt = (struct ieee80211_mgmt *)skb->data;
 526         pos = mgmt->u.beacon.variable;
 527         end = skb->data + skb->len;
 528
 529         while (pos + 2 < end) {
 530                 id = *pos++;
 531                 elen = *pos++;
 532                 if (pos + elen > end)
 533                         break;
 534
 535                 if (id == WLAN_EID_TIM) {
 536                         if (elen < sizeof(*tim))
 537                                 break;
 538                         tim = (struct ieee80211_tim_ie *) pos;
 539                         if (tim->dtim_count != 0)
 540                                 break;
 541                         return tim->bitmap_ctrl & 0x01;
 542                 }
 543
 544                 pos += elen;
 545         }
 546
 547         return false;
 548 }
 549
 550 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
 551 {
 552         struct ieee80211_mgmt *mgmt;
 553         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 554
 555         if (skb->len < 24 + 8 + 2 + 2)
 556                 return;
 557
 558         mgmt = (struct ieee80211_mgmt *)skb->data;
 559         if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
 560                 /* TODO:  This doesn't work well if you have stations
 561                  * associated to two different APs because curbssid
 562                  * is just the last AP that any of the stations associated
 563                  * with.
 564                  */
 565                 return; /* not from our current AP */
 566         }
 567
 568         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
 569
 570         if (sc->ps_flags & PS_BEACON_SYNC) {
 571                 sc->ps_flags &= ~PS_BEACON_SYNC;
 572                 ath_dbg(common, ATH_DBG_PS,
 573                         "Reconfigure Beacon timers based on timestamp from the AP\n");
 574                 ath_set_beacon(sc);
 575         }
 576
 577         if (ath_beacon_dtim_pending_cab(skb)) {
 578                 /*
 579                  * Remain awake waiting for buffered broadcast/multicast
 580                  * frames. If the last broadcast/multicast frame is not
 581                  * received properly, the next beacon frame will work as
 582                  * a backup trigger for returning into NETWORK SLEEP state,
 583                  * so we are waiting for it as well.
 584                  */
 585                 ath_dbg(common, ATH_DBG_PS,
 586                         "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
 587                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
 588                 return;
 589         }
 590
 591         if (sc->ps_flags & PS_WAIT_FOR_CAB) {
 592                 /*
 593                  * This can happen if a broadcast frame is dropped or the AP
 594                  * fails to send a frame indicating that all CAB frames have
 595                  * been delivered.
 596                  */
 597                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
 598                 ath_dbg(common, ATH_DBG_PS,
 599                         "PS wait for CAB frames timed out\n");
 600         }
 601 }
 602
 603 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
 604 {
 605         struct ieee80211_hdr *hdr;
 606         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 607
 608         hdr = (struct ieee80211_hdr *)skb->data;
 609
 610         /* Process Beacon and CAB receive in PS state */
 611         if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
 612             && ieee80211_is_beacon(hdr->frame_control))
 613                 ath_rx_ps_beacon(sc, skb);
 614         else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
 615                  (ieee80211_is_data(hdr->frame_control) ||
 616                   ieee80211_is_action(hdr->frame_control)) &&
 617                  is_multicast_ether_addr(hdr->addr1) &&
 618                  !ieee80211_has_moredata(hdr->frame_control)) {
 619                 /*
 620                  * No more broadcast/multicast frames to be received at this
 621                  * point.
 622                  */
 623                 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
 624                 ath_dbg(common, ATH_DBG_PS,
 625                         "All PS CAB frames received, back to sleep\n");
 626         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
 627                    !is_multicast_ether_addr(hdr->addr1) &&
 628                    !ieee80211_has_morefrags(hdr->frame_control)) {
 629                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
 630                 ath_dbg(common, ATH_DBG_PS,
 631                         "Going back to sleep after having received PS-Poll data (0x%lx)\n",
 632                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
 633                                         PS_WAIT_FOR_CAB |
 634                                         PS_WAIT_FOR_PSPOLL_DATA |
 635                                         PS_WAIT_FOR_TX_ACK));
 636         }
 637 }
 638
 639 static bool ath_edma_get_buffers(struct ath_softc *sc,
 640                                  enum ath9k_rx_qtype qtype)
 641 {
 642         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 643         struct ath_hw *ah = sc->sc_ah;
 644         struct ath_common *common = ath9k_hw_common(ah);
 645         struct sk_buff *skb;
 646         struct ath_buf *bf;
 647         int ret;
 648
 649         skb = skb_peek(&rx_edma->rx_fifo);
 650         if (!skb)
 651                 return false;
 652
 653         bf = SKB_CB_ATHBUF(skb);
 654         BUG_ON(!bf);
 655
 656         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
 657                                 common->rx_bufsize, DMA_FROM_DEVICE);
 658
 659         ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
 660         if (ret == -EINPROGRESS) {
 661                 /*let device gain the buffer again*/
 662                 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 663                                 common->rx_bufsize, DMA_FROM_DEVICE);
 664                 return false;
 665         }
 666
 667         __skb_unlink(skb, &rx_edma->rx_fifo);
 668         if (ret == -EINVAL) {
 669                 /* corrupt descriptor, skip this one and the following one */
 670                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 671                 ath_rx_edma_buf_link(sc, qtype);
 672                 skb = skb_peek(&rx_edma->rx_fifo);
 673                 if (!skb)
 674                         return true;
 675
 676                 bf = SKB_CB_ATHBUF(skb);
 677                 BUG_ON(!bf);
 678
 679                 __skb_unlink(skb, &rx_edma->rx_fifo);
 680                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 681                 ath_rx_edma_buf_link(sc, qtype);
 682                 return true;
 683         }
 684         skb_queue_tail(&rx_edma->rx_buffers, skb);
 685
 686         return true;
 687 }
 688
 689 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
 690                                                 struct ath_rx_status *rs,
 691                                                 enum ath9k_rx_qtype qtype)
 692 {
 693         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 694         struct sk_buff *skb;
 695         struct ath_buf *bf;
 696
 697         while (ath_edma_get_buffers(sc, qtype));
 698         skb = __skb_dequeue(&rx_edma->rx_buffers);
 699         if (!skb)
 700                 return NULL;
 701
 702         bf = SKB_CB_ATHBUF(skb);
 703         ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
 704         return bf;
 705 }
 706
 707 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
 708                                            struct ath_rx_status *rs)
 709 {
 710         struct ath_hw *ah = sc->sc_ah;
 711         struct ath_common *common = ath9k_hw_common(ah);
 712         struct ath_desc *ds;
 713         struct ath_buf *bf;
 714         int ret;
 715
 716         if (list_empty(&sc->rx.rxbuf)) {
 717                 sc->rx.rxlink = NULL;
 718                 return NULL;
 719         }
 720
 721         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 722         ds = bf->bf_desc;
 723
 724         /*
 725          * Must provide the virtual address of the current
 726          * descriptor, the physical address, and the virtual
 727          * address of the next descriptor in the h/w chain.
 728          * This allows the HAL to look ahead to see if the
 729          * hardware is done with a descriptor by checking the
 730          * done bit in the following descriptor and the address
 731          * of the current descriptor the DMA engine is working
 732          * on.  All this is necessary because of our use of
 733          * a self-linked list to avoid rx overruns.
 734          */
 735         ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
 736         if (ret == -EINPROGRESS) {
 737                 struct ath_rx_status trs;
 738                 struct ath_buf *tbf;
 739                 struct ath_desc *tds;
 740
 741                 memset(&trs, 0, sizeof(trs));
 742                 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
 743                         sc->rx.rxlink = NULL;
 744                         return NULL;
 745                 }
 746
 747                 tbf = list_entry(bf->list.next, struct ath_buf, list);
 748
 749                 /*
 750                  * On some hardware the descriptor status words could
 751                  * get corrupted, including the done bit. Because of
 752                  * this, check if the next descriptor's done bit is
 753                  * set or not.
 754                  *
 755                  * If the next descriptor's done bit is set, the current
 756                  * descriptor has been corrupted. Force s/w to discard
 757                  * this descriptor and continue...
 758                  */
 759
 760                 tds = tbf->bf_desc;
 761                 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
 762                 if (ret == -EINPROGRESS)
 763                         return NULL;
 764         }
 765
 766         if (!bf->bf_mpdu)
 767                 return bf;
 768
 769         /*
 770          * Synchronize the DMA transfer with CPU before
 771          * 1. accessing the frame
 772          * 2. requeueing the same buffer to h/w
 773          */
 774         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
 775                         common->rx_bufsize,
 776                         DMA_FROM_DEVICE);
 777
 778         return bf;
 779 }
 780
 781 /* Assumes you've already done the endian to CPU conversion */
 782 static bool ath9k_rx_accept(struct ath_common *common,
 783                             struct ieee80211_hdr *hdr,
 784                             struct ieee80211_rx_status *rxs,
 785                             struct ath_rx_status *rx_stats,
 786                             bool *decrypt_error)
 787 {
 788 #define is_mc_or_valid_tkip_keyix ((is_mc ||                    \
 789                 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
 790                 test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
 791
 792         struct ath_hw *ah = common->ah;
 793         __le16 fc;
 794         u8 rx_status_len = ah->caps.rx_status_len;
 795
 796         fc = hdr->frame_control;
 797
 798         if (!rx_stats->rs_datalen)
 799                 return false;
 800         /*
 801          * rs_status follows rs_datalen so if rs_datalen is too large
 802          * we can take a hint that hardware corrupted it, so ignore
 803          * those frames.
 804          */
 805         if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
 806                 return false;
 807
 808         /* Only use error bits from the last fragment */
 809         if (rx_stats->rs_more)
 810                 return true;
 811
 812         /*
 813          * The rx_stats->rs_status will not be set until the end of the
 814          * chained descriptors so it can be ignored if rs_more is set. The
 815          * rs_more will be false at the last element of the chained
 816          * descriptors.
 817          */
 818         if (rx_stats->rs_status != 0) {
 819                 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
 820                         rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
 821                 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
 822                         return false;
 823
 824                 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
 825                         *decrypt_error = true;
 826                 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
 827                         bool is_mc;
 828                         /*
 829                          * The MIC error bit is only valid if the frame
 830                          * is not a control frame or fragment, and it was
 831                          * decrypted using a valid TKIP key.
 832                          */
 833                         is_mc = !!is_multicast_ether_addr(hdr->addr1);
 834
 835                         if (!ieee80211_is_ctl(fc) &&
 836                             !ieee80211_has_morefrags(fc) &&
 837                             !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
 838                             is_mc_or_valid_tkip_keyix)
 839                                 rxs->flag |= RX_FLAG_MMIC_ERROR;
 840                         else
 841                                 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
 842                 }
 843                 /*
 844                  * Reject error frames with the exception of
 845                  * decryption and MIC failures. For monitor mode,
 846                  * we also ignore the CRC error.
 847                  */
 848                 if (ah->is_monitoring) {
 849                         if (rx_stats->rs_status &
 850                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
 851                               ATH9K_RXERR_CRC))
 852                                 return false;
 853                 } else {
 854                         if (rx_stats->rs_status &
 855                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
 856                                 return false;
 857                         }
 858                 }
 859         }
 860         return true;
 861 }
 862
 863 static int ath9k_process_rate(struct ath_common *common,
 864                               struct ieee80211_hw *hw,
 865                               struct ath_rx_status *rx_stats,
 866                               struct ieee80211_rx_status *rxs)
 867 {
 868         struct ieee80211_supported_band *sband;
 869         enum ieee80211_band band;
 870         unsigned int i = 0;
 871
 872         band = hw->conf.channel->band;
 873         sband = hw->wiphy->bands[band];
 874
 875         if (rx_stats->rs_rate & 0x80) {
 876                 /* HT rate */
 877                 rxs->flag |= RX_FLAG_HT;
 878                 if (rx_stats->rs_flags & ATH9K_RX_2040)
 879                         rxs->flag |= RX_FLAG_40MHZ;
 880                 if (rx_stats->rs_flags & ATH9K_RX_GI)
 881                         rxs->flag |= RX_FLAG_SHORT_GI;
 882                 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
 883                 return 0;
 884         }
 885
 886         for (i = 0; i < sband->n_bitrates; i++) {
 887                 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
 888                         rxs->rate_idx = i;
 889                         return 0;
 890                 }
 891                 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
 892                         rxs->flag |= RX_FLAG_SHORTPRE;
 893                         rxs->rate_idx = i;
 894                         return 0;
 895                 }
 896         }
 897
 898         /*
 899          * No valid hardware bitrate found -- we should not get here
 900          * because hardware has already validated this frame as OK.
 901          */
 902         ath_dbg(common, ATH_DBG_XMIT,
 903                 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
 904                 rx_stats->rs_rate);
 905
 906         return -EINVAL;
 907 }
 908
 909 static void ath9k_process_rssi(struct ath_common *common,
 910                                struct ieee80211_hw *hw,
 911                                struct ieee80211_hdr *hdr,
 912                                struct ath_rx_status *rx_stats)
 913 {
 914         struct ath_softc *sc = hw->priv;
 915         struct ath_hw *ah = common->ah;
 916         int last_rssi;
 917         __le16 fc;
 918
 919         if (ah->opmode != NL80211_IFTYPE_STATION)
 920                 return;
 921
 922         fc = hdr->frame_control;
 923         if (!ieee80211_is_beacon(fc) ||
 924             compare_ether_addr(hdr->addr3, common->curbssid)) {
 925                 /* TODO:  This doesn't work well if you have stations
 926                  * associated to two different APs because curbssid
 927                  * is just the last AP that any of the stations associated
 928                  * with.
 929                  */
 930                 return;
 931         }
 932
 933         if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
 934                 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
 935
 936         last_rssi = sc->last_rssi;
 937         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
 938                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
 939                                               ATH_RSSI_EP_MULTIPLIER);
 940         if (rx_stats->rs_rssi < 0)
 941                 rx_stats->rs_rssi = 0;
 942
 943         /* Update Beacon RSSI, this is used by ANI. */
 944         ah->stats.avgbrssi = rx_stats->rs_rssi;
 945 }
 946
 947 /*
 948  * For Decrypt or Demic errors, we only mark packet status here and always push
 949  * up the frame up to let mac80211 handle the actual error case, be it no
 950  * decryption key or real decryption error. This let us keep statistics there.
 951  */
 952 static int ath9k_rx_skb_preprocess(struct ath_common *common,
 953                                    struct ieee80211_hw *hw,
 954                                    struct ieee80211_hdr *hdr,
 955                                    struct ath_rx_status *rx_stats,
 956                                    struct ieee80211_rx_status *rx_status,
 957                                    bool *decrypt_error)
 958 {
 959         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
 960
 961         /*
 962          * everything but the rate is checked here, the rate check is done
 963          * separately to avoid doing two lookups for a rate for each frame.
 964          */
 965         if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
 966                 return -EINVAL;
 967
 968         /* Only use status info from the last fragment */
 969         if (rx_stats->rs_more)
 970                 return 0;
 971
 972         ath9k_process_rssi(common, hw, hdr, rx_stats);
 973
 974         if (ath9k_process_rate(common, hw, rx_stats, rx_status))
 975                 return -EINVAL;
 976
 977         rx_status->band = hw->conf.channel->band;
 978         rx_status->freq = hw->conf.channel->center_freq;
 979         rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
 980         rx_status->antenna = rx_stats->rs_antenna;
 981         rx_status->flag |= RX_FLAG_MACTIME_MPDU;
 982
 983         return 0;
 984 }
 985
 986 static void ath9k_rx_skb_postprocess(struct ath_common *common,
 987                                      struct sk_buff *skb,
 988                                      struct ath_rx_status *rx_stats,
 989                                      struct ieee80211_rx_status *rxs,
 990                                      bool decrypt_error)
 991 {
 992         struct ath_hw *ah = common->ah;
 993         struct ieee80211_hdr *hdr;
 994         int hdrlen, padpos, padsize;
 995         u8 keyix;
 996         __le16 fc;
 997
 998         /* see if any padding is done by the hw and remove it */
 999         hdr = (struct ieee80211_hdr *) skb->data;
1000         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1001         fc = hdr->frame_control;
1002         padpos = ath9k_cmn_padpos(hdr->frame_control);
1003
1004         /* The MAC header is padded to have 32-bit boundary if the
1005          * packet payload is non-zero. The general calculation for
1006          * padsize would take into account odd header lengths:
1007          * padsize = (4 - padpos % 4) % 4; However, since only
1008          * even-length headers are used, padding can only be 0 or 2
1009          * bytes and we can optimize this a bit. In addition, we must
1010          * not try to remove padding from short control frames that do
1011          * not have payload. */
1012         padsize = padpos & 3;
1013         if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1014                 memmove(skb->data + padsize, skb->data, padpos);
1015                 skb_pull(skb, padsize);
1016         }
1017
1018         keyix = rx_stats->rs_keyix;
1019
1020         if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1021             ieee80211_has_protected(fc)) {
1022                 rxs->flag |= RX_FLAG_DECRYPTED;
1023         } else if (ieee80211_has_protected(fc)
1024                    && !decrypt_error && skb->len >= hdrlen + 4) {
1025                 keyix = skb->data[hdrlen + 3] >> 6;
1026
1027                 if (test_bit(keyix, common->keymap))
1028                         rxs->flag |= RX_FLAG_DECRYPTED;
1029         }
1030         if (ah->sw_mgmt_crypto &&
1031             (rxs->flag & RX_FLAG_DECRYPTED) &&
1032             ieee80211_is_mgmt(fc))
1033                 /* Use software decrypt for management frames. */
1034                 rxs->flag &= ~RX_FLAG_DECRYPTED;
1035 }
1036
1037 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1038                                       struct ath_hw_antcomb_conf ant_conf,
1039                                       int main_rssi_avg)
1040 {
1041         antcomb->quick_scan_cnt = 0;
1042
1043         if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1044                 antcomb->rssi_lna2 = main_rssi_avg;
1045         else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1046                 antcomb->rssi_lna1 = main_rssi_avg;
1047
1048         switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1049         case (0x10): /* LNA2 A-B */
1050                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1051                 antcomb->first_quick_scan_conf =
1052                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1053                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1054                 break;
1055         case (0x20): /* LNA1 A-B */
1056                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1057                 antcomb->first_quick_scan_conf =
1058                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1059                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1060                 break;
1061         case (0x21): /* LNA1 LNA2 */
1062                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1063                 antcomb->first_quick_scan_conf =
1064                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1065                 antcomb->second_quick_scan_conf =
1066                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1067                 break;
1068         case (0x12): /* LNA2 LNA1 */
1069                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1070                 antcomb->first_quick_scan_conf =
1071                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1072                 antcomb->second_quick_scan_conf =
1073                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1074                 break;
1075         case (0x13): /* LNA2 A+B */
1076                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1077                 antcomb->first_quick_scan_conf =
1078                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1079                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1080                 break;
1081         case (0x23): /* LNA1 A+B */
1082                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1083                 antcomb->first_quick_scan_conf =
1084                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1085                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1086                 break;
1087         default:
1088                 break;
1089         }
1090 }
1091
1092 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1093                                 struct ath_hw_antcomb_conf *div_ant_conf,
1094                                 int main_rssi_avg, int alt_rssi_avg,
1095                                 int alt_ratio)
1096 {
1097         /* alt_good */
1098         switch (antcomb->quick_scan_cnt) {
1099         case 0:
1100                 /* set alt to main, and alt to first conf */
1101                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1102                 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1103                 break;
1104         case 1:
1105                 /* set alt to main, and alt to first conf */
1106                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1107                 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1108                 antcomb->rssi_first = main_rssi_avg;
1109                 antcomb->rssi_second = alt_rssi_avg;
1110
1111                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1112                         /* main is LNA1 */
1113                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1114                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1115                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1116                                                 main_rssi_avg, alt_rssi_avg,
1117                                                 antcomb->total_pkt_count))
1118                                 antcomb->first_ratio = true;
1119                         else
1120                                 antcomb->first_ratio = false;
1121                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1122                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1123                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1124                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1125                                                 main_rssi_avg, alt_rssi_avg,
1126                                                 antcomb->total_pkt_count))
1127                                 antcomb->first_ratio = true;
1128                         else
1129                                 antcomb->first_ratio = false;
1130                 } else {
1131                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1132                             (alt_rssi_avg > main_rssi_avg +
1133                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1134                             (alt_rssi_avg > main_rssi_avg)) &&
1135                             (antcomb->total_pkt_count > 50))
1136                                 antcomb->first_ratio = true;
1137                         else
1138                                 antcomb->first_ratio = false;
1139                 }
1140                 break;
1141         case 2:
1142                 antcomb->alt_good = false;
1143                 antcomb->scan_not_start = false;
1144                 antcomb->scan = false;
1145                 antcomb->rssi_first = main_rssi_avg;
1146                 antcomb->rssi_third = alt_rssi_avg;
1147
1148                 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1149                         antcomb->rssi_lna1 = alt_rssi_avg;
1150                 else if (antcomb->second_quick_scan_conf ==
1151                          ATH_ANT_DIV_COMB_LNA2)
1152                         antcomb->rssi_lna2 = alt_rssi_avg;
1153                 else if (antcomb->second_quick_scan_conf ==
1154                          ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1155                         if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1156                                 antcomb->rssi_lna2 = main_rssi_avg;
1157                         else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1158                                 antcomb->rssi_lna1 = main_rssi_avg;
1159                 }
1160
1161                 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1162                     ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1163                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1164                 else
1165                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1166
1167                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1168                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1169                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1170                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1171                                                 main_rssi_avg, alt_rssi_avg,
1172                                                 antcomb->total_pkt_count))
1173                                 antcomb->second_ratio = true;
1174                         else
1175                                 antcomb->second_ratio = false;
1176                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1177                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1178                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1179                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1180                                                 main_rssi_avg, alt_rssi_avg,
1181                                                 antcomb->total_pkt_count))
1182                                 antcomb->second_ratio = true;
1183                         else
1184                                 antcomb->second_ratio = false;
1185                 } else {
1186                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1187                             (alt_rssi_avg > main_rssi_avg +
1188                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1189                             (alt_rssi_avg > main_rssi_avg)) &&
1190                             (antcomb->total_pkt_count > 50))
1191                                 antcomb->second_ratio = true;
1192                         else
1193                                 antcomb->second_ratio = false;
1194                 }
1195
1196                 /* set alt to the conf with maximun ratio */
1197                 if (antcomb->first_ratio && antcomb->second_ratio) {
1198                         if (antcomb->rssi_second > antcomb->rssi_third) {
1199                                 /* first alt*/
1200                                 if ((antcomb->first_quick_scan_conf ==
1201                                     ATH_ANT_DIV_COMB_LNA1) ||
1202                                     (antcomb->first_quick_scan_conf ==
1203                                     ATH_ANT_DIV_COMB_LNA2))
1204                                         /* Set alt LNA1 or LNA2*/
1205                                         if (div_ant_conf->main_lna_conf ==
1206                                             ATH_ANT_DIV_COMB_LNA2)
1207                                                 div_ant_conf->alt_lna_conf =
1208                                                         ATH_ANT_DIV_COMB_LNA1;
1209                                         else
1210                                                 div_ant_conf->alt_lna_conf =
1211                                                         ATH_ANT_DIV_COMB_LNA2;
1212                                 else
1213                                         /* Set alt to A+B or A-B */
1214                                         div_ant_conf->alt_lna_conf =
1215                                                 antcomb->first_quick_scan_conf;
1216                         } else if ((antcomb->second_quick_scan_conf ==
1217                                    ATH_ANT_DIV_COMB_LNA1) ||
1218                                    (antcomb->second_quick_scan_conf ==
1219                                    ATH_ANT_DIV_COMB_LNA2)) {
1220                                 /* Set alt LNA1 or LNA2 */
1221                                 if (div_ant_conf->main_lna_conf ==
1222                                     ATH_ANT_DIV_COMB_LNA2)
1223                                         div_ant_conf->alt_lna_conf =
1224                                                 ATH_ANT_DIV_COMB_LNA1;
1225                                 else
1226                                         div_ant_conf->alt_lna_conf =
1227                                                 ATH_ANT_DIV_COMB_LNA2;
1228                         } else {
1229                                 /* Set alt to A+B or A-B */
1230                                 div_ant_conf->alt_lna_conf =
1231                                         antcomb->second_quick_scan_conf;
1232                         }
1233                 } else if (antcomb->first_ratio) {
1234                         /* first alt */
1235                         if ((antcomb->first_quick_scan_conf ==
1236                             ATH_ANT_DIV_COMB_LNA1) ||
1237                             (antcomb->first_quick_scan_conf ==
1238                             ATH_ANT_DIV_COMB_LNA2))
1239                                         /* Set alt LNA1 or LNA2 */
1240                                 if (div_ant_conf->main_lna_conf ==
1241                                     ATH_ANT_DIV_COMB_LNA2)
1242                                         div_ant_conf->alt_lna_conf =
1243                                                         ATH_ANT_DIV_COMB_LNA1;
1244                                 else
1245                                         div_ant_conf->alt_lna_conf =
1246                                                         ATH_ANT_DIV_COMB_LNA2;
1247                         else
1248                                 /* Set alt to A+B or A-B */
1249                                 div_ant_conf->alt_lna_conf =
1250                                                 antcomb->first_quick_scan_conf;
1251                 } else if (antcomb->second_ratio) {
1252                                 /* second alt */
1253                         if ((antcomb->second_quick_scan_conf ==
1254                             ATH_ANT_DIV_COMB_LNA1) ||
1255                             (antcomb->second_quick_scan_conf ==
1256                             ATH_ANT_DIV_COMB_LNA2))
1257                                 /* Set alt LNA1 or LNA2 */
1258                                 if (div_ant_conf->main_lna_conf ==
1259                                     ATH_ANT_DIV_COMB_LNA2)
1260                                         div_ant_conf->alt_lna_conf =
1261                                                 ATH_ANT_DIV_COMB_LNA1;
1262                                 else
1263                                         div_ant_conf->alt_lna_conf =
1264                                                 ATH_ANT_DIV_COMB_LNA2;
1265                         else
1266                                 /* Set alt to A+B or A-B */
1267                                 div_ant_conf->alt_lna_conf =
1268                                                 antcomb->second_quick_scan_conf;
1269                 } else {
1270                         /* main is largest */
1271                         if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1272                             (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1273                                 /* Set alt LNA1 or LNA2 */
1274                                 if (div_ant_conf->main_lna_conf ==
1275                                     ATH_ANT_DIV_COMB_LNA2)
1276                                         div_ant_conf->alt_lna_conf =
1277                                                         ATH_ANT_DIV_COMB_LNA1;
1278                                 else
1279                                         div_ant_conf->alt_lna_conf =
1280                                                         ATH_ANT_DIV_COMB_LNA2;
1281                         else
1282                                 /* Set alt to A+B or A-B */
1283                                 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1284                 }
1285                 break;
1286         default:
1287                 break;
1288         }
1289 }
1290
1291 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1292 {
1293         /* Adjust the fast_div_bias based on main and alt lna conf */
1294         switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1295         case (0x01): /* A-B LNA2 */
1296                 ant_conf->fast_div_bias = 0x3b;
1297                 break;
1298         case (0x02): /* A-B LNA1 */
1299                 ant_conf->fast_div_bias = 0x3d;
1300                 break;
1301         case (0x03): /* A-B A+B */
1302                 ant_conf->fast_div_bias = 0x1;
1303                 break;
1304         case (0x10): /* LNA2 A-B */
1305                 ant_conf->fast_div_bias = 0x7;
1306                 break;
1307         case (0x12): /* LNA2 LNA1 */
1308                 ant_conf->fast_div_bias = 0x2;
1309                 break;
1310         case (0x13): /* LNA2 A+B */
1311                 ant_conf->fast_div_bias = 0x7;
1312                 break;
1313         case (0x20): /* LNA1 A-B */
1314                 ant_conf->fast_div_bias = 0x6;
1315                 break;
1316         case (0x21): /* LNA1 LNA2 */
1317                 ant_conf->fast_div_bias = 0x0;
1318                 break;
1319         case (0x23): /* LNA1 A+B */
1320                 ant_conf->fast_div_bias = 0x6;
1321                 break;
1322         case (0x30): /* A+B A-B */
1323                 ant_conf->fast_div_bias = 0x1;
1324                 break;
1325         case (0x31): /* A+B LNA2 */
1326                 ant_conf->fast_div_bias = 0x3b;
1327                 break;
1328         case (0x32): /* A+B LNA1 */
1329                 ant_conf->fast_div_bias = 0x3d;
1330                 break;
1331         default:
1332                 break;
1333         }
1334 }
1335
1336 /* Antenna diversity and combining */
1337 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1338 {
1339         struct ath_hw_antcomb_conf div_ant_conf;
1340         struct ath_ant_comb *antcomb = &sc->ant_comb;
1341         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1342         int curr_main_set, curr_bias;
1343         int main_rssi = rs->rs_rssi_ctl0;
1344         int alt_rssi = rs->rs_rssi_ctl1;
1345         int rx_ant_conf,  main_ant_conf;
1346         bool short_scan = false;
1347
1348         rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1349                        ATH_ANT_RX_MASK;
1350         main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1351                          ATH_ANT_RX_MASK;
1352
1353         /* Record packet only when alt_rssi is positive */
1354         if (alt_rssi > 0) {
1355                 antcomb->total_pkt_count++;
1356                 antcomb->main_total_rssi += main_rssi;
1357                 antcomb->alt_total_rssi  += alt_rssi;
1358                 if (main_ant_conf == rx_ant_conf)
1359                         antcomb->main_recv_cnt++;
1360                 else
1361                         antcomb->alt_recv_cnt++;
1362         }
1363
1364         /* Short scan check */
1365         if (antcomb->scan && antcomb->alt_good) {
1366                 if (time_after(jiffies, antcomb->scan_start_time +
1367                     msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1368                         short_scan = true;
1369                 else
1370                         if (antcomb->total_pkt_count ==
1371                             ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1372                                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1373                                             antcomb->total_pkt_count);
1374                                 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1375                                         short_scan = true;
1376                         }
1377         }
1378
1379         if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1380             rs->rs_moreaggr) && !short_scan)
1381                 return;
1382
1383         if (antcomb->total_pkt_count) {
1384                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1385                              antcomb->total_pkt_count);
1386                 main_rssi_avg = (antcomb->main_total_rssi /
1387                                  antcomb->total_pkt_count);
1388                 alt_rssi_avg = (antcomb->alt_total_rssi /
1389                                  antcomb->total_pkt_count);
1390         }
1391
1392
1393         ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1394         curr_alt_set = div_ant_conf.alt_lna_conf;
1395         curr_main_set = div_ant_conf.main_lna_conf;
1396         curr_bias = div_ant_conf.fast_div_bias;
1397
1398         antcomb->count++;
1399
1400         if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1401                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1402                         ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1403                                                   main_rssi_avg);
1404                         antcomb->alt_good = true;
1405                 } else {
1406                         antcomb->alt_good = false;
1407                 }
1408
1409                 antcomb->count = 0;
1410                 antcomb->scan = true;
1411                 antcomb->scan_not_start = true;
1412         }
1413
1414         if (!antcomb->scan) {
1415                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1416                         if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1417                                 /* Switch main and alt LNA */
1418                                 div_ant_conf.main_lna_conf =
1419                                                 ATH_ANT_DIV_COMB_LNA2;
1420                                 div_ant_conf.alt_lna_conf  =
1421                                                 ATH_ANT_DIV_COMB_LNA1;
1422                         } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1423                                 div_ant_conf.main_lna_conf =
1424                                                 ATH_ANT_DIV_COMB_LNA1;
1425                                 div_ant_conf.alt_lna_conf  =
1426                                                 ATH_ANT_DIV_COMB_LNA2;
1427                         }
1428
1429                         goto div_comb_done;
1430                 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1431                            (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1432                         /* Set alt to another LNA */
1433                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1434                                 div_ant_conf.alt_lna_conf =
1435                                                 ATH_ANT_DIV_COMB_LNA1;
1436                         else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1437                                 div_ant_conf.alt_lna_conf =
1438                                                 ATH_ANT_DIV_COMB_LNA2;
1439
1440                         goto div_comb_done;
1441                 }
1442
1443                 if ((alt_rssi_avg < (main_rssi_avg +
1444                     ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1445                         goto div_comb_done;
1446         }
1447
1448         if (!antcomb->scan_not_start) {
1449                 switch (curr_alt_set) {
1450                 case ATH_ANT_DIV_COMB_LNA2:
1451                         antcomb->rssi_lna2 = alt_rssi_avg;
1452                         antcomb->rssi_lna1 = main_rssi_avg;
1453                         antcomb->scan = true;
1454                         /* set to A+B */
1455                         div_ant_conf.main_lna_conf =
1456                                 ATH_ANT_DIV_COMB_LNA1;
1457                         div_ant_conf.alt_lna_conf  =
1458                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1459                         break;
1460                 case ATH_ANT_DIV_COMB_LNA1:
1461                         antcomb->rssi_lna1 = alt_rssi_avg;
1462                         antcomb->rssi_lna2 = main_rssi_avg;
1463                         antcomb->scan = true;
1464                         /* set to A+B */
1465                         div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1466                         div_ant_conf.alt_lna_conf  =
1467                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1468                         break;
1469                 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1470                         antcomb->rssi_add = alt_rssi_avg;
1471                         antcomb->scan = true;
1472                         /* set to A-B */
1473                         div_ant_conf.alt_lna_conf =
1474                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1475                         break;
1476                 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1477                         antcomb->rssi_sub = alt_rssi_avg;
1478                         antcomb->scan = false;
1479                         if (antcomb->rssi_lna2 >
1480                             (antcomb->rssi_lna1 +
1481                             ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1482                                 /* use LNA2 as main LNA */
1483                                 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1484                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1485                                         /* set to A+B */
1486                                         div_ant_conf.main_lna_conf =
1487                                                 ATH_ANT_DIV_COMB_LNA2;
1488                                         div_ant_conf.alt_lna_conf  =
1489                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1490                                 } else if (antcomb->rssi_sub >
1491                                            antcomb->rssi_lna1) {
1492                                         /* set to A-B */
1493                                         div_ant_conf.main_lna_conf =
1494                                                 ATH_ANT_DIV_COMB_LNA2;
1495                                         div_ant_conf.alt_lna_conf =
1496                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1497                                 } else {
1498                                         /* set to LNA1 */
1499                                         div_ant_conf.main_lna_conf =
1500                                                 ATH_ANT_DIV_COMB_LNA2;
1501                                         div_ant_conf.alt_lna_conf =
1502                                                 ATH_ANT_DIV_COMB_LNA1;
1503                                 }
1504                         } else {
1505                                 /* use LNA1 as main LNA */
1506                                 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1507                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1508                                         /* set to A+B */
1509                                         div_ant_conf.main_lna_conf =
1510                                                 ATH_ANT_DIV_COMB_LNA1;
1511                                         div_ant_conf.alt_lna_conf  =
1512                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1513                                 } else if (antcomb->rssi_sub >
1514                                            antcomb->rssi_lna1) {
1515                                         /* set to A-B */
1516                                         div_ant_conf.main_lna_conf =
1517                                                 ATH_ANT_DIV_COMB_LNA1;
1518                                         div_ant_conf.alt_lna_conf =
1519                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1520                                 } else {
1521                                         /* set to LNA2 */
1522                                         div_ant_conf.main_lna_conf =
1523                                                 ATH_ANT_DIV_COMB_LNA1;
1524                                         div_ant_conf.alt_lna_conf =
1525                                                 ATH_ANT_DIV_COMB_LNA2;
1526                                 }
1527                         }
1528                         break;
1529                 default:
1530                         break;
1531                 }
1532         } else {
1533                 if (!antcomb->alt_good) {
1534                         antcomb->scan_not_start = false;
1535                         /* Set alt to another LNA */
1536                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1537                                 div_ant_conf.main_lna_conf =
1538                                                 ATH_ANT_DIV_COMB_LNA2;
1539                                 div_ant_conf.alt_lna_conf =
1540                                                 ATH_ANT_DIV_COMB_LNA1;
1541                         } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1542                                 div_ant_conf.main_lna_conf =
1543                                                 ATH_ANT_DIV_COMB_LNA1;
1544                                 div_ant_conf.alt_lna_conf =
1545                                                 ATH_ANT_DIV_COMB_LNA2;
1546                         }
1547                         goto div_comb_done;
1548                 }
1549         }
1550
1551         ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1552                                            main_rssi_avg, alt_rssi_avg,
1553                                            alt_ratio);
1554
1555         antcomb->quick_scan_cnt++;
1556
1557 div_comb_done:
1558         ath_ant_div_conf_fast_divbias(&div_ant_conf);
1559
1560         ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1561
1562         antcomb->scan_start_time = jiffies;
1563         antcomb->total_pkt_count = 0;
1564         antcomb->main_total_rssi = 0;
1565         antcomb->alt_total_rssi = 0;
1566         antcomb->main_recv_cnt = 0;
1567         antcomb->alt_recv_cnt = 0;
1568 }
1569
1570 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1571 {
1572         struct ath_buf *bf;
1573         struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1574         struct ieee80211_rx_status *rxs;
1575         struct ath_hw *ah = sc->sc_ah;
1576         struct ath_common *common = ath9k_hw_common(ah);
1577         /*
1578          * The hw can technically differ from common->hw when using ath9k
1579          * virtual wiphy so to account for that we iterate over the active
1580          * wiphys and find the appropriate wiphy and therefore hw.
1581          */
1582         struct ieee80211_hw *hw = sc->hw;
1583         struct ieee80211_hdr *hdr;
1584         int retval;
1585         bool decrypt_error = false;
1586         struct ath_rx_status rs;
1587         enum ath9k_rx_qtype qtype;
1588         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1589         int dma_type;
1590         u8 rx_status_len = ah->caps.rx_status_len;
1591         u64 tsf = 0;
1592         u32 tsf_lower = 0;
1593         unsigned long flags;
1594
1595         if (edma)
1596                 dma_type = DMA_BIDIRECTIONAL;
1597         else
1598                 dma_type = DMA_FROM_DEVICE;
1599
1600         qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1601         spin_lock_bh(&sc->rx.rxbuflock);
1602
1603         tsf = ath9k_hw_gettsf64(ah);
1604         tsf_lower = tsf & 0xffffffff;
1605
1606         do {
1607                 /* If handling rx interrupt and flush is in progress => exit */
1608                 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1609                         break;
1610
1611                 memset(&rs, 0, sizeof(rs));
1612                 if (edma)
1613                         bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1614                 else
1615                         bf = ath_get_next_rx_buf(sc, &rs);
1616
1617                 if (!bf)
1618                         break;
1619
1620                 skb = bf->bf_mpdu;
1621                 if (!skb)
1622                         continue;
1623
1624                 /*
1625                  * Take frame header from the first fragment and RX status from
1626                  * the last one.
1627                  */
1628                 if (sc->rx.frag)
1629                         hdr_skb = sc->rx.frag;
1630                 else
1631                         hdr_skb = skb;
1632
1633                 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1634                 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1635
1636                 ath_debug_stat_rx(sc, &rs);
1637
1638                 /*
1639                  * If we're asked to flush receive queue, directly
1640                  * chain it back at the queue without processing it.
1641                  */
1642                 if (flush)
1643                         goto requeue_drop_frag;
1644
1645                 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1646                                                  rxs, &decrypt_error);
1647                 if (retval)
1648                         goto requeue_drop_frag;
1649
1650                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1651                 if (rs.rs_tstamp > tsf_lower &&
1652                     unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1653                         rxs->mactime -= 0x100000000ULL;
1654
1655                 if (rs.rs_tstamp < tsf_lower &&
1656                     unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1657                         rxs->mactime += 0x100000000ULL;
1658
1659                 /* Ensure we always have an skb to requeue once we are done
1660                  * processing the current buffer's skb */
1661                 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1662
1663                 /* If there is no memory we ignore the current RX'd frame,
1664                  * tell hardware it can give us a new frame using the old
1665                  * skb and put it at the tail of the sc->rx.rxbuf list for
1666                  * processing. */
1667                 if (!requeue_skb)
1668                         goto requeue_drop_frag;
1669
1670                 /* Unmap the frame */
1671                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1672                                  common->rx_bufsize,
1673                                  dma_type);
1674
1675                 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1676                 if (ah->caps.rx_status_len)
1677                         skb_pull(skb, ah->caps.rx_status_len);
1678
1679                 if (!rs.rs_more)
1680                         ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1681                                                  rxs, decrypt_error);
1682
1683                 /* We will now give hardware our shiny new allocated skb */
1684                 bf->bf_mpdu = requeue_skb;
1685                 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1686                                                  common->rx_bufsize,
1687                                                  dma_type);
1688                 if (unlikely(dma_mapping_error(sc->dev,
1689                           bf->bf_buf_addr))) {
1690                         dev_kfree_skb_any(requeue_skb);
1691                         bf->bf_mpdu = NULL;
1692                         bf->bf_buf_addr = 0;
1693                         ath_err(common, "dma_mapping_error() on RX\n");
1694                         ieee80211_rx(hw, skb);
1695                         break;
1696                 }
1697
1698                 if (rs.rs_more) {
1699                         /*
1700                          * rs_more indicates chained descriptors which can be
1701                          * used to link buffers together for a sort of
1702                          * scatter-gather operation.
1703                          */
1704                         if (sc->rx.frag) {
1705                                 /* too many fragments - cannot handle frame */
1706                                 dev_kfree_skb_any(sc->rx.frag);
1707                                 dev_kfree_skb_any(skb);
1708                                 skb = NULL;
1709                         }
1710                         sc->rx.frag = skb;
1711                         goto requeue;
1712                 }
1713
1714                 if (sc->rx.frag) {
1715                         int space = skb->len - skb_tailroom(hdr_skb);
1716
1717                         sc->rx.frag = NULL;
1718
1719                         if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1720                                 dev_kfree_skb(skb);
1721                                 goto requeue_drop_frag;
1722                         }
1723
1724                         skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1725                                                   skb->len);
1726                         dev_kfree_skb_any(skb);
1727                         skb = hdr_skb;
1728                 }
1729
1730                 /*
1731                  * change the default rx antenna if rx diversity chooses the
1732                  * other antenna 3 times in a row.
1733                  */
1734                 if (sc->rx.defant != rs.rs_antenna) {
1735                         if (++sc->rx.rxotherant >= 3)
1736                                 ath_setdefantenna(sc, rs.rs_antenna);
1737                 } else {
1738                         sc->rx.rxotherant = 0;
1739                 }
1740
1741                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1742
1743                 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1744                                               PS_WAIT_FOR_CAB |
1745                                               PS_WAIT_FOR_PSPOLL_DATA)) ||
1746                                         unlikely(ath9k_check_auto_sleep(sc)))
1747                         ath_rx_ps(sc, skb);
1748                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1749
1750                 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1751                         ath_ant_comb_scan(sc, &rs);
1752
1753                 ieee80211_rx(hw, skb);
1754
1755 requeue_drop_frag:
1756                 if (sc->rx.frag) {
1757                         dev_kfree_skb_any(sc->rx.frag);
1758                         sc->rx.frag = NULL;
1759                 }
1760 requeue:
1761                 if (edma) {
1762                         list_add_tail(&bf->list, &sc->rx.rxbuf);
1763                         ath_rx_edma_buf_link(sc, qtype);
1764                 } else {
1765                         list_move_tail(&bf->list, &sc->rx.rxbuf);
1766                         ath_rx_buf_link(sc, bf);
1767                         ath9k_hw_rxena(ah);
1768                 }
1769         } while (1);
1770
1771         spin_unlock_bh(&sc->rx.rxbuflock);
1772
1773         return 0;
1774 }