2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u16 bits_per_symbol[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
60 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int txok);
62 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
63 int nbad, int txok, bool update_rc);
72 static int ath_max_4ms_framelen[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
105 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
125 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
127 WARN_ON(!tid->paused);
129 spin_lock_bh(&txq->axq_lock);
132 if (list_empty(&tid->buf_q))
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
138 spin_unlock_bh(&txq->axq_lock);
141 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
143 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
145 struct list_head bf_head;
146 INIT_LIST_HEAD(&bf_head);
148 WARN_ON(!tid->paused);
150 spin_lock_bh(&txq->axq_lock);
153 while (!list_empty(&tid->buf_q)) {
154 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
155 BUG_ON(bf_isretried(bf));
156 list_move_tail(&bf->list, &bf_head);
157 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
160 spin_unlock_bh(&txq->axq_lock);
163 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
168 index = ATH_BA_INDEX(tid->seq_start, seqno);
169 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
171 tid->tx_buf[cindex] = NULL;
173 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
174 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
175 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
179 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
184 if (bf_isretried(bf))
187 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
188 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
190 BUG_ON(tid->tx_buf[cindex] != NULL);
191 tid->tx_buf[cindex] = bf;
193 if (index >= ((tid->baw_tail - tid->baw_head) &
194 (ATH_TID_MAX_BUFS - 1))) {
195 tid->baw_tail = cindex;
196 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
201 * TODO: For frame(s) that are in the retry state, we will reuse the
202 * sequence number(s) without setting the retry bit. The
203 * alternative is to give up on these and BAR the receiver's window
206 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
207 struct ath_atx_tid *tid)
211 struct list_head bf_head;
212 struct ath_tx_status ts;
214 memset(&ts, 0, sizeof(ts));
215 INIT_LIST_HEAD(&bf_head);
218 if (list_empty(&tid->buf_q))
221 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
222 list_move_tail(&bf->list, &bf_head);
224 if (bf_isretried(bf))
225 ath_tx_update_baw(sc, tid, bf->bf_seqno);
227 spin_unlock(&txq->axq_lock);
228 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
229 spin_lock(&txq->axq_lock);
232 tid->seq_next = tid->seq_start;
233 tid->baw_tail = tid->baw_head;
236 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
240 struct ieee80211_hdr *hdr;
242 bf->bf_state.bf_type |= BUF_RETRY;
244 TX_STAT_INC(txq->axq_qnum, a_retries);
247 hdr = (struct ieee80211_hdr *)skb->data;
248 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
251 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
253 struct ath_buf *bf = NULL;
255 spin_lock_bh(&sc->tx.txbuflock);
257 if (unlikely(list_empty(&sc->tx.txbuf))) {
258 spin_unlock_bh(&sc->tx.txbuflock);
262 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
265 spin_unlock_bh(&sc->tx.txbuflock);
270 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
272 spin_lock_bh(&sc->tx.txbuflock);
273 list_add_tail(&bf->list, &sc->tx.txbuf);
274 spin_unlock_bh(&sc->tx.txbuflock);
277 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
281 tbf = ath_tx_get_buffer(sc);
285 ATH_TXBUF_RESET(tbf);
287 tbf->aphy = bf->aphy;
288 tbf->bf_mpdu = bf->bf_mpdu;
289 tbf->bf_buf_addr = bf->bf_buf_addr;
290 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
291 tbf->bf_state = bf->bf_state;
292 tbf->bf_dmacontext = bf->bf_dmacontext;
297 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
298 struct ath_buf *bf, struct list_head *bf_q,
299 struct ath_tx_status *ts, int txok)
301 struct ath_node *an = NULL;
303 struct ieee80211_sta *sta;
304 struct ieee80211_hw *hw;
305 struct ieee80211_hdr *hdr;
306 struct ieee80211_tx_info *tx_info;
307 struct ath_atx_tid *tid = NULL;
308 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
309 struct list_head bf_head, bf_pending;
310 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
311 u32 ba[WME_BA_BMP_SIZE >> 5];
312 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
313 bool rc_update = true;
314 struct ieee80211_tx_rate rates[4];
317 hdr = (struct ieee80211_hdr *)skb->data;
319 tx_info = IEEE80211_SKB_CB(skb);
322 memcpy(rates, tx_info->control.rates, sizeof(rates));
326 /* XXX: use ieee80211_find_sta! */
327 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
331 INIT_LIST_HEAD(&bf_head);
333 bf_next = bf->bf_next;
335 bf->bf_state.bf_type |= BUF_XRETRY;
336 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
337 !bf->bf_stale || bf_next != NULL)
338 list_move_tail(&bf->list, &bf_head);
340 ath_tx_rc_status(bf, ts, 0, 0, false);
341 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
349 an = (struct ath_node *)sta->drv_priv;
350 tid = ATH_AN_2_TID(an, bf->bf_tidno);
353 * The hardware occasionally sends a tx status for the wrong TID.
354 * In this case, the BA status cannot be considered valid and all
355 * subframes need to be retransmitted
357 if (bf->bf_tidno != ts->tid)
360 isaggr = bf_isaggr(bf);
361 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
363 if (isaggr && txok) {
364 if (ts->ts_flags & ATH9K_TX_BA) {
365 seq_st = ts->ts_seqnum;
366 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
369 * AR5416 can become deaf/mute when BA
370 * issue happens. Chip needs to be reset.
371 * But AP code may have sychronization issues
372 * when perform internal reset in this routine.
373 * Only enable reset in STA mode for now.
375 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
380 INIT_LIST_HEAD(&bf_pending);
381 INIT_LIST_HEAD(&bf_head);
383 nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
385 txfail = txpending = 0;
386 bf_next = bf->bf_next;
389 tx_info = IEEE80211_SKB_CB(skb);
391 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
392 /* transmit completion, subframe is
393 * acked by block ack */
395 } else if (!isaggr && txok) {
396 /* transmit completion */
399 if (!(tid->state & AGGR_CLEANUP) &&
400 !bf_last->bf_tx_aborted) {
401 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
402 ath_tx_set_retry(sc, txq, bf);
405 bf->bf_state.bf_type |= BUF_XRETRY;
412 * cleanup in progress, just fail
413 * the un-acked sub-frames
419 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
422 * Make sure the last desc is reclaimed if it
423 * not a holding desc.
425 if (!bf_last->bf_stale)
426 list_move_tail(&bf->list, &bf_head);
428 INIT_LIST_HEAD(&bf_head);
430 BUG_ON(list_empty(bf_q));
431 list_move_tail(&bf->list, &bf_head);
436 * complete the acked-ones/xretried ones; update
439 spin_lock_bh(&txq->axq_lock);
440 ath_tx_update_baw(sc, tid, bf->bf_seqno);
441 spin_unlock_bh(&txq->axq_lock);
443 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
444 memcpy(tx_info->control.rates, rates, sizeof(rates));
445 ath_tx_rc_status(bf, ts, nbad, txok, true);
448 ath_tx_rc_status(bf, ts, nbad, txok, false);
451 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
454 /* retry the un-acked ones */
455 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
456 if (bf->bf_next == NULL && bf_last->bf_stale) {
459 tbf = ath_clone_txbuf(sc, bf_last);
461 * Update tx baw and complete the
462 * frame with failed status if we
466 spin_lock_bh(&txq->axq_lock);
467 ath_tx_update_baw(sc, tid,
469 spin_unlock_bh(&txq->axq_lock);
471 bf->bf_state.bf_type |=
473 ath_tx_rc_status(bf, ts, nbad,
475 ath_tx_complete_buf(sc, bf, txq,
481 ath9k_hw_cleartxdesc(sc->sc_ah,
483 list_add_tail(&tbf->list, &bf_head);
486 * Clear descriptor status words for
489 ath9k_hw_cleartxdesc(sc->sc_ah,
495 * Put this buffer to the temporary pending
496 * queue to retain ordering
498 list_splice_tail_init(&bf_head, &bf_pending);
504 /* prepend un-acked frames to the beginning of the pending frame queue */
505 if (!list_empty(&bf_pending)) {
506 spin_lock_bh(&txq->axq_lock);
507 list_splice(&bf_pending, &tid->buf_q);
508 ath_tx_queue_tid(txq, tid);
509 spin_unlock_bh(&txq->axq_lock);
512 if (tid->state & AGGR_CLEANUP) {
513 if (tid->baw_head == tid->baw_tail) {
514 tid->state &= ~AGGR_ADDBA_COMPLETE;
515 tid->state &= ~AGGR_CLEANUP;
517 /* send buffered frames as singles */
518 ath_tx_flush_tid(sc, tid);
527 ath_reset(sc, false);
530 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
531 struct ath_atx_tid *tid)
534 struct ieee80211_tx_info *tx_info;
535 struct ieee80211_tx_rate *rates;
536 u32 max_4ms_framelen, frmlen;
537 u16 aggr_limit, legacy = 0;
541 tx_info = IEEE80211_SKB_CB(skb);
542 rates = tx_info->control.rates;
545 * Find the lowest frame length among the rate series that will have a
546 * 4ms transmit duration.
547 * TODO - TXOP limit needs to be considered.
549 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
551 for (i = 0; i < 4; i++) {
552 if (rates[i].count) {
554 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
559 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
564 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
567 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
568 max_4ms_framelen = min(max_4ms_framelen, frmlen);
573 * limit aggregate size by the minimum rate if rate selected is
574 * not a probe rate, if rate selected is a probe rate then
575 * avoid aggregation of this packet.
577 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
580 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
581 aggr_limit = min((max_4ms_framelen * 3) / 8,
582 (u32)ATH_AMPDU_LIMIT_MAX);
584 aggr_limit = min(max_4ms_framelen,
585 (u32)ATH_AMPDU_LIMIT_MAX);
588 * h/w can accept aggregates upto 16 bit lengths (65535).
589 * The IE, however can hold upto 65536, which shows up here
590 * as zero. Ignore 65536 since we are constrained by hw.
592 if (tid->an->maxampdu)
593 aggr_limit = min(aggr_limit, tid->an->maxampdu);
599 * Returns the number of delimiters to be added to
600 * meet the minimum required mpdudensity.
602 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
603 struct ath_buf *bf, u16 frmlen)
605 struct sk_buff *skb = bf->bf_mpdu;
606 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
607 u32 nsymbits, nsymbols;
610 int width, streams, half_gi, ndelim, mindelim;
612 /* Select standard number of delimiters based on frame length alone */
613 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
616 * If encryption enabled, hardware requires some more padding between
618 * TODO - this could be improved to be dependent on the rate.
619 * The hardware can keep up at lower rates, but not higher rates
621 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
622 ndelim += ATH_AGGR_ENCRYPTDELIM;
625 * Convert desired mpdu density from microeconds to bytes based
626 * on highest rate in rate series (i.e. first rate) to determine
627 * required minimum length for subframe. Take into account
628 * whether high rate is 20 or 40Mhz and half or full GI.
630 * If there is no mpdu density restriction, no further calculation
634 if (tid->an->mpdudensity == 0)
637 rix = tx_info->control.rates[0].idx;
638 flags = tx_info->control.rates[0].flags;
639 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
640 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
643 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
645 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
650 streams = HT_RC_2_STREAMS(rix);
651 nsymbits = bits_per_symbol[rix % 8][width] * streams;
652 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
654 if (frmlen < minlen) {
655 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
656 ndelim = max(mindelim, ndelim);
662 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
664 struct ath_atx_tid *tid,
665 struct list_head *bf_q)
667 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
668 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
669 int rl = 0, nframes = 0, ndelim, prev_al = 0;
670 u16 aggr_limit = 0, al = 0, bpad = 0,
671 al_delta, h_baw = tid->baw_size / 2;
672 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
674 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
677 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
679 /* do not step over block-ack window */
680 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
681 status = ATH_AGGR_BAW_CLOSED;
686 aggr_limit = ath_lookup_rate(sc, bf, tid);
690 /* do not exceed aggregation limit */
691 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
694 (aggr_limit < (al + bpad + al_delta + prev_al))) {
695 status = ATH_AGGR_LIMITED;
699 /* do not exceed subframe limit */
700 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
701 status = ATH_AGGR_LIMITED;
706 /* add padding for previous frame to aggregation length */
707 al += bpad + al_delta;
710 * Get the delimiters needed to meet the MPDU
711 * density for this node.
713 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
714 bpad = PADBYTES(al_delta) + (ndelim << 2);
717 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
719 /* link buffers of this frame to the aggregate */
720 ath_tx_addto_baw(sc, tid, bf);
721 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
722 list_move_tail(&bf->list, bf_q);
724 bf_prev->bf_next = bf;
725 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
730 } while (!list_empty(&tid->buf_q));
732 bf_first->bf_al = al;
733 bf_first->bf_nframes = nframes;
739 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
740 struct ath_atx_tid *tid)
743 enum ATH_AGGR_STATUS status;
744 struct list_head bf_q;
747 if (list_empty(&tid->buf_q))
750 INIT_LIST_HEAD(&bf_q);
752 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
755 * no frames picked up to be aggregated;
756 * block-ack window is not open.
758 if (list_empty(&bf_q))
761 bf = list_first_entry(&bf_q, struct ath_buf, list);
762 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
764 /* if only one frame, send as non-aggregate */
765 if (bf->bf_nframes == 1) {
766 bf->bf_state.bf_type &= ~BUF_AGGR;
767 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
768 ath_buf_set_rate(sc, bf);
769 ath_tx_txqaddbuf(sc, txq, &bf_q);
773 /* setup first desc of aggregate */
774 bf->bf_state.bf_type |= BUF_AGGR;
775 ath_buf_set_rate(sc, bf);
776 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
778 /* anchor last desc of aggregate */
779 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
781 ath_tx_txqaddbuf(sc, txq, &bf_q);
782 TX_STAT_INC(txq->axq_qnum, a_aggr);
784 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
785 status != ATH_AGGR_BAW_CLOSED);
788 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
791 struct ath_atx_tid *txtid;
794 an = (struct ath_node *)sta->drv_priv;
795 txtid = ATH_AN_2_TID(an, tid);
796 txtid->state |= AGGR_ADDBA_PROGRESS;
797 txtid->paused = true;
798 *ssn = txtid->seq_start;
801 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
803 struct ath_node *an = (struct ath_node *)sta->drv_priv;
804 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
805 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
806 struct ath_tx_status ts;
808 struct list_head bf_head;
810 memset(&ts, 0, sizeof(ts));
811 INIT_LIST_HEAD(&bf_head);
813 if (txtid->state & AGGR_CLEANUP)
816 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
817 txtid->state &= ~AGGR_ADDBA_PROGRESS;
821 /* drop all software retried frames and mark this TID */
822 spin_lock_bh(&txq->axq_lock);
823 txtid->paused = true;
824 while (!list_empty(&txtid->buf_q)) {
825 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
826 if (!bf_isretried(bf)) {
828 * NB: it's based on the assumption that
829 * software retried frame will always stay
830 * at the head of software queue.
834 list_move_tail(&bf->list, &bf_head);
835 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
836 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
838 spin_unlock_bh(&txq->axq_lock);
840 if (txtid->baw_head != txtid->baw_tail) {
841 txtid->state |= AGGR_CLEANUP;
843 txtid->state &= ~AGGR_ADDBA_COMPLETE;
844 ath_tx_flush_tid(sc, txtid);
848 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
850 struct ath_atx_tid *txtid;
853 an = (struct ath_node *)sta->drv_priv;
855 if (sc->sc_flags & SC_OP_TXAGGR) {
856 txtid = ATH_AN_2_TID(an, tid);
858 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
859 txtid->state |= AGGR_ADDBA_COMPLETE;
860 txtid->state &= ~AGGR_ADDBA_PROGRESS;
861 ath_tx_resume_tid(sc, txtid);
865 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
867 struct ath_atx_tid *txtid;
869 if (!(sc->sc_flags & SC_OP_TXAGGR))
872 txtid = ATH_AN_2_TID(an, tidno);
874 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
879 /********************/
880 /* Queue Management */
881 /********************/
883 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
886 struct ath_atx_ac *ac, *ac_tmp;
887 struct ath_atx_tid *tid, *tid_tmp;
889 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
892 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
893 list_del(&tid->list);
895 ath_tid_drain(sc, txq, tid);
900 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
902 struct ath_hw *ah = sc->sc_ah;
903 struct ath_common *common = ath9k_hw_common(ah);
904 struct ath9k_tx_queue_info qi;
907 memset(&qi, 0, sizeof(qi));
908 qi.tqi_subtype = subtype;
909 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
910 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
911 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
912 qi.tqi_physCompBuf = 0;
915 * Enable interrupts only for EOL and DESC conditions.
916 * We mark tx descriptors to receive a DESC interrupt
917 * when a tx queue gets deep; otherwise waiting for the
918 * EOL to reap descriptors. Note that this is done to
919 * reduce interrupt load and this only defers reaping
920 * descriptors, never transmitting frames. Aside from
921 * reducing interrupts this also permits more concurrency.
922 * The only potential downside is if the tx queue backs
923 * up in which case the top half of the kernel may backup
924 * due to a lack of tx descriptors.
926 * The UAPSD queue is an exception, since we take a desc-
927 * based intr on the EOSP frames.
929 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
930 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
931 TXQ_FLAG_TXERRINT_ENABLE;
933 if (qtype == ATH9K_TX_QUEUE_UAPSD)
934 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
936 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
937 TXQ_FLAG_TXDESCINT_ENABLE;
939 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
942 * NB: don't print a message, this happens
943 * normally on parts with too few tx queues
947 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
948 ath_print(common, ATH_DBG_FATAL,
949 "qnum %u out of range, max %u!\n",
950 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
951 ath9k_hw_releasetxqueue(ah, qnum);
954 if (!ATH_TXQ_SETUP(sc, qnum)) {
955 struct ath_txq *txq = &sc->tx.txq[qnum];
957 txq->axq_class = subtype;
958 txq->axq_qnum = qnum;
959 txq->axq_link = NULL;
960 INIT_LIST_HEAD(&txq->axq_q);
961 INIT_LIST_HEAD(&txq->axq_acq);
962 spin_lock_init(&txq->axq_lock);
964 txq->axq_tx_inprogress = false;
965 sc->tx.txqsetup |= 1<<qnum;
967 txq->txq_headidx = txq->txq_tailidx = 0;
968 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
969 INIT_LIST_HEAD(&txq->txq_fifo[i]);
970 INIT_LIST_HEAD(&txq->txq_fifo_pending);
972 return &sc->tx.txq[qnum];
975 int ath_txq_update(struct ath_softc *sc, int qnum,
976 struct ath9k_tx_queue_info *qinfo)
978 struct ath_hw *ah = sc->sc_ah;
980 struct ath9k_tx_queue_info qi;
982 if (qnum == sc->beacon.beaconq) {
984 * XXX: for beacon queue, we just save the parameter.
985 * It will be picked up by ath_beaconq_config when
988 sc->beacon.beacon_qi = *qinfo;
992 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
994 ath9k_hw_get_txq_props(ah, qnum, &qi);
995 qi.tqi_aifs = qinfo->tqi_aifs;
996 qi.tqi_cwmin = qinfo->tqi_cwmin;
997 qi.tqi_cwmax = qinfo->tqi_cwmax;
998 qi.tqi_burstTime = qinfo->tqi_burstTime;
999 qi.tqi_readyTime = qinfo->tqi_readyTime;
1001 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1002 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1003 "Unable to update hardware queue %u!\n", qnum);
1006 ath9k_hw_resettxqueue(ah, qnum);
1012 int ath_cabq_update(struct ath_softc *sc)
1014 struct ath9k_tx_queue_info qi;
1015 int qnum = sc->beacon.cabq->axq_qnum;
1017 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1019 * Ensure the readytime % is within the bounds.
1021 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1022 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1023 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1024 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1026 qi.tqi_readyTime = (sc->beacon_interval *
1027 sc->config.cabqReadytime) / 100;
1028 ath_txq_update(sc, qnum, &qi);
1034 * Drain a given TX queue (could be Beacon or Data)
1036 * This assumes output has been stopped and
1037 * we do not need to block ath_tx_tasklet.
1039 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1041 struct ath_buf *bf, *lastbf;
1042 struct list_head bf_head;
1043 struct ath_tx_status ts;
1045 memset(&ts, 0, sizeof(ts));
1046 INIT_LIST_HEAD(&bf_head);
1049 spin_lock_bh(&txq->axq_lock);
1051 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1052 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1053 txq->txq_headidx = txq->txq_tailidx = 0;
1054 spin_unlock_bh(&txq->axq_lock);
1057 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1058 struct ath_buf, list);
1061 if (list_empty(&txq->axq_q)) {
1062 txq->axq_link = NULL;
1063 spin_unlock_bh(&txq->axq_lock);
1066 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1070 list_del(&bf->list);
1071 spin_unlock_bh(&txq->axq_lock);
1073 ath_tx_return_buffer(sc, bf);
1078 lastbf = bf->bf_lastbf;
1080 lastbf->bf_tx_aborted = true;
1082 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1083 list_cut_position(&bf_head,
1084 &txq->txq_fifo[txq->txq_tailidx],
1086 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1088 /* remove ath_buf's of the same mpdu from txq */
1089 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1094 spin_unlock_bh(&txq->axq_lock);
1097 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
1099 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1102 spin_lock_bh(&txq->axq_lock);
1103 txq->axq_tx_inprogress = false;
1104 spin_unlock_bh(&txq->axq_lock);
1106 /* flush any pending frames if aggregation is enabled */
1107 if (sc->sc_flags & SC_OP_TXAGGR) {
1109 spin_lock_bh(&txq->axq_lock);
1110 ath_txq_drain_pending_buffers(sc, txq);
1111 spin_unlock_bh(&txq->axq_lock);
1115 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1116 spin_lock_bh(&txq->axq_lock);
1117 while (!list_empty(&txq->txq_fifo_pending)) {
1118 bf = list_first_entry(&txq->txq_fifo_pending,
1119 struct ath_buf, list);
1120 list_cut_position(&bf_head,
1121 &txq->txq_fifo_pending,
1122 &bf->bf_lastbf->list);
1123 spin_unlock_bh(&txq->axq_lock);
1126 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1129 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1131 spin_lock_bh(&txq->axq_lock);
1133 spin_unlock_bh(&txq->axq_lock);
1137 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1139 struct ath_hw *ah = sc->sc_ah;
1140 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1141 struct ath_txq *txq;
1144 if (sc->sc_flags & SC_OP_INVALID)
1147 /* Stop beacon queue */
1148 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1150 /* Stop data queues */
1151 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1152 if (ATH_TXQ_SETUP(sc, i)) {
1153 txq = &sc->tx.txq[i];
1154 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1155 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1162 ath_print(common, ATH_DBG_FATAL,
1163 "Failed to stop TX DMA. Resetting hardware!\n");
1165 spin_lock_bh(&sc->sc_resetlock);
1166 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1168 ath_print(common, ATH_DBG_FATAL,
1169 "Unable to reset hardware; reset status %d\n",
1171 spin_unlock_bh(&sc->sc_resetlock);
1174 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1175 if (ATH_TXQ_SETUP(sc, i))
1176 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1180 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1182 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1183 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1186 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1188 struct ath_atx_ac *ac;
1189 struct ath_atx_tid *tid;
1191 if (list_empty(&txq->axq_acq))
1194 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1195 list_del(&ac->list);
1199 if (list_empty(&ac->tid_q))
1202 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1203 list_del(&tid->list);
1209 ath_tx_sched_aggr(sc, txq, tid);
1212 * add tid to round-robin queue if more frames
1213 * are pending for the tid
1215 if (!list_empty(&tid->buf_q))
1216 ath_tx_queue_tid(txq, tid);
1219 } while (!list_empty(&ac->tid_q));
1221 if (!list_empty(&ac->tid_q)) {
1224 list_add_tail(&ac->list, &txq->axq_acq);
1229 int ath_tx_setup(struct ath_softc *sc, int haltype)
1231 struct ath_txq *txq;
1233 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1234 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1235 "HAL AC %u out of range, max %zu!\n",
1236 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1239 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1241 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1252 * Insert a chain of ath_buf (descriptors) on a txq and
1253 * assume the descriptors are already chained together by caller.
1255 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1256 struct list_head *head)
1258 struct ath_hw *ah = sc->sc_ah;
1259 struct ath_common *common = ath9k_hw_common(ah);
1263 * Insert the frame on the outbound list and
1264 * pass it on to the hardware.
1267 if (list_empty(head))
1270 bf = list_first_entry(head, struct ath_buf, list);
1272 ath_print(common, ATH_DBG_QUEUE,
1273 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1276 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1277 list_splice_tail_init(head, &txq->txq_fifo_pending);
1280 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1281 ath_print(common, ATH_DBG_XMIT,
1282 "Initializing tx fifo %d which "
1285 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1286 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1287 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1288 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1289 ath_print(common, ATH_DBG_XMIT,
1290 "TXDP[%u] = %llx (%p)\n",
1291 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1293 list_splice_tail_init(head, &txq->axq_q);
1295 if (txq->axq_link == NULL) {
1296 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1297 ath_print(common, ATH_DBG_XMIT,
1298 "TXDP[%u] = %llx (%p)\n",
1299 txq->axq_qnum, ito64(bf->bf_daddr),
1302 *txq->axq_link = bf->bf_daddr;
1303 ath_print(common, ATH_DBG_XMIT,
1304 "link[%u] (%p)=%llx (%p)\n",
1305 txq->axq_qnum, txq->axq_link,
1306 ito64(bf->bf_daddr), bf->bf_desc);
1308 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1310 ath9k_hw_txstart(ah, txq->axq_qnum);
1315 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1316 struct list_head *bf_head,
1317 struct ath_tx_control *txctl)
1321 bf = list_first_entry(bf_head, struct ath_buf, list);
1322 bf->bf_state.bf_type |= BUF_AMPDU;
1323 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1326 * Do not queue to h/w when any of the following conditions is true:
1327 * - there are pending frames in software queue
1328 * - the TID is currently paused for ADDBA/BAR request
1329 * - seqno is not within block-ack window
1330 * - h/w queue depth exceeds low water mark
1332 if (!list_empty(&tid->buf_q) || tid->paused ||
1333 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1334 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1336 * Add this frame to software queue for scheduling later
1339 list_move_tail(&bf->list, &tid->buf_q);
1340 ath_tx_queue_tid(txctl->txq, tid);
1344 /* Add sub-frame to BAW */
1345 ath_tx_addto_baw(sc, tid, bf);
1347 /* Queue to h/w without aggregation */
1350 ath_buf_set_rate(sc, bf);
1351 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1354 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1355 struct ath_atx_tid *tid,
1356 struct list_head *bf_head)
1360 bf = list_first_entry(bf_head, struct ath_buf, list);
1361 bf->bf_state.bf_type &= ~BUF_AMPDU;
1363 /* update starting sequence number for subsequent ADDBA request */
1364 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1368 ath_buf_set_rate(sc, bf);
1369 ath_tx_txqaddbuf(sc, txq, bf_head);
1370 TX_STAT_INC(txq->axq_qnum, queued);
1373 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1374 struct list_head *bf_head)
1378 bf = list_first_entry(bf_head, struct ath_buf, list);
1382 ath_buf_set_rate(sc, bf);
1383 ath_tx_txqaddbuf(sc, txq, bf_head);
1384 TX_STAT_INC(txq->axq_qnum, queued);
1387 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1389 struct ieee80211_hdr *hdr;
1390 enum ath9k_pkt_type htype;
1393 hdr = (struct ieee80211_hdr *)skb->data;
1394 fc = hdr->frame_control;
1396 if (ieee80211_is_beacon(fc))
1397 htype = ATH9K_PKT_TYPE_BEACON;
1398 else if (ieee80211_is_probe_resp(fc))
1399 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1400 else if (ieee80211_is_atim(fc))
1401 htype = ATH9K_PKT_TYPE_ATIM;
1402 else if (ieee80211_is_pspoll(fc))
1403 htype = ATH9K_PKT_TYPE_PSPOLL;
1405 htype = ATH9K_PKT_TYPE_NORMAL;
1410 static int get_hw_crypto_keytype(struct sk_buff *skb)
1412 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1414 if (tx_info->control.hw_key) {
1415 if (tx_info->control.hw_key->alg == ALG_WEP)
1416 return ATH9K_KEY_TYPE_WEP;
1417 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1418 return ATH9K_KEY_TYPE_TKIP;
1419 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1420 return ATH9K_KEY_TYPE_AES;
1423 return ATH9K_KEY_TYPE_CLEAR;
1426 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1429 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1430 struct ieee80211_hdr *hdr;
1431 struct ath_node *an;
1432 struct ath_atx_tid *tid;
1436 if (!tx_info->control.sta)
1439 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1440 hdr = (struct ieee80211_hdr *)skb->data;
1441 fc = hdr->frame_control;
1443 if (ieee80211_is_data_qos(fc)) {
1444 qc = ieee80211_get_qos_ctl(hdr);
1445 bf->bf_tidno = qc[0] & 0xf;
1449 * For HT capable stations, we save tidno for later use.
1450 * We also override seqno set by upper layer with the one
1451 * in tx aggregation state.
1453 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1454 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1455 bf->bf_seqno = tid->seq_next;
1456 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1459 static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1461 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1464 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1465 flags |= ATH9K_TXDESC_INTREQ;
1467 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1468 flags |= ATH9K_TXDESC_NOACK;
1471 flags |= ATH9K_TXDESC_LDPC;
1478 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1479 * width - 0 for 20 MHz, 1 for 40 MHz
1480 * half_gi - to use 4us v/s 3.6 us for symbol time
1482 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1483 int width, int half_gi, bool shortPreamble)
1485 u32 nbits, nsymbits, duration, nsymbols;
1486 int streams, pktlen;
1488 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1490 /* find number of symbols: PLCP + data */
1491 streams = HT_RC_2_STREAMS(rix);
1492 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1493 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1494 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1497 duration = SYMBOL_TIME(nsymbols);
1499 duration = SYMBOL_TIME_HALFGI(nsymbols);
1501 /* addup duration for legacy/ht training and signal fields */
1502 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1507 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1509 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1510 struct ath9k_11n_rate_series series[4];
1511 struct sk_buff *skb;
1512 struct ieee80211_tx_info *tx_info;
1513 struct ieee80211_tx_rate *rates;
1514 const struct ieee80211_rate *rate;
1515 struct ieee80211_hdr *hdr;
1517 u8 rix = 0, ctsrate = 0;
1520 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1523 tx_info = IEEE80211_SKB_CB(skb);
1524 rates = tx_info->control.rates;
1525 hdr = (struct ieee80211_hdr *)skb->data;
1526 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1529 * We check if Short Preamble is needed for the CTS rate by
1530 * checking the BSS's global flag.
1531 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1533 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1534 ctsrate = rate->hw_value;
1535 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1536 ctsrate |= rate->hw_value_short;
1538 for (i = 0; i < 4; i++) {
1539 bool is_40, is_sgi, is_sp;
1542 if (!rates[i].count || (rates[i].idx < 0))
1546 series[i].Tries = rates[i].count;
1547 series[i].ChSel = common->tx_chainmask;
1549 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1550 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1551 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1552 flags |= ATH9K_TXDESC_RTSENA;
1553 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1554 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1555 flags |= ATH9K_TXDESC_CTSENA;
1558 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1559 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1560 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1561 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1563 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1564 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1565 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1567 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1569 series[i].Rate = rix | 0x80;
1570 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1571 is_40, is_sgi, is_sp);
1572 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1573 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1578 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1579 !(rate->flags & IEEE80211_RATE_ERP_G))
1580 phy = WLAN_RC_PHY_CCK;
1582 phy = WLAN_RC_PHY_OFDM;
1584 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1585 series[i].Rate = rate->hw_value;
1586 if (rate->hw_value_short) {
1587 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1588 series[i].Rate |= rate->hw_value_short;
1593 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1594 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1597 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1598 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1599 flags &= ~ATH9K_TXDESC_RTSENA;
1601 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1602 if (flags & ATH9K_TXDESC_RTSENA)
1603 flags &= ~ATH9K_TXDESC_CTSENA;
1605 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1606 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1607 bf->bf_lastbf->bf_desc,
1608 !is_pspoll, ctsrate,
1609 0, series, 4, flags);
1611 if (sc->config.ath_aggr_prot && flags)
1612 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1615 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1616 struct sk_buff *skb,
1617 struct ath_tx_control *txctl)
1619 struct ath_wiphy *aphy = hw->priv;
1620 struct ath_softc *sc = aphy->sc;
1621 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1622 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1625 int padpos, padsize;
1626 bool use_ldpc = false;
1628 tx_info->pad[0] = 0;
1629 switch (txctl->frame_type) {
1630 case ATH9K_IFT_NOT_INTERNAL:
1632 case ATH9K_IFT_PAUSE:
1633 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1635 case ATH9K_IFT_UNPAUSE:
1636 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1639 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1640 fc = hdr->frame_control;
1642 ATH_TXBUF_RESET(bf);
1645 bf->bf_frmlen = skb->len + FCS_LEN;
1646 /* Remove the padding size from bf_frmlen, if any */
1647 padpos = ath9k_cmn_padpos(hdr->frame_control);
1648 padsize = padpos & 3;
1649 if (padsize && skb->len>padpos+padsize) {
1650 bf->bf_frmlen -= padsize;
1653 if (!txctl->paprd && conf_is_ht(&hw->conf)) {
1654 bf->bf_state.bf_type |= BUF_HT;
1655 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1659 bf->bf_state.bfs_paprd = txctl->paprd;
1661 bf->bf_state.bfs_paprd_timestamp = jiffies;
1662 bf->bf_flags = setup_tx_flags(skb, use_ldpc);
1664 bf->bf_keytype = get_hw_crypto_keytype(skb);
1665 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1666 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1667 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1669 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1672 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1673 (sc->sc_flags & SC_OP_TXAGGR))
1674 assign_aggr_tid_seqno(skb, bf);
1678 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1679 skb->len, DMA_TO_DEVICE);
1680 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1682 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1683 "dma_mapping_error() on TX\n");
1687 bf->bf_buf_addr = bf->bf_dmacontext;
1689 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1690 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1691 bf->bf_isnullfunc = true;
1692 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1694 bf->bf_isnullfunc = false;
1696 bf->bf_tx_aborted = false;
1701 /* FIXME: tx power */
1702 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1703 struct ath_tx_control *txctl)
1705 struct sk_buff *skb = bf->bf_mpdu;
1706 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1707 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1708 struct ath_node *an = NULL;
1709 struct list_head bf_head;
1710 struct ath_desc *ds;
1711 struct ath_atx_tid *tid;
1712 struct ath_hw *ah = sc->sc_ah;
1716 frm_type = get_hw_packet_type(skb);
1717 fc = hdr->frame_control;
1719 INIT_LIST_HEAD(&bf_head);
1720 list_add_tail(&bf->list, &bf_head);
1723 ath9k_hw_set_desc_link(ah, ds, 0);
1725 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1726 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1728 ath9k_hw_filltxdesc(ah, ds,
1729 skb->len, /* segment length */
1730 true, /* first segment */
1731 true, /* last segment */
1732 ds, /* first descriptor */
1734 txctl->txq->axq_qnum);
1736 if (bf->bf_state.bfs_paprd)
1737 ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
1739 spin_lock_bh(&txctl->txq->axq_lock);
1741 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1742 tx_info->control.sta) {
1743 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1744 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1746 if (!ieee80211_is_data_qos(fc)) {
1747 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1751 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1753 * Try aggregation if it's a unicast data frame
1754 * and the destination is HT capable.
1756 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1759 * Send this frame as regular when ADDBA
1760 * exchange is neither complete nor pending.
1762 ath_tx_send_ht_normal(sc, txctl->txq,
1766 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1770 spin_unlock_bh(&txctl->txq->axq_lock);
1773 /* Upon failure caller should free skb */
1774 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1775 struct ath_tx_control *txctl)
1777 struct ath_wiphy *aphy = hw->priv;
1778 struct ath_softc *sc = aphy->sc;
1779 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1780 struct ath_txq *txq = txctl->txq;
1784 bf = ath_tx_get_buffer(sc);
1786 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1790 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1792 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1794 /* upon ath_tx_processq() this TX queue will be resumed, we
1795 * guarantee this will happen by knowing beforehand that
1796 * we will at least have to run TX completionon one buffer
1798 spin_lock_bh(&txq->axq_lock);
1799 if (!txq->stopped && txq->axq_depth > 1) {
1800 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1803 spin_unlock_bh(&txq->axq_lock);
1805 ath_tx_return_buffer(sc, bf);
1810 q = skb_get_queue_mapping(skb);
1814 spin_lock_bh(&txq->axq_lock);
1815 if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
1816 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1819 spin_unlock_bh(&txq->axq_lock);
1821 ath_tx_start_dma(sc, bf, txctl);
1826 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1828 struct ath_wiphy *aphy = hw->priv;
1829 struct ath_softc *sc = aphy->sc;
1830 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1831 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1832 int padpos, padsize;
1833 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1834 struct ath_tx_control txctl;
1836 memset(&txctl, 0, sizeof(struct ath_tx_control));
1839 * As a temporary workaround, assign seq# here; this will likely need
1840 * to be cleaned up to work better with Beacon transmission and virtual
1843 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1844 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1845 sc->tx.seq_no += 0x10;
1846 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1847 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1850 /* Add the padding after the header if this is not already done */
1851 padpos = ath9k_cmn_padpos(hdr->frame_control);
1852 padsize = padpos & 3;
1853 if (padsize && skb->len>padpos) {
1854 if (skb_headroom(skb) < padsize) {
1855 ath_print(common, ATH_DBG_XMIT,
1856 "TX CABQ padding failed\n");
1857 dev_kfree_skb_any(skb);
1860 skb_push(skb, padsize);
1861 memmove(skb->data, skb->data + padsize, padpos);
1864 txctl.txq = sc->beacon.cabq;
1866 ath_print(common, ATH_DBG_XMIT,
1867 "transmitting CABQ packet, skb: %p\n", skb);
1869 if (ath_tx_start(hw, skb, &txctl) != 0) {
1870 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1876 dev_kfree_skb_any(skb);
1883 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1884 struct ath_wiphy *aphy, int tx_flags)
1886 struct ieee80211_hw *hw = sc->hw;
1887 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1888 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1889 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1890 int q, padpos, padsize;
1892 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1897 if (tx_flags & ATH_TX_BAR)
1898 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1900 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1901 /* Frame was ACKed */
1902 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1905 padpos = ath9k_cmn_padpos(hdr->frame_control);
1906 padsize = padpos & 3;
1907 if (padsize && skb->len>padpos+padsize) {
1909 * Remove MAC header padding before giving the frame back to
1912 memmove(skb->data + padsize, skb->data, padpos);
1913 skb_pull(skb, padsize);
1916 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1917 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1918 ath_print(common, ATH_DBG_PS,
1919 "Going back to sleep after having "
1920 "received TX status (0x%lx)\n",
1921 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1923 PS_WAIT_FOR_PSPOLL_DATA |
1924 PS_WAIT_FOR_TX_ACK));
1927 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1928 ath9k_tx_status(hw, skb);
1930 q = skb_get_queue_mapping(skb);
1934 if (--sc->tx.pending_frames[q] < 0)
1935 sc->tx.pending_frames[q] = 0;
1937 ieee80211_tx_status(hw, skb);
1941 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1942 struct ath_txq *txq, struct list_head *bf_q,
1943 struct ath_tx_status *ts, int txok, int sendbar)
1945 struct sk_buff *skb = bf->bf_mpdu;
1946 unsigned long flags;
1950 tx_flags = ATH_TX_BAR;
1953 tx_flags |= ATH_TX_ERROR;
1955 if (bf_isxretried(bf))
1956 tx_flags |= ATH_TX_XRETRY;
1959 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1961 if (bf->bf_state.bfs_paprd) {
1962 if (time_after(jiffies,
1963 bf->bf_state.bfs_paprd_timestamp +
1964 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1965 dev_kfree_skb_any(skb);
1967 complete(&sc->paprd_complete);
1969 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1970 ath_debug_stat_tx(sc, txq, bf, ts);
1974 * Return the list of ath_buf of this mpdu to free queue
1976 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1977 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1978 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1981 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1982 struct ath_tx_status *ts, int txok)
1985 u32 ba[WME_BA_BMP_SIZE >> 5];
1990 if (bf->bf_lastbf->bf_tx_aborted)
1993 isaggr = bf_isaggr(bf);
1995 seq_st = ts->ts_seqnum;
1996 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
2000 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
2001 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
2010 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
2011 int nbad, int txok, bool update_rc)
2013 struct sk_buff *skb = bf->bf_mpdu;
2014 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2015 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2016 struct ieee80211_hw *hw = bf->aphy->hw;
2020 tx_info->status.ack_signal = ts->ts_rssi;
2022 tx_rateindex = ts->ts_rateindex;
2023 WARN_ON(tx_rateindex >= hw->max_rates);
2025 if (ts->ts_status & ATH9K_TXERR_FILT)
2026 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2027 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
2028 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2030 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2031 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2032 if (ieee80211_is_data(hdr->frame_control)) {
2034 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
2035 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
2036 if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
2037 (ts->ts_status & ATH9K_TXERR_FIFO))
2038 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
2039 tx_info->status.ampdu_len = bf->bf_nframes;
2040 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
2044 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2045 tx_info->status.rates[i].count = 0;
2046 tx_info->status.rates[i].idx = -1;
2049 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2052 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
2056 qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
2060 spin_lock_bh(&txq->axq_lock);
2061 if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
2062 if (ath_mac80211_start_queue(sc, qnum))
2065 spin_unlock_bh(&txq->axq_lock);
2068 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2070 struct ath_hw *ah = sc->sc_ah;
2071 struct ath_common *common = ath9k_hw_common(ah);
2072 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2073 struct list_head bf_head;
2074 struct ath_desc *ds;
2075 struct ath_tx_status ts;
2079 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2080 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2084 spin_lock_bh(&txq->axq_lock);
2085 if (list_empty(&txq->axq_q)) {
2086 txq->axq_link = NULL;
2087 spin_unlock_bh(&txq->axq_lock);
2090 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2093 * There is a race condition that a BH gets scheduled
2094 * after sw writes TxE and before hw re-load the last
2095 * descriptor to get the newly chained one.
2096 * Software must keep the last DONE descriptor as a
2097 * holding descriptor - software does so by marking
2098 * it with the STALE flag.
2103 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2104 spin_unlock_bh(&txq->axq_lock);
2107 bf = list_entry(bf_held->list.next,
2108 struct ath_buf, list);
2112 lastbf = bf->bf_lastbf;
2113 ds = lastbf->bf_desc;
2115 memset(&ts, 0, sizeof(ts));
2116 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2117 if (status == -EINPROGRESS) {
2118 spin_unlock_bh(&txq->axq_lock);
2123 * We now know the nullfunc frame has been ACKed so we
2126 if (bf->bf_isnullfunc &&
2127 (ts.ts_status & ATH9K_TX_ACKED)) {
2128 if ((sc->ps_flags & PS_ENABLED))
2129 ath9k_enable_ps(sc);
2131 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2135 * Remove ath_buf's of the same transmit unit from txq,
2136 * however leave the last descriptor back as the holding
2137 * descriptor for hw.
2139 lastbf->bf_stale = true;
2140 INIT_LIST_HEAD(&bf_head);
2141 if (!list_is_singular(&lastbf->list))
2142 list_cut_position(&bf_head,
2143 &txq->axq_q, lastbf->list.prev);
2146 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2147 txq->axq_tx_inprogress = false;
2149 list_del(&bf_held->list);
2150 spin_unlock_bh(&txq->axq_lock);
2153 ath_tx_return_buffer(sc, bf_held);
2155 if (!bf_isampdu(bf)) {
2157 * This frame is sent out as a single frame.
2158 * Use hardware retry status for this frame.
2160 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2161 bf->bf_state.bf_type |= BUF_XRETRY;
2162 ath_tx_rc_status(bf, &ts, 0, txok, true);
2166 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
2168 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2170 ath_wake_mac80211_queue(sc, txq);
2172 spin_lock_bh(&txq->axq_lock);
2173 if (sc->sc_flags & SC_OP_TXAGGR)
2174 ath_txq_schedule(sc, txq);
2175 spin_unlock_bh(&txq->axq_lock);
2179 static void ath_tx_complete_poll_work(struct work_struct *work)
2181 struct ath_softc *sc = container_of(work, struct ath_softc,
2182 tx_complete_work.work);
2183 struct ath_txq *txq;
2185 bool needreset = false;
2187 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2188 if (ATH_TXQ_SETUP(sc, i)) {
2189 txq = &sc->tx.txq[i];
2190 spin_lock_bh(&txq->axq_lock);
2191 if (txq->axq_depth) {
2192 if (txq->axq_tx_inprogress) {
2194 spin_unlock_bh(&txq->axq_lock);
2197 txq->axq_tx_inprogress = true;
2200 spin_unlock_bh(&txq->axq_lock);
2204 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2205 "tx hung, resetting the chip\n");
2206 ath9k_ps_wakeup(sc);
2207 ath_reset(sc, false);
2208 ath9k_ps_restore(sc);
2211 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2212 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2217 void ath_tx_tasklet(struct ath_softc *sc)
2220 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2222 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2224 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2225 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2226 ath_tx_processq(sc, &sc->tx.txq[i]);
2230 void ath_tx_edma_tasklet(struct ath_softc *sc)
2232 struct ath_tx_status txs;
2233 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2234 struct ath_hw *ah = sc->sc_ah;
2235 struct ath_txq *txq;
2236 struct ath_buf *bf, *lastbf;
2237 struct list_head bf_head;
2242 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2243 if (status == -EINPROGRESS)
2245 if (status == -EIO) {
2246 ath_print(common, ATH_DBG_XMIT,
2247 "Error processing tx status\n");
2251 /* Skip beacon completions */
2252 if (txs.qid == sc->beacon.beaconq)
2255 txq = &sc->tx.txq[txs.qid];
2257 spin_lock_bh(&txq->axq_lock);
2258 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2259 spin_unlock_bh(&txq->axq_lock);
2263 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2264 struct ath_buf, list);
2265 lastbf = bf->bf_lastbf;
2267 INIT_LIST_HEAD(&bf_head);
2268 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2270 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2272 txq->axq_tx_inprogress = false;
2273 spin_unlock_bh(&txq->axq_lock);
2275 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2278 * Make sure null func frame is acked before configuring
2281 if (bf->bf_isnullfunc && txok) {
2282 if ((sc->ps_flags & PS_ENABLED))
2283 ath9k_enable_ps(sc);
2285 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2288 if (!bf_isampdu(bf)) {
2289 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2290 bf->bf_state.bf_type |= BUF_XRETRY;
2291 ath_tx_rc_status(bf, &txs, 0, txok, true);
2295 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
2297 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2300 ath_wake_mac80211_queue(sc, txq);
2302 spin_lock_bh(&txq->axq_lock);
2303 if (!list_empty(&txq->txq_fifo_pending)) {
2304 INIT_LIST_HEAD(&bf_head);
2305 bf = list_first_entry(&txq->txq_fifo_pending,
2306 struct ath_buf, list);
2307 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2308 &bf->bf_lastbf->list);
2309 ath_tx_txqaddbuf(sc, txq, &bf_head);
2310 } else if (sc->sc_flags & SC_OP_TXAGGR)
2311 ath_txq_schedule(sc, txq);
2312 spin_unlock_bh(&txq->axq_lock);
2320 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2322 struct ath_descdma *dd = &sc->txsdma;
2323 u8 txs_len = sc->sc_ah->caps.txs_len;
2325 dd->dd_desc_len = size * txs_len;
2326 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2327 &dd->dd_desc_paddr, GFP_KERNEL);
2334 static int ath_tx_edma_init(struct ath_softc *sc)
2338 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2340 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2341 sc->txsdma.dd_desc_paddr,
2342 ATH_TXSTATUS_RING_SIZE);
2347 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2349 struct ath_descdma *dd = &sc->txsdma;
2351 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2355 int ath_tx_init(struct ath_softc *sc, int nbufs)
2357 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2360 spin_lock_init(&sc->tx.txbuflock);
2362 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2365 ath_print(common, ATH_DBG_FATAL,
2366 "Failed to allocate tx descriptors: %d\n", error);
2370 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2371 "beacon", ATH_BCBUF, 1, 1);
2373 ath_print(common, ATH_DBG_FATAL,
2374 "Failed to allocate beacon descriptors: %d\n", error);
2378 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2380 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2381 error = ath_tx_edma_init(sc);
2393 void ath_tx_cleanup(struct ath_softc *sc)
2395 if (sc->beacon.bdma.dd_desc_len != 0)
2396 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2398 if (sc->tx.txdma.dd_desc_len != 0)
2399 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2401 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2402 ath_tx_edma_cleanup(sc);
2405 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2407 struct ath_atx_tid *tid;
2408 struct ath_atx_ac *ac;
2411 for (tidno = 0, tid = &an->tid[tidno];
2412 tidno < WME_NUM_TID;
2416 tid->seq_start = tid->seq_next = 0;
2417 tid->baw_size = WME_MAX_BA;
2418 tid->baw_head = tid->baw_tail = 0;
2420 tid->paused = false;
2421 tid->state &= ~AGGR_CLEANUP;
2422 INIT_LIST_HEAD(&tid->buf_q);
2423 acno = TID_TO_WME_AC(tidno);
2424 tid->ac = &an->ac[acno];
2425 tid->state &= ~AGGR_ADDBA_COMPLETE;
2426 tid->state &= ~AGGR_ADDBA_PROGRESS;
2429 for (acno = 0, ac = &an->ac[acno];
2430 acno < WME_NUM_AC; acno++, ac++) {
2432 ac->qnum = sc->tx.hwq_map[acno];
2433 INIT_LIST_HEAD(&ac->tid_q);
2437 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2439 struct ath_atx_ac *ac;
2440 struct ath_atx_tid *tid;
2441 struct ath_txq *txq;
2444 for (tidno = 0, tid = &an->tid[tidno];
2445 tidno < WME_NUM_TID; tidno++, tid++) {
2448 if (!ATH_TXQ_SETUP(sc, i))
2451 txq = &sc->tx.txq[i];
2454 spin_lock_bh(&txq->axq_lock);
2457 list_del(&tid->list);
2462 list_del(&ac->list);
2463 tid->ac->sched = false;
2466 ath_tid_drain(sc, txq, tid);
2467 tid->state &= ~AGGR_ADDBA_COMPLETE;
2468 tid->state &= ~AGGR_CLEANUP;
2470 spin_unlock_bh(&txq->axq_lock);