2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int nframes, int nbad,
62 int txok, bool update_rc);
63 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_atx_tid *tid,
77 static int ath_max_4ms_framelen[4][32] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = tid->ac->txq;
132 WARN_ON(!tid->paused);
134 spin_lock_bh(&txq->axq_lock);
137 if (skb_queue_empty(&tid->buf_q))
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
143 spin_unlock_bh(&txq->axq_lock);
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
154 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 struct ath_txq *txq = tid->ac->txq;
159 struct list_head bf_head;
160 struct ath_tx_status ts;
161 struct ath_frame_info *fi;
163 INIT_LIST_HEAD(&bf_head);
165 memset(&ts, 0, sizeof(ts));
166 spin_lock_bh(&txq->axq_lock);
168 while ((skb = __skb_dequeue(&tid->buf_q))) {
169 fi = get_frame_info(skb);
172 spin_unlock_bh(&txq->axq_lock);
173 if (bf && fi->retries) {
174 list_add_tail(&bf->list, &bf_head);
175 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
178 ath_tx_send_normal(sc, txq, NULL, skb);
180 spin_lock_bh(&txq->axq_lock);
183 spin_unlock_bh(&txq->axq_lock);
186 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
191 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
194 __clear_bit(cindex, tid->tx_buf);
196 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
197 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
198 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
202 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
207 index = ATH_BA_INDEX(tid->seq_start, seqno);
208 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
209 __set_bit(cindex, tid->tx_buf);
211 if (index >= ((tid->baw_tail - tid->baw_head) &
212 (ATH_TID_MAX_BUFS - 1))) {
213 tid->baw_tail = cindex;
214 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
219 * TODO: For frame(s) that are in the retry state, we will reuse the
220 * sequence number(s) without setting the retry bit. The
221 * alternative is to give up on these and BAR the receiver's window
224 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_atx_tid *tid)
230 struct list_head bf_head;
231 struct ath_tx_status ts;
232 struct ath_frame_info *fi;
234 memset(&ts, 0, sizeof(ts));
235 INIT_LIST_HEAD(&bf_head);
237 while ((skb = __skb_dequeue(&tid->buf_q))) {
238 fi = get_frame_info(skb);
242 spin_unlock(&txq->axq_lock);
243 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
244 spin_lock(&txq->axq_lock);
248 list_add_tail(&bf->list, &bf_head);
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
253 spin_unlock(&txq->axq_lock);
254 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
255 spin_lock(&txq->axq_lock);
258 tid->seq_next = tid->seq_start;
259 tid->baw_tail = tid->baw_head;
262 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
265 struct ath_frame_info *fi = get_frame_info(skb);
266 struct ieee80211_hdr *hdr;
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
276 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
278 struct ath_buf *bf = NULL;
280 spin_lock_bh(&sc->tx.txbuflock);
282 if (unlikely(list_empty(&sc->tx.txbuf))) {
283 spin_unlock_bh(&sc->tx.txbuflock);
287 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
290 spin_unlock_bh(&sc->tx.txbuflock);
295 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
297 spin_lock_bh(&sc->tx.txbuflock);
298 list_add_tail(&bf->list, &sc->tx.txbuf);
299 spin_unlock_bh(&sc->tx.txbuflock);
302 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
306 tbf = ath_tx_get_buffer(sc);
310 ATH_TXBUF_RESET(tbf);
312 tbf->bf_mpdu = bf->bf_mpdu;
313 tbf->bf_buf_addr = bf->bf_buf_addr;
314 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
315 tbf->bf_state = bf->bf_state;
320 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
321 struct ath_tx_status *ts, int txok,
322 int *nframes, int *nbad)
324 struct ath_frame_info *fi;
326 u32 ba[WME_BA_BMP_SIZE >> 5];
333 isaggr = bf_isaggr(bf);
335 seq_st = ts->ts_seqnum;
336 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
340 fi = get_frame_info(bf->bf_mpdu);
341 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
344 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
352 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
353 struct ath_buf *bf, struct list_head *bf_q,
354 struct ath_tx_status *ts, int txok, bool retry)
356 struct ath_node *an = NULL;
358 struct ieee80211_sta *sta;
359 struct ieee80211_hw *hw = sc->hw;
360 struct ieee80211_hdr *hdr;
361 struct ieee80211_tx_info *tx_info;
362 struct ath_atx_tid *tid = NULL;
363 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
364 struct list_head bf_head;
365 struct sk_buff_head bf_pending;
366 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
367 u32 ba[WME_BA_BMP_SIZE >> 5];
368 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
369 bool rc_update = true;
370 struct ieee80211_tx_rate rates[4];
371 struct ath_frame_info *fi;
377 hdr = (struct ieee80211_hdr *)skb->data;
379 tx_info = IEEE80211_SKB_CB(skb);
381 memcpy(rates, tx_info->control.rates, sizeof(rates));
385 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
389 INIT_LIST_HEAD(&bf_head);
391 bf_next = bf->bf_next;
393 if (!bf->bf_stale || bf_next != NULL)
394 list_move_tail(&bf->list, &bf_head);
396 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
397 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
405 an = (struct ath_node *)sta->drv_priv;
406 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
407 tid = ATH_AN_2_TID(an, tidno);
410 * The hardware occasionally sends a tx status for the wrong TID.
411 * In this case, the BA status cannot be considered valid and all
412 * subframes need to be retransmitted
414 if (tidno != ts->tid)
417 isaggr = bf_isaggr(bf);
418 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
420 if (isaggr && txok) {
421 if (ts->ts_flags & ATH9K_TX_BA) {
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
426 * AR5416 can become deaf/mute when BA
427 * issue happens. Chip needs to be reset.
428 * But AP code may have sychronization issues
429 * when perform internal reset in this routine.
430 * Only enable reset in STA mode for now.
432 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
437 __skb_queue_head_init(&bf_pending);
439 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
441 u16 seqno = bf->bf_state.seqno;
443 txfail = txpending = sendbar = 0;
444 bf_next = bf->bf_next;
447 tx_info = IEEE80211_SKB_CB(skb);
448 fi = get_frame_info(skb);
450 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
451 /* transmit completion, subframe is
452 * acked by block ack */
454 } else if (!isaggr && txok) {
455 /* transmit completion */
458 if ((tid->state & AGGR_CLEANUP) || !retry) {
460 * cleanup in progress, just fail
461 * the un-acked sub-frames
464 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
465 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
467 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
479 * Make sure the last desc is reclaimed if it
480 * not a holding desc.
482 INIT_LIST_HEAD(&bf_head);
483 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
484 bf_next != NULL || !bf_last->bf_stale)
485 list_move_tail(&bf->list, &bf_head);
487 if (!txpending || (tid->state & AGGR_CLEANUP)) {
489 * complete the acked-ones/xretried ones; update
492 spin_lock_bh(&txq->axq_lock);
493 ath_tx_update_baw(sc, tid, seqno);
494 spin_unlock_bh(&txq->axq_lock);
496 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
497 memcpy(tx_info->control.rates, rates, sizeof(rates));
498 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
501 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
504 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
507 /* retry the un-acked ones */
508 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
509 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
510 if (bf->bf_next == NULL && bf_last->bf_stale) {
513 tbf = ath_clone_txbuf(sc, bf_last);
515 * Update tx baw and complete the
516 * frame with failed status if we
520 spin_lock_bh(&txq->axq_lock);
521 ath_tx_update_baw(sc, tid, seqno);
522 spin_unlock_bh(&txq->axq_lock);
524 ath_tx_rc_status(sc, bf, ts, nframes,
526 ath_tx_complete_buf(sc, bf, txq,
532 ath9k_hw_cleartxdesc(sc->sc_ah,
537 * Clear descriptor status words for
540 ath9k_hw_cleartxdesc(sc->sc_ah,
546 * Put this buffer to the temporary pending
547 * queue to retain ordering
549 __skb_queue_tail(&bf_pending, skb);
555 /* prepend un-acked frames to the beginning of the pending frame queue */
556 if (!skb_queue_empty(&bf_pending)) {
558 ieee80211_sta_set_tim(sta);
560 spin_lock_bh(&txq->axq_lock);
562 tid->ac->clear_ps_filter = true;
563 skb_queue_splice(&bf_pending, &tid->buf_q);
565 ath_tx_queue_tid(txq, tid);
566 spin_unlock_bh(&txq->axq_lock);
569 if (tid->state & AGGR_CLEANUP) {
570 ath_tx_flush_tid(sc, tid);
572 if (tid->baw_head == tid->baw_tail) {
573 tid->state &= ~AGGR_ADDBA_COMPLETE;
574 tid->state &= ~AGGR_CLEANUP;
581 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
584 static bool ath_lookup_legacy(struct ath_buf *bf)
587 struct ieee80211_tx_info *tx_info;
588 struct ieee80211_tx_rate *rates;
592 tx_info = IEEE80211_SKB_CB(skb);
593 rates = tx_info->control.rates;
595 for (i = 0; i < 4; i++) {
596 if (!rates[i].count || rates[i].idx < 0)
599 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
606 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
607 struct ath_atx_tid *tid)
610 struct ieee80211_tx_info *tx_info;
611 struct ieee80211_tx_rate *rates;
612 u32 max_4ms_framelen, frmlen;
613 u16 aggr_limit, legacy = 0;
617 tx_info = IEEE80211_SKB_CB(skb);
618 rates = tx_info->control.rates;
621 * Find the lowest frame length among the rate series that will have a
622 * 4ms transmit duration.
623 * TODO - TXOP limit needs to be considered.
625 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
627 for (i = 0; i < 4; i++) {
628 if (rates[i].count) {
630 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
635 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
640 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
643 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
644 max_4ms_framelen = min(max_4ms_framelen, frmlen);
649 * limit aggregate size by the minimum rate if rate selected is
650 * not a probe rate, if rate selected is a probe rate then
651 * avoid aggregation of this packet.
653 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
656 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
657 aggr_limit = min((max_4ms_framelen * 3) / 8,
658 (u32)ATH_AMPDU_LIMIT_MAX);
660 aggr_limit = min(max_4ms_framelen,
661 (u32)ATH_AMPDU_LIMIT_MAX);
664 * h/w can accept aggregates up to 16 bit lengths (65535).
665 * The IE, however can hold up to 65536, which shows up here
666 * as zero. Ignore 65536 since we are constrained by hw.
668 if (tid->an->maxampdu)
669 aggr_limit = min(aggr_limit, tid->an->maxampdu);
675 * Returns the number of delimiters to be added to
676 * meet the minimum required mpdudensity.
678 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
679 struct ath_buf *bf, u16 frmlen,
682 #define FIRST_DESC_NDELIMS 60
683 struct sk_buff *skb = bf->bf_mpdu;
684 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
685 u32 nsymbits, nsymbols;
688 int width, streams, half_gi, ndelim, mindelim;
689 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
691 /* Select standard number of delimiters based on frame length alone */
692 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
695 * If encryption enabled, hardware requires some more padding between
697 * TODO - this could be improved to be dependent on the rate.
698 * The hardware can keep up at lower rates, but not higher rates
700 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
701 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
702 ndelim += ATH_AGGR_ENCRYPTDELIM;
705 * Add delimiter when using RTS/CTS with aggregation
706 * and non enterprise AR9003 card
708 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
709 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
710 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
713 * Convert desired mpdu density from microeconds to bytes based
714 * on highest rate in rate series (i.e. first rate) to determine
715 * required minimum length for subframe. Take into account
716 * whether high rate is 20 or 40Mhz and half or full GI.
718 * If there is no mpdu density restriction, no further calculation
722 if (tid->an->mpdudensity == 0)
725 rix = tx_info->control.rates[0].idx;
726 flags = tx_info->control.rates[0].flags;
727 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
728 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
731 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
733 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
738 streams = HT_RC_2_STREAMS(rix);
739 nsymbits = bits_per_symbol[rix % 8][width] * streams;
740 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
742 if (frmlen < minlen) {
743 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
744 ndelim = max(mindelim, ndelim);
750 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
752 struct ath_atx_tid *tid,
753 struct list_head *bf_q,
756 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
757 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
758 int rl = 0, nframes = 0, ndelim, prev_al = 0;
759 u16 aggr_limit = 0, al = 0, bpad = 0,
760 al_delta, h_baw = tid->baw_size / 2;
761 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
762 struct ieee80211_tx_info *tx_info;
763 struct ath_frame_info *fi;
768 skb = skb_peek(&tid->buf_q);
769 fi = get_frame_info(skb);
772 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
777 bf->bf_state.bf_type |= BUF_AMPDU;
778 seqno = bf->bf_state.seqno;
782 /* do not step over block-ack window */
783 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
784 status = ATH_AGGR_BAW_CLOSED;
789 aggr_limit = ath_lookup_rate(sc, bf, tid);
793 /* do not exceed aggregation limit */
794 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
797 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
798 ath_lookup_legacy(bf))) {
799 status = ATH_AGGR_LIMITED;
803 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
804 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
805 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
808 /* do not exceed subframe limit */
809 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
810 status = ATH_AGGR_LIMITED;
814 /* add padding for previous frame to aggregation length */
815 al += bpad + al_delta;
818 * Get the delimiters needed to meet the MPDU
819 * density for this node.
821 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
823 bpad = PADBYTES(al_delta) + (ndelim << 2);
827 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
829 /* link buffers of this frame to the aggregate */
831 ath_tx_addto_baw(sc, tid, seqno);
832 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
834 __skb_unlink(skb, &tid->buf_q);
835 list_add_tail(&bf->list, bf_q);
837 bf_prev->bf_next = bf;
838 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
843 } while (!skb_queue_empty(&tid->buf_q));
851 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
852 struct ath_atx_tid *tid)
855 enum ATH_AGGR_STATUS status;
856 struct ath_frame_info *fi;
857 struct list_head bf_q;
861 if (skb_queue_empty(&tid->buf_q))
864 INIT_LIST_HEAD(&bf_q);
866 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
869 * no frames picked up to be aggregated;
870 * block-ack window is not open.
872 if (list_empty(&bf_q))
875 bf = list_first_entry(&bf_q, struct ath_buf, list);
876 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
878 if (tid->ac->clear_ps_filter) {
879 tid->ac->clear_ps_filter = false;
880 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
883 /* if only one frame, send as non-aggregate */
884 if (bf == bf->bf_lastbf) {
885 fi = get_frame_info(bf->bf_mpdu);
887 bf->bf_state.bf_type &= ~BUF_AGGR;
888 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
889 ath_buf_set_rate(sc, bf, fi->framelen);
890 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
894 /* setup first desc of aggregate */
895 bf->bf_state.bf_type |= BUF_AGGR;
896 ath_buf_set_rate(sc, bf, aggr_len);
897 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
899 /* anchor last desc of aggregate */
900 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
902 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
903 TX_STAT_INC(txq->axq_qnum, a_aggr);
905 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
906 status != ATH_AGGR_BAW_CLOSED);
909 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
912 struct ath_atx_tid *txtid;
915 an = (struct ath_node *)sta->drv_priv;
916 txtid = ATH_AN_2_TID(an, tid);
918 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
921 txtid->state |= AGGR_ADDBA_PROGRESS;
922 txtid->paused = true;
923 *ssn = txtid->seq_start = txtid->seq_next;
925 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
926 txtid->baw_head = txtid->baw_tail = 0;
931 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
933 struct ath_node *an = (struct ath_node *)sta->drv_priv;
934 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
935 struct ath_txq *txq = txtid->ac->txq;
937 if (txtid->state & AGGR_CLEANUP)
940 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
941 txtid->state &= ~AGGR_ADDBA_PROGRESS;
945 spin_lock_bh(&txq->axq_lock);
946 txtid->paused = true;
949 * If frames are still being transmitted for this TID, they will be
950 * cleaned up during tx completion. To prevent race conditions, this
951 * TID can only be reused after all in-progress subframes have been
954 if (txtid->baw_head != txtid->baw_tail)
955 txtid->state |= AGGR_CLEANUP;
957 txtid->state &= ~AGGR_ADDBA_COMPLETE;
958 spin_unlock_bh(&txq->axq_lock);
960 ath_tx_flush_tid(sc, txtid);
963 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
965 struct ath_atx_tid *tid;
966 struct ath_atx_ac *ac;
968 bool buffered = false;
971 for (tidno = 0, tid = &an->tid[tidno];
972 tidno < WME_NUM_TID; tidno++, tid++) {
980 spin_lock_bh(&txq->axq_lock);
982 if (!skb_queue_empty(&tid->buf_q))
986 list_del(&tid->list);
993 spin_unlock_bh(&txq->axq_lock);
999 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1001 struct ath_atx_tid *tid;
1002 struct ath_atx_ac *ac;
1003 struct ath_txq *txq;
1006 for (tidno = 0, tid = &an->tid[tidno];
1007 tidno < WME_NUM_TID; tidno++, tid++) {
1012 spin_lock_bh(&txq->axq_lock);
1013 ac->clear_ps_filter = true;
1015 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1016 ath_tx_queue_tid(txq, tid);
1017 ath_txq_schedule(sc, txq);
1020 spin_unlock_bh(&txq->axq_lock);
1024 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1026 struct ath_atx_tid *txtid;
1027 struct ath_node *an;
1029 an = (struct ath_node *)sta->drv_priv;
1031 if (sc->sc_flags & SC_OP_TXAGGR) {
1032 txtid = ATH_AN_2_TID(an, tid);
1034 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1035 txtid->state |= AGGR_ADDBA_COMPLETE;
1036 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1037 ath_tx_resume_tid(sc, txtid);
1041 /********************/
1042 /* Queue Management */
1043 /********************/
1045 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1046 struct ath_txq *txq)
1048 struct ath_atx_ac *ac, *ac_tmp;
1049 struct ath_atx_tid *tid, *tid_tmp;
1051 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1052 list_del(&ac->list);
1054 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1055 list_del(&tid->list);
1057 ath_tid_drain(sc, txq, tid);
1062 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1064 struct ath_hw *ah = sc->sc_ah;
1065 struct ath_common *common = ath9k_hw_common(ah);
1066 struct ath9k_tx_queue_info qi;
1067 static const int subtype_txq_to_hwq[] = {
1068 [WME_AC_BE] = ATH_TXQ_AC_BE,
1069 [WME_AC_BK] = ATH_TXQ_AC_BK,
1070 [WME_AC_VI] = ATH_TXQ_AC_VI,
1071 [WME_AC_VO] = ATH_TXQ_AC_VO,
1075 memset(&qi, 0, sizeof(qi));
1076 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1077 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1078 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1079 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1080 qi.tqi_physCompBuf = 0;
1083 * Enable interrupts only for EOL and DESC conditions.
1084 * We mark tx descriptors to receive a DESC interrupt
1085 * when a tx queue gets deep; otherwise waiting for the
1086 * EOL to reap descriptors. Note that this is done to
1087 * reduce interrupt load and this only defers reaping
1088 * descriptors, never transmitting frames. Aside from
1089 * reducing interrupts this also permits more concurrency.
1090 * The only potential downside is if the tx queue backs
1091 * up in which case the top half of the kernel may backup
1092 * due to a lack of tx descriptors.
1094 * The UAPSD queue is an exception, since we take a desc-
1095 * based intr on the EOSP frames.
1097 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1098 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1099 TXQ_FLAG_TXERRINT_ENABLE;
1101 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1102 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1104 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1105 TXQ_FLAG_TXDESCINT_ENABLE;
1107 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1108 if (axq_qnum == -1) {
1110 * NB: don't print a message, this happens
1111 * normally on parts with too few tx queues
1115 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1116 ath_err(common, "qnum %u out of range, max %zu!\n",
1117 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1118 ath9k_hw_releasetxqueue(ah, axq_qnum);
1121 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1122 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1124 txq->axq_qnum = axq_qnum;
1125 txq->mac80211_qnum = -1;
1126 txq->axq_link = NULL;
1127 INIT_LIST_HEAD(&txq->axq_q);
1128 INIT_LIST_HEAD(&txq->axq_acq);
1129 spin_lock_init(&txq->axq_lock);
1131 txq->axq_ampdu_depth = 0;
1132 txq->axq_tx_inprogress = false;
1133 sc->tx.txqsetup |= 1<<axq_qnum;
1135 txq->txq_headidx = txq->txq_tailidx = 0;
1136 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1137 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1139 return &sc->tx.txq[axq_qnum];
1142 int ath_txq_update(struct ath_softc *sc, int qnum,
1143 struct ath9k_tx_queue_info *qinfo)
1145 struct ath_hw *ah = sc->sc_ah;
1147 struct ath9k_tx_queue_info qi;
1149 if (qnum == sc->beacon.beaconq) {
1151 * XXX: for beacon queue, we just save the parameter.
1152 * It will be picked up by ath_beaconq_config when
1155 sc->beacon.beacon_qi = *qinfo;
1159 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1161 ath9k_hw_get_txq_props(ah, qnum, &qi);
1162 qi.tqi_aifs = qinfo->tqi_aifs;
1163 qi.tqi_cwmin = qinfo->tqi_cwmin;
1164 qi.tqi_cwmax = qinfo->tqi_cwmax;
1165 qi.tqi_burstTime = qinfo->tqi_burstTime;
1166 qi.tqi_readyTime = qinfo->tqi_readyTime;
1168 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1169 ath_err(ath9k_hw_common(sc->sc_ah),
1170 "Unable to update hardware queue %u!\n", qnum);
1173 ath9k_hw_resettxqueue(ah, qnum);
1179 int ath_cabq_update(struct ath_softc *sc)
1181 struct ath9k_tx_queue_info qi;
1182 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1183 int qnum = sc->beacon.cabq->axq_qnum;
1185 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1187 * Ensure the readytime % is within the bounds.
1189 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1190 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1191 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1192 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1194 qi.tqi_readyTime = (cur_conf->beacon_interval *
1195 sc->config.cabqReadytime) / 100;
1196 ath_txq_update(sc, qnum, &qi);
1201 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1203 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1204 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1207 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1208 struct list_head *list, bool retry_tx)
1209 __releases(txq->axq_lock)
1210 __acquires(txq->axq_lock)
1212 struct ath_buf *bf, *lastbf;
1213 struct list_head bf_head;
1214 struct ath_tx_status ts;
1216 memset(&ts, 0, sizeof(ts));
1217 INIT_LIST_HEAD(&bf_head);
1219 while (!list_empty(list)) {
1220 bf = list_first_entry(list, struct ath_buf, list);
1223 list_del(&bf->list);
1225 ath_tx_return_buffer(sc, bf);
1229 lastbf = bf->bf_lastbf;
1230 list_cut_position(&bf_head, list, &lastbf->list);
1233 if (bf_is_ampdu_not_probing(bf))
1234 txq->axq_ampdu_depth--;
1236 spin_unlock_bh(&txq->axq_lock);
1238 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1242 spin_lock_bh(&txq->axq_lock);
1247 * Drain a given TX queue (could be Beacon or Data)
1249 * This assumes output has been stopped and
1250 * we do not need to block ath_tx_tasklet.
1252 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1254 spin_lock_bh(&txq->axq_lock);
1255 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1256 int idx = txq->txq_tailidx;
1258 while (!list_empty(&txq->txq_fifo[idx])) {
1259 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1262 INCR(idx, ATH_TXFIFO_DEPTH);
1264 txq->txq_tailidx = idx;
1267 txq->axq_link = NULL;
1268 txq->axq_tx_inprogress = false;
1269 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1271 /* flush any pending frames if aggregation is enabled */
1272 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1273 ath_txq_drain_pending_buffers(sc, txq);
1275 spin_unlock_bh(&txq->axq_lock);
1278 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1280 struct ath_hw *ah = sc->sc_ah;
1281 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1282 struct ath_txq *txq;
1285 if (sc->sc_flags & SC_OP_INVALID)
1288 ath9k_hw_abort_tx_dma(ah);
1290 /* Check if any queue remains active */
1291 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1292 if (!ATH_TXQ_SETUP(sc, i))
1295 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1299 ath_err(common, "Failed to stop TX DMA!\n");
1301 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1302 if (!ATH_TXQ_SETUP(sc, i))
1306 * The caller will resume queues with ieee80211_wake_queues.
1307 * Mark the queue as not stopped to prevent ath_tx_complete
1308 * from waking the queue too early.
1310 txq = &sc->tx.txq[i];
1311 txq->stopped = false;
1312 ath_draintxq(sc, txq, retry_tx);
1318 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1320 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1321 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1324 /* For each axq_acq entry, for each tid, try to schedule packets
1325 * for transmit until ampdu_depth has reached min Q depth.
1327 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1329 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1330 struct ath_atx_tid *tid, *last_tid;
1332 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1333 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1336 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1337 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1339 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1340 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1341 list_del(&ac->list);
1344 while (!list_empty(&ac->tid_q)) {
1345 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1347 list_del(&tid->list);
1353 ath_tx_sched_aggr(sc, txq, tid);
1356 * add tid to round-robin queue if more frames
1357 * are pending for the tid
1359 if (!skb_queue_empty(&tid->buf_q))
1360 ath_tx_queue_tid(txq, tid);
1362 if (tid == last_tid ||
1363 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1367 if (!list_empty(&ac->tid_q)) {
1370 list_add_tail(&ac->list, &txq->axq_acq);
1374 if (ac == last_ac ||
1375 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1385 * Insert a chain of ath_buf (descriptors) on a txq and
1386 * assume the descriptors are already chained together by caller.
1388 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1389 struct list_head *head, bool internal)
1391 struct ath_hw *ah = sc->sc_ah;
1392 struct ath_common *common = ath9k_hw_common(ah);
1393 struct ath_buf *bf, *bf_last;
1394 bool puttxbuf = false;
1398 * Insert the frame on the outbound list and
1399 * pass it on to the hardware.
1402 if (list_empty(head))
1405 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1406 bf = list_first_entry(head, struct ath_buf, list);
1407 bf_last = list_entry(head->prev, struct ath_buf, list);
1409 ath_dbg(common, ATH_DBG_QUEUE,
1410 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1412 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1413 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1414 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1417 list_splice_tail_init(head, &txq->axq_q);
1419 if (txq->axq_link) {
1420 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1421 ath_dbg(common, ATH_DBG_XMIT,
1422 "link[%u] (%p)=%llx (%p)\n",
1423 txq->axq_qnum, txq->axq_link,
1424 ito64(bf->bf_daddr), bf->bf_desc);
1428 txq->axq_link = bf_last->bf_desc;
1432 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1433 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1434 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1435 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1439 TX_STAT_INC(txq->axq_qnum, txstart);
1440 ath9k_hw_txstart(ah, txq->axq_qnum);
1445 if (bf_is_ampdu_not_probing(bf))
1446 txq->axq_ampdu_depth++;
1450 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1451 struct sk_buff *skb, struct ath_tx_control *txctl)
1453 struct ath_frame_info *fi = get_frame_info(skb);
1454 struct list_head bf_head;
1458 * Do not queue to h/w when any of the following conditions is true:
1459 * - there are pending frames in software queue
1460 * - the TID is currently paused for ADDBA/BAR request
1461 * - seqno is not within block-ack window
1462 * - h/w queue depth exceeds low water mark
1464 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1465 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1466 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1468 * Add this frame to software queue for scheduling later
1471 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1472 __skb_queue_tail(&tid->buf_q, skb);
1473 if (!txctl->an || !txctl->an->sleeping)
1474 ath_tx_queue_tid(txctl->txq, tid);
1478 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1482 bf->bf_state.bf_type |= BUF_AMPDU;
1483 INIT_LIST_HEAD(&bf_head);
1484 list_add(&bf->list, &bf_head);
1486 /* Add sub-frame to BAW */
1487 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1489 /* Queue to h/w without aggregation */
1490 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1492 ath_buf_set_rate(sc, bf, fi->framelen);
1493 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1496 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1497 struct ath_atx_tid *tid, struct sk_buff *skb)
1499 struct ath_frame_info *fi = get_frame_info(skb);
1500 struct list_head bf_head;
1505 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1510 INIT_LIST_HEAD(&bf_head);
1511 list_add_tail(&bf->list, &bf_head);
1512 bf->bf_state.bf_type &= ~BUF_AMPDU;
1514 /* update starting sequence number for subsequent ADDBA request */
1516 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1519 ath_buf_set_rate(sc, bf, fi->framelen);
1520 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1521 TX_STAT_INC(txq->axq_qnum, queued);
1524 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1526 struct ieee80211_hdr *hdr;
1527 enum ath9k_pkt_type htype;
1530 hdr = (struct ieee80211_hdr *)skb->data;
1531 fc = hdr->frame_control;
1533 if (ieee80211_is_beacon(fc))
1534 htype = ATH9K_PKT_TYPE_BEACON;
1535 else if (ieee80211_is_probe_resp(fc))
1536 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1537 else if (ieee80211_is_atim(fc))
1538 htype = ATH9K_PKT_TYPE_ATIM;
1539 else if (ieee80211_is_pspoll(fc))
1540 htype = ATH9K_PKT_TYPE_PSPOLL;
1542 htype = ATH9K_PKT_TYPE_NORMAL;
1547 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1550 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1551 struct ieee80211_sta *sta = tx_info->control.sta;
1552 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1553 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1554 struct ath_frame_info *fi = get_frame_info(skb);
1555 struct ath_node *an = NULL;
1556 enum ath9k_key_type keytype;
1558 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1561 an = (struct ath_node *) sta->drv_priv;
1563 memset(fi, 0, sizeof(*fi));
1565 fi->keyix = hw_key->hw_key_idx;
1566 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1567 fi->keyix = an->ps_key;
1569 fi->keyix = ATH9K_TXKEYIX_INVALID;
1570 fi->keytype = keytype;
1571 fi->framelen = framelen;
1574 static int setup_tx_flags(struct sk_buff *skb)
1576 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1579 flags |= ATH9K_TXDESC_INTREQ;
1581 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1582 flags |= ATH9K_TXDESC_NOACK;
1584 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1585 flags |= ATH9K_TXDESC_LDPC;
1592 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1593 * width - 0 for 20 MHz, 1 for 40 MHz
1594 * half_gi - to use 4us v/s 3.6 us for symbol time
1596 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1597 int width, int half_gi, bool shortPreamble)
1599 u32 nbits, nsymbits, duration, nsymbols;
1602 /* find number of symbols: PLCP + data */
1603 streams = HT_RC_2_STREAMS(rix);
1604 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1605 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1606 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1609 duration = SYMBOL_TIME(nsymbols);
1611 duration = SYMBOL_TIME_HALFGI(nsymbols);
1613 /* addup duration for legacy/ht training and signal fields */
1614 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1619 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1621 struct ath_hw *ah = sc->sc_ah;
1622 struct ath9k_channel *curchan = ah->curchan;
1623 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1624 (curchan->channelFlags & CHANNEL_5GHZ) &&
1625 (chainmask == 0x7) && (rate < 0x90))
1631 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1633 struct ath_hw *ah = sc->sc_ah;
1634 struct ath9k_11n_rate_series series[4];
1635 struct sk_buff *skb;
1636 struct ieee80211_tx_info *tx_info;
1637 struct ieee80211_tx_rate *rates;
1638 const struct ieee80211_rate *rate;
1639 struct ieee80211_hdr *hdr;
1641 u8 rix = 0, ctsrate = 0;
1644 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1647 tx_info = IEEE80211_SKB_CB(skb);
1648 rates = tx_info->control.rates;
1649 hdr = (struct ieee80211_hdr *)skb->data;
1650 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1653 * We check if Short Preamble is needed for the CTS rate by
1654 * checking the BSS's global flag.
1655 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1657 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1658 ctsrate = rate->hw_value;
1659 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1660 ctsrate |= rate->hw_value_short;
1662 for (i = 0; i < 4; i++) {
1663 bool is_40, is_sgi, is_sp;
1666 if (!rates[i].count || (rates[i].idx < 0))
1670 series[i].Tries = rates[i].count;
1672 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1673 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1674 flags |= ATH9K_TXDESC_RTSENA;
1675 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1676 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1677 flags |= ATH9K_TXDESC_CTSENA;
1680 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1681 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1682 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1683 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1685 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1686 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1687 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1689 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1691 series[i].Rate = rix | 0x80;
1692 series[i].ChSel = ath_txchainmask_reduction(sc,
1693 ah->txchainmask, series[i].Rate);
1694 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1695 is_40, is_sgi, is_sp);
1696 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1697 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1702 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1703 !(rate->flags & IEEE80211_RATE_ERP_G))
1704 phy = WLAN_RC_PHY_CCK;
1706 phy = WLAN_RC_PHY_OFDM;
1708 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1709 series[i].Rate = rate->hw_value;
1710 if (rate->hw_value_short) {
1711 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1712 series[i].Rate |= rate->hw_value_short;
1717 if (bf->bf_state.bfs_paprd)
1718 series[i].ChSel = ah->txchainmask;
1720 series[i].ChSel = ath_txchainmask_reduction(sc,
1721 ah->txchainmask, series[i].Rate);
1723 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1724 phy, rate->bitrate * 100, len, rix, is_sp);
1727 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1728 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1729 flags &= ~ATH9K_TXDESC_RTSENA;
1731 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1732 if (flags & ATH9K_TXDESC_RTSENA)
1733 flags &= ~ATH9K_TXDESC_CTSENA;
1735 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1736 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1737 bf->bf_lastbf->bf_desc,
1738 !is_pspoll, ctsrate,
1739 0, series, 4, flags);
1744 * Assign a descriptor (and sequence number if necessary,
1745 * and map buffer for DMA. Frees skb on error
1747 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1748 struct ath_txq *txq,
1749 struct ath_atx_tid *tid,
1750 struct sk_buff *skb)
1752 struct ath_hw *ah = sc->sc_ah;
1753 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1754 struct ath_frame_info *fi = get_frame_info(skb);
1755 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1757 struct ath_desc *ds;
1761 bf = ath_tx_get_buffer(sc);
1763 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1767 ATH_TXBUF_RESET(bf);
1770 seqno = tid->seq_next;
1771 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1772 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1773 bf->bf_state.seqno = seqno;
1776 bf->bf_flags = setup_tx_flags(skb);
1779 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1780 skb->len, DMA_TO_DEVICE);
1781 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1783 bf->bf_buf_addr = 0;
1784 ath_err(ath9k_hw_common(sc->sc_ah),
1785 "dma_mapping_error() on TX\n");
1786 ath_tx_return_buffer(sc, bf);
1790 frm_type = get_hw_packet_type(skb);
1793 ath9k_hw_set_desc_link(ah, ds, 0);
1795 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1796 fi->keyix, fi->keytype, bf->bf_flags);
1798 ath9k_hw_filltxdesc(ah, ds,
1799 skb->len, /* segment length */
1800 true, /* first segment */
1801 true, /* last segment */
1802 ds, /* first descriptor */
1811 dev_kfree_skb_any(skb);
1815 /* FIXME: tx power */
1816 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1817 struct ath_tx_control *txctl)
1819 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1820 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1821 struct ath_atx_tid *tid = NULL;
1825 spin_lock_bh(&txctl->txq->axq_lock);
1826 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1827 ieee80211_is_data_qos(hdr->frame_control)) {
1828 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1829 IEEE80211_QOS_CTL_TID_MASK;
1830 tid = ATH_AN_2_TID(txctl->an, tidno);
1832 WARN_ON(tid->ac->txq != txctl->txq);
1835 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1837 * Try aggregation if it's a unicast data frame
1838 * and the destination is HT capable.
1840 ath_tx_send_ampdu(sc, tid, skb, txctl);
1842 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1846 bf->bf_state.bfs_paprd = txctl->paprd;
1848 if (bf->bf_state.bfs_paprd)
1849 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1850 bf->bf_state.bfs_paprd);
1853 bf->bf_state.bfs_paprd_timestamp = jiffies;
1855 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1856 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1858 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1862 spin_unlock_bh(&txctl->txq->axq_lock);
1865 /* Upon failure caller should free skb */
1866 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1867 struct ath_tx_control *txctl)
1869 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1870 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1871 struct ieee80211_sta *sta = info->control.sta;
1872 struct ieee80211_vif *vif = info->control.vif;
1873 struct ath_softc *sc = hw->priv;
1874 struct ath_txq *txq = txctl->txq;
1875 int padpos, padsize;
1876 int frmlen = skb->len + FCS_LEN;
1879 /* NOTE: sta can be NULL according to net/mac80211.h */
1881 txctl->an = (struct ath_node *)sta->drv_priv;
1883 if (info->control.hw_key)
1884 frmlen += info->control.hw_key->icv_len;
1887 * As a temporary workaround, assign seq# here; this will likely need
1888 * to be cleaned up to work better with Beacon transmission and virtual
1891 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1892 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1893 sc->tx.seq_no += 0x10;
1894 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1895 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1898 /* Add the padding after the header if this is not already done */
1899 padpos = ath9k_cmn_padpos(hdr->frame_control);
1900 padsize = padpos & 3;
1901 if (padsize && skb->len > padpos) {
1902 if (skb_headroom(skb) < padsize)
1905 skb_push(skb, padsize);
1906 memmove(skb->data, skb->data + padsize, padpos);
1909 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1910 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1911 !ieee80211_is_data(hdr->frame_control))
1912 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1914 setup_frame_info(hw, skb, frmlen);
1917 * At this point, the vif, hw_key and sta pointers in the tx control
1918 * info are no longer valid (overwritten by the ath_frame_info data.
1921 q = skb_get_queue_mapping(skb);
1922 spin_lock_bh(&txq->axq_lock);
1923 if (txq == sc->tx.txq_map[q] &&
1924 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1925 ieee80211_stop_queue(sc->hw, q);
1928 spin_unlock_bh(&txq->axq_lock);
1930 ath_tx_start_dma(sc, skb, txctl);
1938 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1939 int tx_flags, struct ath_txq *txq)
1941 struct ieee80211_hw *hw = sc->hw;
1942 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1943 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1944 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1945 int q, padpos, padsize;
1947 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1949 if (tx_flags & ATH_TX_BAR)
1950 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1952 if (!(tx_flags & ATH_TX_ERROR))
1953 /* Frame was ACKed */
1954 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1956 padpos = ath9k_cmn_padpos(hdr->frame_control);
1957 padsize = padpos & 3;
1958 if (padsize && skb->len>padpos+padsize) {
1960 * Remove MAC header padding before giving the frame back to
1963 memmove(skb->data + padsize, skb->data, padpos);
1964 skb_pull(skb, padsize);
1967 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1968 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1969 ath_dbg(common, ATH_DBG_PS,
1970 "Going back to sleep after having received TX status (0x%lx)\n",
1971 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1973 PS_WAIT_FOR_PSPOLL_DATA |
1974 PS_WAIT_FOR_TX_ACK));
1977 q = skb_get_queue_mapping(skb);
1978 if (txq == sc->tx.txq_map[q]) {
1979 spin_lock_bh(&txq->axq_lock);
1980 if (WARN_ON(--txq->pending_frames < 0))
1981 txq->pending_frames = 0;
1983 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1984 ieee80211_wake_queue(sc->hw, q);
1987 spin_unlock_bh(&txq->axq_lock);
1990 ieee80211_tx_status(hw, skb);
1993 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1994 struct ath_txq *txq, struct list_head *bf_q,
1995 struct ath_tx_status *ts, int txok, int sendbar)
1997 struct sk_buff *skb = bf->bf_mpdu;
1998 unsigned long flags;
2002 tx_flags = ATH_TX_BAR;
2005 tx_flags |= ATH_TX_ERROR;
2007 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2008 bf->bf_buf_addr = 0;
2010 if (bf->bf_state.bfs_paprd) {
2011 if (time_after(jiffies,
2012 bf->bf_state.bfs_paprd_timestamp +
2013 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2014 dev_kfree_skb_any(skb);
2016 complete(&sc->paprd_complete);
2018 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2019 ath_tx_complete(sc, skb, tx_flags, txq);
2021 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2022 * accidentally reference it later.
2027 * Return the list of ath_buf of this mpdu to free queue
2029 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2030 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2031 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2034 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2035 struct ath_tx_status *ts, int nframes, int nbad,
2036 int txok, bool update_rc)
2038 struct sk_buff *skb = bf->bf_mpdu;
2039 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2040 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2041 struct ieee80211_hw *hw = sc->hw;
2042 struct ath_hw *ah = sc->sc_ah;
2046 tx_info->status.ack_signal = ts->ts_rssi;
2048 tx_rateindex = ts->ts_rateindex;
2049 WARN_ON(tx_rateindex >= hw->max_rates);
2051 if (ts->ts_status & ATH9K_TXERR_FILT)
2052 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2053 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2054 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2056 BUG_ON(nbad > nframes);
2058 tx_info->status.ampdu_len = nframes;
2059 tx_info->status.ampdu_ack_len = nframes - nbad;
2062 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2063 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2065 * If an underrun error is seen assume it as an excessive
2066 * retry only if max frame trigger level has been reached
2067 * (2 KB for single stream, and 4 KB for dual stream).
2068 * Adjust the long retry as if the frame was tried
2069 * hw->max_rate_tries times to affect how rate control updates
2070 * PER for the failed rate.
2071 * In case of congestion on the bus penalizing this type of
2072 * underruns should help hardware actually transmit new frames
2073 * successfully by eventually preferring slower rates.
2074 * This itself should also alleviate congestion on the bus.
2076 if (ieee80211_is_data(hdr->frame_control) &&
2077 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2078 ATH9K_TX_DELIM_UNDERRUN)) &&
2079 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2080 tx_info->status.rates[tx_rateindex].count =
2084 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2085 tx_info->status.rates[i].count = 0;
2086 tx_info->status.rates[i].idx = -1;
2089 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2092 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2093 struct ath_tx_status *ts, struct ath_buf *bf,
2094 struct list_head *bf_head)
2095 __releases(txq->axq_lock)
2096 __acquires(txq->axq_lock)
2101 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2102 txq->axq_tx_inprogress = false;
2103 if (bf_is_ampdu_not_probing(bf))
2104 txq->axq_ampdu_depth--;
2106 spin_unlock_bh(&txq->axq_lock);
2108 if (!bf_isampdu(bf)) {
2109 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2110 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2112 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2114 spin_lock_bh(&txq->axq_lock);
2116 if (sc->sc_flags & SC_OP_TXAGGR)
2117 ath_txq_schedule(sc, txq);
2120 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2122 struct ath_hw *ah = sc->sc_ah;
2123 struct ath_common *common = ath9k_hw_common(ah);
2124 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2125 struct list_head bf_head;
2126 struct ath_desc *ds;
2127 struct ath_tx_status ts;
2130 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2131 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2134 spin_lock_bh(&txq->axq_lock);
2136 if (work_pending(&sc->hw_reset_work))
2139 if (list_empty(&txq->axq_q)) {
2140 txq->axq_link = NULL;
2141 if (sc->sc_flags & SC_OP_TXAGGR)
2142 ath_txq_schedule(sc, txq);
2145 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2148 * There is a race condition that a BH gets scheduled
2149 * after sw writes TxE and before hw re-load the last
2150 * descriptor to get the newly chained one.
2151 * Software must keep the last DONE descriptor as a
2152 * holding descriptor - software does so by marking
2153 * it with the STALE flag.
2158 if (list_is_last(&bf_held->list, &txq->axq_q))
2161 bf = list_entry(bf_held->list.next, struct ath_buf,
2165 lastbf = bf->bf_lastbf;
2166 ds = lastbf->bf_desc;
2168 memset(&ts, 0, sizeof(ts));
2169 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2170 if (status == -EINPROGRESS)
2173 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2176 * Remove ath_buf's of the same transmit unit from txq,
2177 * however leave the last descriptor back as the holding
2178 * descriptor for hw.
2180 lastbf->bf_stale = true;
2181 INIT_LIST_HEAD(&bf_head);
2182 if (!list_is_singular(&lastbf->list))
2183 list_cut_position(&bf_head,
2184 &txq->axq_q, lastbf->list.prev);
2187 list_del(&bf_held->list);
2188 ath_tx_return_buffer(sc, bf_held);
2191 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2193 spin_unlock_bh(&txq->axq_lock);
2196 static void ath_tx_complete_poll_work(struct work_struct *work)
2198 struct ath_softc *sc = container_of(work, struct ath_softc,
2199 tx_complete_work.work);
2200 struct ath_txq *txq;
2202 bool needreset = false;
2203 #ifdef CONFIG_ATH9K_DEBUGFS
2204 sc->tx_complete_poll_work_seen++;
2207 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2208 if (ATH_TXQ_SETUP(sc, i)) {
2209 txq = &sc->tx.txq[i];
2210 spin_lock_bh(&txq->axq_lock);
2211 if (txq->axq_depth) {
2212 if (txq->axq_tx_inprogress) {
2214 spin_unlock_bh(&txq->axq_lock);
2217 txq->axq_tx_inprogress = true;
2220 spin_unlock_bh(&txq->axq_lock);
2224 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2225 "tx hung, resetting the chip\n");
2226 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2229 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2230 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2235 void ath_tx_tasklet(struct ath_softc *sc)
2238 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2240 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2242 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2243 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2244 ath_tx_processq(sc, &sc->tx.txq[i]);
2248 void ath_tx_edma_tasklet(struct ath_softc *sc)
2250 struct ath_tx_status ts;
2251 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2252 struct ath_hw *ah = sc->sc_ah;
2253 struct ath_txq *txq;
2254 struct ath_buf *bf, *lastbf;
2255 struct list_head bf_head;
2259 if (work_pending(&sc->hw_reset_work))
2262 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2263 if (status == -EINPROGRESS)
2265 if (status == -EIO) {
2266 ath_dbg(common, ATH_DBG_XMIT,
2267 "Error processing tx status\n");
2271 /* Skip beacon completions */
2272 if (ts.qid == sc->beacon.beaconq)
2275 txq = &sc->tx.txq[ts.qid];
2277 spin_lock_bh(&txq->axq_lock);
2279 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2280 spin_unlock_bh(&txq->axq_lock);
2284 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2285 struct ath_buf, list);
2286 lastbf = bf->bf_lastbf;
2288 INIT_LIST_HEAD(&bf_head);
2289 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2292 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2293 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2295 if (!list_empty(&txq->axq_q)) {
2296 struct list_head bf_q;
2298 INIT_LIST_HEAD(&bf_q);
2299 txq->axq_link = NULL;
2300 list_splice_tail_init(&txq->axq_q, &bf_q);
2301 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2305 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2306 spin_unlock_bh(&txq->axq_lock);
2314 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2316 struct ath_descdma *dd = &sc->txsdma;
2317 u8 txs_len = sc->sc_ah->caps.txs_len;
2319 dd->dd_desc_len = size * txs_len;
2320 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2321 &dd->dd_desc_paddr, GFP_KERNEL);
2328 static int ath_tx_edma_init(struct ath_softc *sc)
2332 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2334 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2335 sc->txsdma.dd_desc_paddr,
2336 ATH_TXSTATUS_RING_SIZE);
2341 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2343 struct ath_descdma *dd = &sc->txsdma;
2345 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2349 int ath_tx_init(struct ath_softc *sc, int nbufs)
2351 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2354 spin_lock_init(&sc->tx.txbuflock);
2356 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2360 "Failed to allocate tx descriptors: %d\n", error);
2364 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2365 "beacon", ATH_BCBUF, 1, 1);
2368 "Failed to allocate beacon descriptors: %d\n", error);
2372 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2374 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2375 error = ath_tx_edma_init(sc);
2387 void ath_tx_cleanup(struct ath_softc *sc)
2389 if (sc->beacon.bdma.dd_desc_len != 0)
2390 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2392 if (sc->tx.txdma.dd_desc_len != 0)
2393 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2395 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2396 ath_tx_edma_cleanup(sc);
2399 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2401 struct ath_atx_tid *tid;
2402 struct ath_atx_ac *ac;
2405 for (tidno = 0, tid = &an->tid[tidno];
2406 tidno < WME_NUM_TID;
2410 tid->seq_start = tid->seq_next = 0;
2411 tid->baw_size = WME_MAX_BA;
2412 tid->baw_head = tid->baw_tail = 0;
2414 tid->paused = false;
2415 tid->state &= ~AGGR_CLEANUP;
2416 __skb_queue_head_init(&tid->buf_q);
2417 acno = TID_TO_WME_AC(tidno);
2418 tid->ac = &an->ac[acno];
2419 tid->state &= ~AGGR_ADDBA_COMPLETE;
2420 tid->state &= ~AGGR_ADDBA_PROGRESS;
2423 for (acno = 0, ac = &an->ac[acno];
2424 acno < WME_NUM_AC; acno++, ac++) {
2426 ac->txq = sc->tx.txq_map[acno];
2427 INIT_LIST_HEAD(&ac->tid_q);
2431 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2433 struct ath_atx_ac *ac;
2434 struct ath_atx_tid *tid;
2435 struct ath_txq *txq;
2438 for (tidno = 0, tid = &an->tid[tidno];
2439 tidno < WME_NUM_TID; tidno++, tid++) {
2444 spin_lock_bh(&txq->axq_lock);
2447 list_del(&tid->list);
2452 list_del(&ac->list);
2453 tid->ac->sched = false;
2456 ath_tid_drain(sc, txq, tid);
2457 tid->state &= ~AGGR_ADDBA_COMPLETE;
2458 tid->state &= ~AGGR_CLEANUP;
2460 spin_unlock_bh(&txq->axq_lock);