2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
108 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
125 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
126 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
127 sizeof(tx_info->rate_driver_data));
128 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
131 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
136 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
137 seqno << IEEE80211_SEQ_SEQ_SHIFT);
140 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
143 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
144 ARRAY_SIZE(bf->rates));
147 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
152 q = skb_get_queue_mapping(skb);
153 if (txq == sc->tx.uapsdq)
154 txq = sc->tx.txq_map[q];
156 if (txq != sc->tx.txq_map[q])
159 if (WARN_ON(--txq->pending_frames < 0))
160 txq->pending_frames = 0;
163 txq->pending_frames < sc->tx.txq_max_pending[q]) {
164 ieee80211_wake_queue(sc->hw, q);
165 txq->stopped = false;
169 static struct ath_atx_tid *
170 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
172 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
173 return ATH_AN_2_TID(an, tidno);
176 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
178 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
181 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
185 skb = __skb_dequeue(&tid->retry_q);
187 skb = __skb_dequeue(&tid->buf_q);
193 * ath_tx_tid_change_state:
194 * - clears a-mpdu flag of previous session
195 * - force sequence number allocation to fix next BlockAck Window
198 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
200 struct ath_txq *txq = tid->ac->txq;
201 struct ieee80211_tx_info *tx_info;
202 struct sk_buff *skb, *tskb;
204 struct ath_frame_info *fi;
206 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
207 fi = get_frame_info(skb);
210 tx_info = IEEE80211_SKB_CB(skb);
211 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
216 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
218 __skb_unlink(skb, &tid->buf_q);
219 ath_txq_skb_done(sc, txq, skb);
220 ieee80211_free_txskb(sc->hw, skb);
227 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
229 struct ath_txq *txq = tid->ac->txq;
232 struct list_head bf_head;
233 struct ath_tx_status ts;
234 struct ath_frame_info *fi;
235 bool sendbar = false;
237 INIT_LIST_HEAD(&bf_head);
239 memset(&ts, 0, sizeof(ts));
241 while ((skb = __skb_dequeue(&tid->retry_q))) {
242 fi = get_frame_info(skb);
245 ath_txq_skb_done(sc, txq, skb);
246 ieee80211_free_txskb(sc->hw, skb);
250 if (fi->baw_tracked) {
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
255 list_add_tail(&bf->list, &bf_head);
256 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
260 ath_txq_unlock(sc, txq);
261 ath_send_bar(tid, tid->seq_start);
262 ath_txq_lock(sc, txq);
266 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
271 index = ATH_BA_INDEX(tid->seq_start, seqno);
272 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
274 __clear_bit(cindex, tid->tx_buf);
276 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
277 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
278 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
279 if (tid->bar_index >= 0)
284 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
287 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
288 u16 seqno = bf->bf_state.seqno;
291 index = ATH_BA_INDEX(tid->seq_start, seqno);
292 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
293 __set_bit(cindex, tid->tx_buf);
296 if (index >= ((tid->baw_tail - tid->baw_head) &
297 (ATH_TID_MAX_BUFS - 1))) {
298 tid->baw_tail = cindex;
299 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
303 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
304 struct ath_atx_tid *tid)
309 struct list_head bf_head;
310 struct ath_tx_status ts;
311 struct ath_frame_info *fi;
313 memset(&ts, 0, sizeof(ts));
314 INIT_LIST_HEAD(&bf_head);
316 while ((skb = ath_tid_dequeue(tid))) {
317 fi = get_frame_info(skb);
321 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
325 list_add_tail(&bf->list, &bf_head);
326 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
330 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
331 struct sk_buff *skb, int count)
333 struct ath_frame_info *fi = get_frame_info(skb);
334 struct ath_buf *bf = fi->bf;
335 struct ieee80211_hdr *hdr;
336 int prev = fi->retries;
338 TX_STAT_INC(txq->axq_qnum, a_retries);
339 fi->retries += count;
344 hdr = (struct ieee80211_hdr *)skb->data;
345 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
346 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
347 sizeof(*hdr), DMA_TO_DEVICE);
350 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
352 struct ath_buf *bf = NULL;
354 spin_lock_bh(&sc->tx.txbuflock);
356 if (unlikely(list_empty(&sc->tx.txbuf))) {
357 spin_unlock_bh(&sc->tx.txbuflock);
361 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
364 spin_unlock_bh(&sc->tx.txbuflock);
369 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
371 spin_lock_bh(&sc->tx.txbuflock);
372 list_add_tail(&bf->list, &sc->tx.txbuf);
373 spin_unlock_bh(&sc->tx.txbuflock);
376 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
380 tbf = ath_tx_get_buffer(sc);
384 ATH_TXBUF_RESET(tbf);
386 tbf->bf_mpdu = bf->bf_mpdu;
387 tbf->bf_buf_addr = bf->bf_buf_addr;
388 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
389 tbf->bf_state = bf->bf_state;
390 tbf->bf_state.stale = false;
395 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
396 struct ath_tx_status *ts, int txok,
397 int *nframes, int *nbad)
399 struct ath_frame_info *fi;
401 u32 ba[WME_BA_BMP_SIZE >> 5];
408 isaggr = bf_isaggr(bf);
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
415 fi = get_frame_info(bf->bf_mpdu);
416 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
419 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
427 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
428 struct ath_buf *bf, struct list_head *bf_q,
429 struct ath_tx_status *ts, int txok)
431 struct ath_node *an = NULL;
433 struct ieee80211_sta *sta;
434 struct ieee80211_hw *hw = sc->hw;
435 struct ieee80211_hdr *hdr;
436 struct ieee80211_tx_info *tx_info;
437 struct ath_atx_tid *tid = NULL;
438 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
439 struct list_head bf_head;
440 struct sk_buff_head bf_pending;
441 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
442 u32 ba[WME_BA_BMP_SIZE >> 5];
443 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
444 bool rc_update = true, isba;
445 struct ieee80211_tx_rate rates[4];
446 struct ath_frame_info *fi;
448 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
453 hdr = (struct ieee80211_hdr *)skb->data;
455 tx_info = IEEE80211_SKB_CB(skb);
457 memcpy(rates, bf->rates, sizeof(rates));
459 retries = ts->ts_longretry + 1;
460 for (i = 0; i < ts->ts_rateindex; i++)
461 retries += rates[i].count;
465 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
469 INIT_LIST_HEAD(&bf_head);
471 bf_next = bf->bf_next;
473 if (!bf->bf_state.stale || bf_next != NULL)
474 list_move_tail(&bf->list, &bf_head);
476 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
483 an = (struct ath_node *)sta->drv_priv;
484 tid = ath_get_skb_tid(sc, an, skb);
485 seq_first = tid->seq_start;
486 isba = ts->ts_flags & ATH9K_TX_BA;
489 * The hardware occasionally sends a tx status for the wrong TID.
490 * In this case, the BA status cannot be considered valid and all
491 * subframes need to be retransmitted
493 * Only BlockAcks have a TID and therefore normal Acks cannot be
496 if (isba && tid->tidno != ts->tid)
499 isaggr = bf_isaggr(bf);
500 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
502 if (isaggr && txok) {
503 if (ts->ts_flags & ATH9K_TX_BA) {
504 seq_st = ts->ts_seqnum;
505 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
508 * AR5416 can become deaf/mute when BA
509 * issue happens. Chip needs to be reset.
510 * But AP code may have sychronization issues
511 * when perform internal reset in this routine.
512 * Only enable reset in STA mode for now.
514 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
519 __skb_queue_head_init(&bf_pending);
521 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
523 u16 seqno = bf->bf_state.seqno;
525 txfail = txpending = sendbar = 0;
526 bf_next = bf->bf_next;
529 tx_info = IEEE80211_SKB_CB(skb);
530 fi = get_frame_info(skb);
532 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
535 * Outside of the current BlockAck window,
536 * maybe part of a previous session
539 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
540 /* transmit completion, subframe is
541 * acked by block ack */
543 } else if (!isaggr && txok) {
544 /* transmit completion */
548 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
549 if (txok || !an->sleeping)
550 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
557 bar_index = max_t(int, bar_index,
558 ATH_BA_INDEX(seq_first, seqno));
562 * Make sure the last desc is reclaimed if it
563 * not a holding desc.
565 INIT_LIST_HEAD(&bf_head);
566 if (bf_next != NULL || !bf_last->bf_state.stale)
567 list_move_tail(&bf->list, &bf_head);
571 * complete the acked-ones/xretried ones; update
574 ath_tx_update_baw(sc, tid, seqno);
576 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
577 memcpy(tx_info->control.rates, rates, sizeof(rates));
578 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
582 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
585 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
586 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
587 ieee80211_sta_eosp(sta);
589 /* retry the un-acked ones */
590 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
593 tbf = ath_clone_txbuf(sc, bf_last);
595 * Update tx baw and complete the
596 * frame with failed status if we
600 ath_tx_update_baw(sc, tid, seqno);
602 ath_tx_complete_buf(sc, bf, txq,
604 bar_index = max_t(int, bar_index,
605 ATH_BA_INDEX(seq_first, seqno));
613 * Put this buffer to the temporary pending
614 * queue to retain ordering
616 __skb_queue_tail(&bf_pending, skb);
622 /* prepend un-acked frames to the beginning of the pending frame queue */
623 if (!skb_queue_empty(&bf_pending)) {
625 ieee80211_sta_set_buffered(sta, tid->tidno, true);
627 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
629 ath_tx_queue_tid(txq, tid);
631 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
632 tid->ac->clear_ps_filter = true;
636 if (bar_index >= 0) {
637 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
639 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
640 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
642 ath_txq_unlock(sc, txq);
643 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
644 ath_txq_lock(sc, txq);
650 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
653 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
655 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
656 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
659 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
660 struct ath_tx_status *ts, struct ath_buf *bf,
661 struct list_head *bf_head)
663 struct ieee80211_tx_info *info;
666 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
667 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
668 txq->axq_tx_inprogress = false;
671 if (bf_is_ampdu_not_probing(bf))
672 txq->axq_ampdu_depth--;
674 if (!bf_isampdu(bf)) {
676 info = IEEE80211_SKB_CB(bf->bf_mpdu);
677 memcpy(info->control.rates, bf->rates,
678 sizeof(info->control.rates));
679 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
681 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
683 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
686 ath_txq_schedule(sc, txq);
689 static bool ath_lookup_legacy(struct ath_buf *bf)
692 struct ieee80211_tx_info *tx_info;
693 struct ieee80211_tx_rate *rates;
697 tx_info = IEEE80211_SKB_CB(skb);
698 rates = tx_info->control.rates;
700 for (i = 0; i < 4; i++) {
701 if (!rates[i].count || rates[i].idx < 0)
704 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
711 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
712 struct ath_atx_tid *tid)
715 struct ieee80211_tx_info *tx_info;
716 struct ieee80211_tx_rate *rates;
717 u32 max_4ms_framelen, frmlen;
718 u16 aggr_limit, bt_aggr_limit, legacy = 0;
719 int q = tid->ac->txq->mac80211_qnum;
723 tx_info = IEEE80211_SKB_CB(skb);
727 * Find the lowest frame length among the rate series that will have a
728 * 4ms (or TXOP limited) transmit duration.
730 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
732 for (i = 0; i < 4; i++) {
738 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
743 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
748 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
751 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
752 max_4ms_framelen = min(max_4ms_framelen, frmlen);
756 * limit aggregate size by the minimum rate if rate selected is
757 * not a probe rate, if rate selected is a probe rate then
758 * avoid aggregation of this packet.
760 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
763 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
766 * Override the default aggregation limit for BTCOEX.
768 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
770 aggr_limit = bt_aggr_limit;
772 if (tid->an->maxampdu)
773 aggr_limit = min(aggr_limit, tid->an->maxampdu);
779 * Returns the number of delimiters to be added to
780 * meet the minimum required mpdudensity.
782 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
783 struct ath_buf *bf, u16 frmlen,
786 #define FIRST_DESC_NDELIMS 60
787 u32 nsymbits, nsymbols;
790 int width, streams, half_gi, ndelim, mindelim;
791 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
793 /* Select standard number of delimiters based on frame length alone */
794 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
797 * If encryption enabled, hardware requires some more padding between
799 * TODO - this could be improved to be dependent on the rate.
800 * The hardware can keep up at lower rates, but not higher rates
802 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
803 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
804 ndelim += ATH_AGGR_ENCRYPTDELIM;
807 * Add delimiter when using RTS/CTS with aggregation
808 * and non enterprise AR9003 card
810 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
811 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
812 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
815 * Convert desired mpdu density from microeconds to bytes based
816 * on highest rate in rate series (i.e. first rate) to determine
817 * required minimum length for subframe. Take into account
818 * whether high rate is 20 or 40Mhz and half or full GI.
820 * If there is no mpdu density restriction, no further calculation
824 if (tid->an->mpdudensity == 0)
827 rix = bf->rates[0].idx;
828 flags = bf->rates[0].flags;
829 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
830 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
833 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
835 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
840 streams = HT_RC_2_STREAMS(rix);
841 nsymbits = bits_per_symbol[rix % 8][width] * streams;
842 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
844 if (frmlen < minlen) {
845 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
846 ndelim = max(mindelim, ndelim);
852 static struct ath_buf *
853 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
854 struct ath_atx_tid *tid, struct sk_buff_head **q)
856 struct ieee80211_tx_info *tx_info;
857 struct ath_frame_info *fi;
864 if (skb_queue_empty(*q))
871 fi = get_frame_info(skb);
874 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
876 bf->bf_state.stale = false;
879 __skb_unlink(skb, *q);
880 ath_txq_skb_done(sc, txq, skb);
881 ieee80211_free_txskb(sc->hw, skb);
888 tx_info = IEEE80211_SKB_CB(skb);
889 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
890 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
891 bf->bf_state.bf_type = 0;
895 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
896 seqno = bf->bf_state.seqno;
898 /* do not step over block-ack window */
899 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
902 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
903 struct ath_tx_status ts = {};
904 struct list_head bf_head;
906 INIT_LIST_HEAD(&bf_head);
907 list_add(&bf->list, &bf_head);
908 __skb_unlink(skb, *q);
909 ath_tx_update_baw(sc, tid, seqno);
910 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
921 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
922 struct ath_atx_tid *tid, struct list_head *bf_q,
923 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
926 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
927 struct ath_buf *bf = bf_first, *bf_prev = NULL;
928 int nframes = 0, ndelim;
929 u16 aggr_limit = 0, al = 0, bpad = 0,
930 al_delta, h_baw = tid->baw_size / 2;
931 struct ieee80211_tx_info *tx_info;
932 struct ath_frame_info *fi;
937 aggr_limit = ath_lookup_rate(sc, bf, tid);
941 fi = get_frame_info(skb);
943 /* do not exceed aggregation limit */
944 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
946 if (aggr_limit < al + bpad + al_delta ||
947 ath_lookup_legacy(bf) || nframes >= h_baw)
950 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
951 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
952 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
956 /* add padding for previous frame to aggregation length */
957 al += bpad + al_delta;
960 * Get the delimiters needed to meet the MPDU
961 * density for this node.
963 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
965 bpad = PADBYTES(al_delta) + (ndelim << 2);
970 /* link buffers of this frame to the aggregate */
971 if (!fi->baw_tracked)
972 ath_tx_addto_baw(sc, tid, bf);
973 bf->bf_state.ndelim = ndelim;
975 __skb_unlink(skb, tid_q);
976 list_add_tail(&bf->list, bf_q);
978 bf_prev->bf_next = bf;
982 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
987 } while (ath_tid_has_buffered(tid));
990 bf->bf_lastbf = bf_prev;
993 al = get_frame_info(bf->bf_mpdu)->framelen;
994 bf->bf_state.bf_type = BUF_AMPDU;
996 TX_STAT_INC(txq->axq_qnum, a_aggr);
1007 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1008 * width - 0 for 20 MHz, 1 for 40 MHz
1009 * half_gi - to use 4us v/s 3.6 us for symbol time
1011 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1012 int width, int half_gi, bool shortPreamble)
1014 u32 nbits, nsymbits, duration, nsymbols;
1017 /* find number of symbols: PLCP + data */
1018 streams = HT_RC_2_STREAMS(rix);
1019 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1020 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1021 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1024 duration = SYMBOL_TIME(nsymbols);
1026 duration = SYMBOL_TIME_HALFGI(nsymbols);
1028 /* addup duration for legacy/ht training and signal fields */
1029 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1034 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1036 int streams = HT_RC_2_STREAMS(mcs);
1040 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1041 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1042 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1043 bits -= OFDM_PLCP_BITS;
1051 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1053 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1056 /* 4ms is the default (and maximum) duration */
1057 if (!txop || txop > 4096)
1060 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1061 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1062 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1063 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1064 for (mcs = 0; mcs < 32; mcs++) {
1065 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1066 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1067 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1068 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1072 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1073 struct ath_tx_info *info, int len, bool rts)
1075 struct ath_hw *ah = sc->sc_ah;
1076 struct ath_common *common = ath9k_hw_common(ah);
1077 struct sk_buff *skb;
1078 struct ieee80211_tx_info *tx_info;
1079 struct ieee80211_tx_rate *rates;
1080 const struct ieee80211_rate *rate;
1081 struct ieee80211_hdr *hdr;
1082 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1083 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1088 tx_info = IEEE80211_SKB_CB(skb);
1090 hdr = (struct ieee80211_hdr *)skb->data;
1092 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1093 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1094 info->rtscts_rate = fi->rtscts_rate;
1096 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1097 bool is_40, is_sgi, is_sp;
1100 if (!rates[i].count || (rates[i].idx < 0))
1104 info->rates[i].Tries = rates[i].count;
1107 * Handle RTS threshold for unaggregated HT frames.
1109 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1110 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1111 unlikely(rts_thresh != (u32) -1)) {
1112 if (!rts_thresh || (len > rts_thresh))
1116 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1117 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1118 info->flags |= ATH9K_TXDESC_RTSENA;
1119 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1120 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1121 info->flags |= ATH9K_TXDESC_CTSENA;
1124 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1125 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1126 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1127 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1129 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1130 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1131 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1133 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1135 info->rates[i].Rate = rix | 0x80;
1136 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1137 ah->txchainmask, info->rates[i].Rate);
1138 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1139 is_40, is_sgi, is_sp);
1140 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1141 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1146 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1147 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1148 !(rate->flags & IEEE80211_RATE_ERP_G))
1149 phy = WLAN_RC_PHY_CCK;
1151 phy = WLAN_RC_PHY_OFDM;
1153 info->rates[i].Rate = rate->hw_value;
1154 if (rate->hw_value_short) {
1155 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1156 info->rates[i].Rate |= rate->hw_value_short;
1161 if (bf->bf_state.bfs_paprd)
1162 info->rates[i].ChSel = ah->txchainmask;
1164 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1165 ah->txchainmask, info->rates[i].Rate);
1167 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1168 phy, rate->bitrate * 100, len, rix, is_sp);
1171 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1172 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1173 info->flags &= ~ATH9K_TXDESC_RTSENA;
1175 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1176 if (info->flags & ATH9K_TXDESC_RTSENA)
1177 info->flags &= ~ATH9K_TXDESC_CTSENA;
1180 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1182 struct ieee80211_hdr *hdr;
1183 enum ath9k_pkt_type htype;
1186 hdr = (struct ieee80211_hdr *)skb->data;
1187 fc = hdr->frame_control;
1189 if (ieee80211_is_beacon(fc))
1190 htype = ATH9K_PKT_TYPE_BEACON;
1191 else if (ieee80211_is_probe_resp(fc))
1192 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1193 else if (ieee80211_is_atim(fc))
1194 htype = ATH9K_PKT_TYPE_ATIM;
1195 else if (ieee80211_is_pspoll(fc))
1196 htype = ATH9K_PKT_TYPE_PSPOLL;
1198 htype = ATH9K_PKT_TYPE_NORMAL;
1203 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1204 struct ath_txq *txq, int len)
1206 struct ath_hw *ah = sc->sc_ah;
1207 struct ath_buf *bf_first = NULL;
1208 struct ath_tx_info info;
1209 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1212 memset(&info, 0, sizeof(info));
1213 info.is_first = true;
1214 info.is_last = true;
1215 info.txpower = MAX_RATE_POWER;
1216 info.qcu = txq->axq_qnum;
1219 struct sk_buff *skb = bf->bf_mpdu;
1220 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1221 struct ath_frame_info *fi = get_frame_info(skb);
1222 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1224 info.type = get_hw_packet_type(skb);
1226 info.link = bf->bf_next->bf_daddr;
1228 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1233 if (!sc->tx99_state)
1234 info.flags = ATH9K_TXDESC_INTREQ;
1235 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1236 txq == sc->tx.uapsdq)
1237 info.flags |= ATH9K_TXDESC_CLRDMASK;
1239 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1240 info.flags |= ATH9K_TXDESC_NOACK;
1241 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1242 info.flags |= ATH9K_TXDESC_LDPC;
1244 if (bf->bf_state.bfs_paprd)
1245 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1246 ATH9K_TXDESC_PAPRD_S;
1249 * mac80211 doesn't handle RTS threshold for HT because
1250 * the decision has to be taken based on AMPDU length
1251 * and aggregation is done entirely inside ath9k.
1252 * Set the RTS/CTS flag for the first subframe based
1255 if (aggr && (bf == bf_first) &&
1256 unlikely(rts_thresh != (u32) -1)) {
1258 * "len" is the size of the entire AMPDU.
1260 if (!rts_thresh || (len > rts_thresh))
1267 ath_buf_set_rate(sc, bf, &info, len, rts);
1270 info.buf_addr[0] = bf->bf_buf_addr;
1271 info.buf_len[0] = skb->len;
1272 info.pkt_len = fi->framelen;
1273 info.keyix = fi->keyix;
1274 info.keytype = fi->keytype;
1278 info.aggr = AGGR_BUF_FIRST;
1279 else if (bf == bf_first->bf_lastbf)
1280 info.aggr = AGGR_BUF_LAST;
1282 info.aggr = AGGR_BUF_MIDDLE;
1284 info.ndelim = bf->bf_state.ndelim;
1285 info.aggr_len = len;
1288 if (bf == bf_first->bf_lastbf)
1291 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1297 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1298 struct ath_atx_tid *tid, struct list_head *bf_q,
1299 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1301 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1302 struct sk_buff *skb;
1306 struct ieee80211_tx_info *tx_info;
1310 __skb_unlink(skb, tid_q);
1311 list_add_tail(&bf->list, bf_q);
1313 bf_prev->bf_next = bf;
1319 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1323 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1324 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1327 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1331 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1332 struct ath_atx_tid *tid, bool *stop)
1335 struct ieee80211_tx_info *tx_info;
1336 struct sk_buff_head *tid_q;
1337 struct list_head bf_q;
1339 bool aggr, last = true;
1341 if (!ath_tid_has_buffered(tid))
1344 INIT_LIST_HEAD(&bf_q);
1346 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1350 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1351 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1352 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1353 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1358 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1360 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1363 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1365 if (list_empty(&bf_q))
1368 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1369 tid->ac->clear_ps_filter = false;
1370 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1373 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1374 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1378 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1381 struct ath_atx_tid *txtid;
1382 struct ath_txq *txq;
1383 struct ath_node *an;
1386 an = (struct ath_node *)sta->drv_priv;
1387 txtid = ATH_AN_2_TID(an, tid);
1388 txq = txtid->ac->txq;
1390 ath_txq_lock(sc, txq);
1392 /* update ampdu factor/density, they may have changed. This may happen
1393 * in HT IBSS when a beacon with HT-info is received after the station
1394 * has already been added.
1396 if (sta->ht_cap.ht_supported) {
1397 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1398 sta->ht_cap.ampdu_factor)) - 1;
1399 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1400 an->mpdudensity = density;
1403 /* force sequence number allocation for pending frames */
1404 ath_tx_tid_change_state(sc, txtid);
1406 txtid->active = true;
1407 *ssn = txtid->seq_start = txtid->seq_next;
1408 txtid->bar_index = -1;
1410 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1411 txtid->baw_head = txtid->baw_tail = 0;
1413 ath_txq_unlock_complete(sc, txq);
1418 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1420 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1421 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1422 struct ath_txq *txq = txtid->ac->txq;
1424 ath_txq_lock(sc, txq);
1425 txtid->active = false;
1426 ath_tx_flush_tid(sc, txtid);
1427 ath_tx_tid_change_state(sc, txtid);
1428 ath_txq_unlock_complete(sc, txq);
1431 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1432 struct ath_node *an)
1434 struct ath_atx_tid *tid;
1435 struct ath_atx_ac *ac;
1436 struct ath_txq *txq;
1440 for (tidno = 0, tid = &an->tid[tidno];
1441 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1446 ath_txq_lock(sc, txq);
1449 ath_txq_unlock(sc, txq);
1453 buffered = ath_tid_has_buffered(tid);
1456 list_del(&tid->list);
1460 list_del(&ac->list);
1463 ath_txq_unlock(sc, txq);
1465 ieee80211_sta_set_buffered(sta, tidno, buffered);
1469 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1471 struct ath_atx_tid *tid;
1472 struct ath_atx_ac *ac;
1473 struct ath_txq *txq;
1476 for (tidno = 0, tid = &an->tid[tidno];
1477 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1482 ath_txq_lock(sc, txq);
1483 ac->clear_ps_filter = true;
1485 if (ath_tid_has_buffered(tid)) {
1486 ath_tx_queue_tid(txq, tid);
1487 ath_txq_schedule(sc, txq);
1490 ath_txq_unlock_complete(sc, txq);
1494 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1497 struct ath_atx_tid *tid;
1498 struct ath_node *an;
1499 struct ath_txq *txq;
1501 an = (struct ath_node *)sta->drv_priv;
1502 tid = ATH_AN_2_TID(an, tidno);
1505 ath_txq_lock(sc, txq);
1507 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1509 if (ath_tid_has_buffered(tid)) {
1510 ath_tx_queue_tid(txq, tid);
1511 ath_txq_schedule(sc, txq);
1514 ath_txq_unlock_complete(sc, txq);
1517 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1518 struct ieee80211_sta *sta,
1519 u16 tids, int nframes,
1520 enum ieee80211_frame_release_type reason,
1523 struct ath_softc *sc = hw->priv;
1524 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1525 struct ath_txq *txq = sc->tx.uapsdq;
1526 struct ieee80211_tx_info *info;
1527 struct list_head bf_q;
1528 struct ath_buf *bf_tail = NULL, *bf;
1529 struct sk_buff_head *tid_q;
1533 INIT_LIST_HEAD(&bf_q);
1534 for (i = 0; tids && nframes; i++, tids >>= 1) {
1535 struct ath_atx_tid *tid;
1540 tid = ATH_AN_2_TID(an, i);
1542 ath_txq_lock(sc, tid->ac->txq);
1543 while (nframes > 0) {
1544 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1548 __skb_unlink(bf->bf_mpdu, tid_q);
1549 list_add_tail(&bf->list, &bf_q);
1550 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1551 if (bf_isampdu(bf)) {
1552 ath_tx_addto_baw(sc, tid, bf);
1553 bf->bf_state.bf_type &= ~BUF_AGGR;
1556 bf_tail->bf_next = bf;
1561 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1563 if (an->sta && !ath_tid_has_buffered(tid))
1564 ieee80211_sta_set_buffered(an->sta, i, false);
1566 ath_txq_unlock_complete(sc, tid->ac->txq);
1569 if (list_empty(&bf_q))
1572 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1573 info->flags |= IEEE80211_TX_STATUS_EOSP;
1575 bf = list_first_entry(&bf_q, struct ath_buf, list);
1576 ath_txq_lock(sc, txq);
1577 ath_tx_fill_desc(sc, bf, txq, 0);
1578 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1579 ath_txq_unlock(sc, txq);
1582 /********************/
1583 /* Queue Management */
1584 /********************/
1586 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1588 struct ath_hw *ah = sc->sc_ah;
1589 struct ath9k_tx_queue_info qi;
1590 static const int subtype_txq_to_hwq[] = {
1591 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1592 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1593 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1594 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1598 memset(&qi, 0, sizeof(qi));
1599 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1600 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1601 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1602 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1603 qi.tqi_physCompBuf = 0;
1606 * Enable interrupts only for EOL and DESC conditions.
1607 * We mark tx descriptors to receive a DESC interrupt
1608 * when a tx queue gets deep; otherwise waiting for the
1609 * EOL to reap descriptors. Note that this is done to
1610 * reduce interrupt load and this only defers reaping
1611 * descriptors, never transmitting frames. Aside from
1612 * reducing interrupts this also permits more concurrency.
1613 * The only potential downside is if the tx queue backs
1614 * up in which case the top half of the kernel may backup
1615 * due to a lack of tx descriptors.
1617 * The UAPSD queue is an exception, since we take a desc-
1618 * based intr on the EOSP frames.
1620 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1621 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1623 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1624 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1626 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1627 TXQ_FLAG_TXDESCINT_ENABLE;
1629 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1630 if (axq_qnum == -1) {
1632 * NB: don't print a message, this happens
1633 * normally on parts with too few tx queues
1637 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1638 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1640 txq->axq_qnum = axq_qnum;
1641 txq->mac80211_qnum = -1;
1642 txq->axq_link = NULL;
1643 __skb_queue_head_init(&txq->complete_q);
1644 INIT_LIST_HEAD(&txq->axq_q);
1645 INIT_LIST_HEAD(&txq->axq_acq);
1646 spin_lock_init(&txq->axq_lock);
1648 txq->axq_ampdu_depth = 0;
1649 txq->axq_tx_inprogress = false;
1650 sc->tx.txqsetup |= 1<<axq_qnum;
1652 txq->txq_headidx = txq->txq_tailidx = 0;
1653 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1654 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1656 return &sc->tx.txq[axq_qnum];
1659 int ath_txq_update(struct ath_softc *sc, int qnum,
1660 struct ath9k_tx_queue_info *qinfo)
1662 struct ath_hw *ah = sc->sc_ah;
1664 struct ath9k_tx_queue_info qi;
1666 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1668 ath9k_hw_get_txq_props(ah, qnum, &qi);
1669 qi.tqi_aifs = qinfo->tqi_aifs;
1670 qi.tqi_cwmin = qinfo->tqi_cwmin;
1671 qi.tqi_cwmax = qinfo->tqi_cwmax;
1672 qi.tqi_burstTime = qinfo->tqi_burstTime;
1673 qi.tqi_readyTime = qinfo->tqi_readyTime;
1675 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1676 ath_err(ath9k_hw_common(sc->sc_ah),
1677 "Unable to update hardware queue %u!\n", qnum);
1680 ath9k_hw_resettxqueue(ah, qnum);
1686 int ath_cabq_update(struct ath_softc *sc)
1688 struct ath9k_tx_queue_info qi;
1689 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1690 int qnum = sc->beacon.cabq->axq_qnum;
1692 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1694 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1695 ATH_CABQ_READY_TIME) / 100;
1696 ath_txq_update(sc, qnum, &qi);
1701 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1702 struct list_head *list)
1704 struct ath_buf *bf, *lastbf;
1705 struct list_head bf_head;
1706 struct ath_tx_status ts;
1708 memset(&ts, 0, sizeof(ts));
1709 ts.ts_status = ATH9K_TX_FLUSH;
1710 INIT_LIST_HEAD(&bf_head);
1712 while (!list_empty(list)) {
1713 bf = list_first_entry(list, struct ath_buf, list);
1715 if (bf->bf_state.stale) {
1716 list_del(&bf->list);
1718 ath_tx_return_buffer(sc, bf);
1722 lastbf = bf->bf_lastbf;
1723 list_cut_position(&bf_head, list, &lastbf->list);
1724 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1729 * Drain a given TX queue (could be Beacon or Data)
1731 * This assumes output has been stopped and
1732 * we do not need to block ath_tx_tasklet.
1734 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1736 ath_txq_lock(sc, txq);
1738 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1739 int idx = txq->txq_tailidx;
1741 while (!list_empty(&txq->txq_fifo[idx])) {
1742 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1744 INCR(idx, ATH_TXFIFO_DEPTH);
1746 txq->txq_tailidx = idx;
1749 txq->axq_link = NULL;
1750 txq->axq_tx_inprogress = false;
1751 ath_drain_txq_list(sc, txq, &txq->axq_q);
1753 ath_txq_unlock_complete(sc, txq);
1756 bool ath_drain_all_txq(struct ath_softc *sc)
1758 struct ath_hw *ah = sc->sc_ah;
1759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1760 struct ath_txq *txq;
1764 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1767 ath9k_hw_abort_tx_dma(ah);
1769 /* Check if any queue remains active */
1770 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1771 if (!ATH_TXQ_SETUP(sc, i))
1774 if (!sc->tx.txq[i].axq_depth)
1777 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1782 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1784 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1785 if (!ATH_TXQ_SETUP(sc, i))
1789 * The caller will resume queues with ieee80211_wake_queues.
1790 * Mark the queue as not stopped to prevent ath_tx_complete
1791 * from waking the queue too early.
1793 txq = &sc->tx.txq[i];
1794 txq->stopped = false;
1795 ath_draintxq(sc, txq);
1801 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1803 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1804 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1807 /* For each axq_acq entry, for each tid, try to schedule packets
1808 * for transmit until ampdu_depth has reached min Q depth.
1810 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1812 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1813 struct ath_atx_ac *ac, *last_ac;
1814 struct ath_atx_tid *tid, *last_tid;
1817 if (test_bit(ATH_OP_HW_RESET, &common->op_flags) ||
1818 list_empty(&txq->axq_acq))
1823 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1824 while (!list_empty(&txq->axq_acq)) {
1827 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1828 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1829 list_del(&ac->list);
1832 while (!list_empty(&ac->tid_q)) {
1834 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1836 list_del(&tid->list);
1839 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1843 * add tid to round-robin queue if more frames
1844 * are pending for the tid
1846 if (ath_tid_has_buffered(tid))
1847 ath_tx_queue_tid(txq, tid);
1849 if (stop || tid == last_tid)
1853 if (!list_empty(&ac->tid_q) && !ac->sched) {
1855 list_add_tail(&ac->list, &txq->axq_acq);
1861 if (ac == last_ac) {
1866 last_ac = list_entry(txq->axq_acq.prev,
1867 struct ath_atx_ac, list);
1879 * Insert a chain of ath_buf (descriptors) on a txq and
1880 * assume the descriptors are already chained together by caller.
1882 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1883 struct list_head *head, bool internal)
1885 struct ath_hw *ah = sc->sc_ah;
1886 struct ath_common *common = ath9k_hw_common(ah);
1887 struct ath_buf *bf, *bf_last;
1888 bool puttxbuf = false;
1892 * Insert the frame on the outbound list and
1893 * pass it on to the hardware.
1896 if (list_empty(head))
1899 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1900 bf = list_first_entry(head, struct ath_buf, list);
1901 bf_last = list_entry(head->prev, struct ath_buf, list);
1903 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1904 txq->axq_qnum, txq->axq_depth);
1906 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1907 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1908 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1911 list_splice_tail_init(head, &txq->axq_q);
1913 if (txq->axq_link) {
1914 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1915 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1916 txq->axq_qnum, txq->axq_link,
1917 ito64(bf->bf_daddr), bf->bf_desc);
1921 txq->axq_link = bf_last->bf_desc;
1925 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1926 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1927 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1928 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1931 if (!edma || sc->tx99_state) {
1932 TX_STAT_INC(txq->axq_qnum, txstart);
1933 ath9k_hw_txstart(ah, txq->axq_qnum);
1939 if (bf_is_ampdu_not_probing(bf))
1940 txq->axq_ampdu_depth++;
1942 bf_last = bf->bf_lastbf;
1943 bf = bf_last->bf_next;
1944 bf_last->bf_next = NULL;
1949 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1950 struct ath_atx_tid *tid, struct sk_buff *skb)
1952 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1953 struct ath_frame_info *fi = get_frame_info(skb);
1954 struct list_head bf_head;
1955 struct ath_buf *bf = fi->bf;
1957 INIT_LIST_HEAD(&bf_head);
1958 list_add_tail(&bf->list, &bf_head);
1959 bf->bf_state.bf_type = 0;
1960 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1961 bf->bf_state.bf_type = BUF_AMPDU;
1962 ath_tx_addto_baw(sc, tid, bf);
1967 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1968 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1969 TX_STAT_INC(txq->axq_qnum, queued);
1972 static void setup_frame_info(struct ieee80211_hw *hw,
1973 struct ieee80211_sta *sta,
1974 struct sk_buff *skb,
1977 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1978 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1979 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1980 const struct ieee80211_rate *rate;
1981 struct ath_frame_info *fi = get_frame_info(skb);
1982 struct ath_node *an = NULL;
1983 enum ath9k_key_type keytype;
1984 bool short_preamble = false;
1987 * We check if Short Preamble is needed for the CTS rate by
1988 * checking the BSS's global flag.
1989 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1991 if (tx_info->control.vif &&
1992 tx_info->control.vif->bss_conf.use_short_preamble)
1993 short_preamble = true;
1995 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1996 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1999 an = (struct ath_node *) sta->drv_priv;
2001 memset(fi, 0, sizeof(*fi));
2003 fi->keyix = hw_key->hw_key_idx;
2004 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2005 fi->keyix = an->ps_key;
2007 fi->keyix = ATH9K_TXKEYIX_INVALID;
2008 fi->keytype = keytype;
2009 fi->framelen = framelen;
2013 fi->rtscts_rate = rate->hw_value;
2015 fi->rtscts_rate |= rate->hw_value_short;
2018 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2020 struct ath_hw *ah = sc->sc_ah;
2021 struct ath9k_channel *curchan = ah->curchan;
2023 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2024 (chainmask == 0x7) && (rate < 0x90))
2026 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2034 * Assign a descriptor (and sequence number if necessary,
2035 * and map buffer for DMA. Frees skb on error
2037 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2038 struct ath_txq *txq,
2039 struct ath_atx_tid *tid,
2040 struct sk_buff *skb)
2042 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2043 struct ath_frame_info *fi = get_frame_info(skb);
2044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2049 bf = ath_tx_get_buffer(sc);
2051 ath_dbg(common, XMIT, "TX buffers are full\n");
2055 ATH_TXBUF_RESET(bf);
2057 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2058 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2059 seqno = tid->seq_next;
2060 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2063 hdr->seq_ctrl |= cpu_to_le16(fragno);
2065 if (!ieee80211_has_morefrags(hdr->frame_control))
2066 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2068 bf->bf_state.seqno = seqno;
2073 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2074 skb->len, DMA_TO_DEVICE);
2075 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2077 bf->bf_buf_addr = 0;
2078 ath_err(ath9k_hw_common(sc->sc_ah),
2079 "dma_mapping_error() on TX\n");
2080 ath_tx_return_buffer(sc, bf);
2089 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2090 struct ath_tx_control *txctl)
2092 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2093 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2094 struct ieee80211_sta *sta = txctl->sta;
2095 struct ieee80211_vif *vif = info->control.vif;
2096 struct ath_vif *avp;
2097 struct ath_softc *sc = hw->priv;
2098 int frmlen = skb->len + FCS_LEN;
2099 int padpos, padsize;
2101 /* NOTE: sta can be NULL according to net/mac80211.h */
2103 txctl->an = (struct ath_node *)sta->drv_priv;
2104 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2105 avp = (void *)vif->drv_priv;
2106 txctl->an = &avp->mcast_node;
2109 if (info->control.hw_key)
2110 frmlen += info->control.hw_key->icv_len;
2113 * As a temporary workaround, assign seq# here; this will likely need
2114 * to be cleaned up to work better with Beacon transmission and virtual
2117 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2118 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2119 sc->tx.seq_no += 0x10;
2120 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2121 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2124 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2125 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2126 !ieee80211_is_data(hdr->frame_control))
2127 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2129 /* Add the padding after the header if this is not already done */
2130 padpos = ieee80211_hdrlen(hdr->frame_control);
2131 padsize = padpos & 3;
2132 if (padsize && skb->len > padpos) {
2133 if (skb_headroom(skb) < padsize)
2136 skb_push(skb, padsize);
2137 memmove(skb->data, skb->data + padsize, padpos);
2140 setup_frame_info(hw, sta, skb, frmlen);
2145 /* Upon failure caller should free skb */
2146 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2147 struct ath_tx_control *txctl)
2149 struct ieee80211_hdr *hdr;
2150 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2151 struct ieee80211_sta *sta = txctl->sta;
2152 struct ieee80211_vif *vif = info->control.vif;
2153 struct ath_softc *sc = hw->priv;
2154 struct ath_txq *txq = txctl->txq;
2155 struct ath_atx_tid *tid = NULL;
2160 ret = ath_tx_prepare(hw, skb, txctl);
2164 hdr = (struct ieee80211_hdr *) skb->data;
2166 * At this point, the vif, hw_key and sta pointers in the tx control
2167 * info are no longer valid (overwritten by the ath_frame_info data.
2170 q = skb_get_queue_mapping(skb);
2172 ath_txq_lock(sc, txq);
2173 if (txq == sc->tx.txq_map[q] &&
2174 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2176 ieee80211_stop_queue(sc->hw, q);
2177 txq->stopped = true;
2180 if (txctl->an && ieee80211_is_data_present(hdr->frame_control))
2181 tid = ath_get_skb_tid(sc, txctl->an, skb);
2183 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2184 ath_txq_unlock(sc, txq);
2185 txq = sc->tx.uapsdq;
2186 ath_txq_lock(sc, txq);
2187 } else if (txctl->an &&
2188 ieee80211_is_data_present(hdr->frame_control)) {
2189 WARN_ON(tid->ac->txq != txctl->txq);
2191 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2192 tid->ac->clear_ps_filter = true;
2195 * Add this frame to software queue for scheduling later
2198 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2199 __skb_queue_tail(&tid->buf_q, skb);
2200 if (!txctl->an->sleeping)
2201 ath_tx_queue_tid(txq, tid);
2203 ath_txq_schedule(sc, txq);
2207 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2209 ath_txq_skb_done(sc, txq, skb);
2211 dev_kfree_skb_any(skb);
2213 ieee80211_free_txskb(sc->hw, skb);
2217 bf->bf_state.bfs_paprd = txctl->paprd;
2220 bf->bf_state.bfs_paprd_timestamp = jiffies;
2222 ath_set_rates(vif, sta, bf);
2223 ath_tx_send_normal(sc, txq, tid, skb);
2226 ath_txq_unlock(sc, txq);
2231 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2232 struct sk_buff *skb)
2234 struct ath_softc *sc = hw->priv;
2235 struct ath_tx_control txctl = {
2236 .txq = sc->beacon.cabq
2238 struct ath_tx_info info = {};
2239 struct ieee80211_hdr *hdr;
2240 struct ath_buf *bf_tail = NULL;
2247 sc->cur_beacon_conf.beacon_interval * 1000 *
2248 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2251 struct ath_frame_info *fi = get_frame_info(skb);
2253 if (ath_tx_prepare(hw, skb, &txctl))
2256 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2261 ath_set_rates(vif, NULL, bf);
2262 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2263 duration += info.rates[0].PktDuration;
2265 bf_tail->bf_next = bf;
2267 list_add_tail(&bf->list, &bf_q);
2271 if (duration > max_duration)
2274 skb = ieee80211_get_buffered_bc(hw, vif);
2278 ieee80211_free_txskb(hw, skb);
2280 if (list_empty(&bf_q))
2283 bf = list_first_entry(&bf_q, struct ath_buf, list);
2284 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2286 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2287 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2288 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2289 sizeof(*hdr), DMA_TO_DEVICE);
2292 ath_txq_lock(sc, txctl.txq);
2293 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2294 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2295 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2296 ath_txq_unlock(sc, txctl.txq);
2303 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2304 int tx_flags, struct ath_txq *txq)
2306 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2307 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2308 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2309 int padpos, padsize;
2310 unsigned long flags;
2312 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2314 if (sc->sc_ah->caldata)
2315 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2317 if (!(tx_flags & ATH_TX_ERROR))
2318 /* Frame was ACKed */
2319 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2321 padpos = ieee80211_hdrlen(hdr->frame_control);
2322 padsize = padpos & 3;
2323 if (padsize && skb->len>padpos+padsize) {
2325 * Remove MAC header padding before giving the frame back to
2328 memmove(skb->data + padsize, skb->data, padpos);
2329 skb_pull(skb, padsize);
2332 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2333 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2334 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2336 "Going back to sleep after having received TX status (0x%lx)\n",
2337 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2339 PS_WAIT_FOR_PSPOLL_DATA |
2340 PS_WAIT_FOR_TX_ACK));
2342 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2344 __skb_queue_tail(&txq->complete_q, skb);
2345 ath_txq_skb_done(sc, txq, skb);
2348 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2349 struct ath_txq *txq, struct list_head *bf_q,
2350 struct ath_tx_status *ts, int txok)
2352 struct sk_buff *skb = bf->bf_mpdu;
2353 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2354 unsigned long flags;
2358 tx_flags |= ATH_TX_ERROR;
2360 if (ts->ts_status & ATH9K_TXERR_FILT)
2361 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2363 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2364 bf->bf_buf_addr = 0;
2366 goto skip_tx_complete;
2368 if (bf->bf_state.bfs_paprd) {
2369 if (time_after(jiffies,
2370 bf->bf_state.bfs_paprd_timestamp +
2371 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2372 dev_kfree_skb_any(skb);
2374 complete(&sc->paprd_complete);
2376 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2377 ath_tx_complete(sc, skb, tx_flags, txq);
2380 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2381 * accidentally reference it later.
2386 * Return the list of ath_buf of this mpdu to free queue
2388 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2389 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2390 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2393 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2394 struct ath_tx_status *ts, int nframes, int nbad,
2397 struct sk_buff *skb = bf->bf_mpdu;
2398 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2399 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2400 struct ieee80211_hw *hw = sc->hw;
2401 struct ath_hw *ah = sc->sc_ah;
2405 tx_info->status.ack_signal = ts->ts_rssi;
2407 tx_rateindex = ts->ts_rateindex;
2408 WARN_ON(tx_rateindex >= hw->max_rates);
2410 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2411 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2413 BUG_ON(nbad > nframes);
2415 tx_info->status.ampdu_len = nframes;
2416 tx_info->status.ampdu_ack_len = nframes - nbad;
2418 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2419 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2421 * If an underrun error is seen assume it as an excessive
2422 * retry only if max frame trigger level has been reached
2423 * (2 KB for single stream, and 4 KB for dual stream).
2424 * Adjust the long retry as if the frame was tried
2425 * hw->max_rate_tries times to affect how rate control updates
2426 * PER for the failed rate.
2427 * In case of congestion on the bus penalizing this type of
2428 * underruns should help hardware actually transmit new frames
2429 * successfully by eventually preferring slower rates.
2430 * This itself should also alleviate congestion on the bus.
2432 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2433 ATH9K_TX_DELIM_UNDERRUN)) &&
2434 ieee80211_is_data(hdr->frame_control) &&
2435 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2436 tx_info->status.rates[tx_rateindex].count =
2440 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2441 tx_info->status.rates[i].count = 0;
2442 tx_info->status.rates[i].idx = -1;
2445 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2448 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2450 struct ath_hw *ah = sc->sc_ah;
2451 struct ath_common *common = ath9k_hw_common(ah);
2452 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2453 struct list_head bf_head;
2454 struct ath_desc *ds;
2455 struct ath_tx_status ts;
2458 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2459 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2462 ath_txq_lock(sc, txq);
2464 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2467 if (list_empty(&txq->axq_q)) {
2468 txq->axq_link = NULL;
2469 ath_txq_schedule(sc, txq);
2472 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2475 * There is a race condition that a BH gets scheduled
2476 * after sw writes TxE and before hw re-load the last
2477 * descriptor to get the newly chained one.
2478 * Software must keep the last DONE descriptor as a
2479 * holding descriptor - software does so by marking
2480 * it with the STALE flag.
2483 if (bf->bf_state.stale) {
2485 if (list_is_last(&bf_held->list, &txq->axq_q))
2488 bf = list_entry(bf_held->list.next, struct ath_buf,
2492 lastbf = bf->bf_lastbf;
2493 ds = lastbf->bf_desc;
2495 memset(&ts, 0, sizeof(ts));
2496 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2497 if (status == -EINPROGRESS)
2500 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2503 * Remove ath_buf's of the same transmit unit from txq,
2504 * however leave the last descriptor back as the holding
2505 * descriptor for hw.
2507 lastbf->bf_state.stale = true;
2508 INIT_LIST_HEAD(&bf_head);
2509 if (!list_is_singular(&lastbf->list))
2510 list_cut_position(&bf_head,
2511 &txq->axq_q, lastbf->list.prev);
2514 list_del(&bf_held->list);
2515 ath_tx_return_buffer(sc, bf_held);
2518 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2520 ath_txq_unlock_complete(sc, txq);
2523 void ath_tx_tasklet(struct ath_softc *sc)
2525 struct ath_hw *ah = sc->sc_ah;
2526 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2529 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2530 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2531 ath_tx_processq(sc, &sc->tx.txq[i]);
2535 void ath_tx_edma_tasklet(struct ath_softc *sc)
2537 struct ath_tx_status ts;
2538 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2539 struct ath_hw *ah = sc->sc_ah;
2540 struct ath_txq *txq;
2541 struct ath_buf *bf, *lastbf;
2542 struct list_head bf_head;
2543 struct list_head *fifo_list;
2547 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2550 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2551 if (status == -EINPROGRESS)
2553 if (status == -EIO) {
2554 ath_dbg(common, XMIT, "Error processing tx status\n");
2558 /* Process beacon completions separately */
2559 if (ts.qid == sc->beacon.beaconq) {
2560 sc->beacon.tx_processed = true;
2561 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2563 ath9k_csa_update(sc);
2567 txq = &sc->tx.txq[ts.qid];
2569 ath_txq_lock(sc, txq);
2571 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2573 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2574 if (list_empty(fifo_list)) {
2575 ath_txq_unlock(sc, txq);
2579 bf = list_first_entry(fifo_list, struct ath_buf, list);
2580 if (bf->bf_state.stale) {
2581 list_del(&bf->list);
2582 ath_tx_return_buffer(sc, bf);
2583 bf = list_first_entry(fifo_list, struct ath_buf, list);
2586 lastbf = bf->bf_lastbf;
2588 INIT_LIST_HEAD(&bf_head);
2589 if (list_is_last(&lastbf->list, fifo_list)) {
2590 list_splice_tail_init(fifo_list, &bf_head);
2591 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2593 if (!list_empty(&txq->axq_q)) {
2594 struct list_head bf_q;
2596 INIT_LIST_HEAD(&bf_q);
2597 txq->axq_link = NULL;
2598 list_splice_tail_init(&txq->axq_q, &bf_q);
2599 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2602 lastbf->bf_state.stale = true;
2604 list_cut_position(&bf_head, fifo_list,
2608 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2609 ath_txq_unlock_complete(sc, txq);
2617 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2619 struct ath_descdma *dd = &sc->txsdma;
2620 u8 txs_len = sc->sc_ah->caps.txs_len;
2622 dd->dd_desc_len = size * txs_len;
2623 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2624 &dd->dd_desc_paddr, GFP_KERNEL);
2631 static int ath_tx_edma_init(struct ath_softc *sc)
2635 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2637 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2638 sc->txsdma.dd_desc_paddr,
2639 ATH_TXSTATUS_RING_SIZE);
2644 int ath_tx_init(struct ath_softc *sc, int nbufs)
2646 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2649 spin_lock_init(&sc->tx.txbuflock);
2651 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2655 "Failed to allocate tx descriptors: %d\n", error);
2659 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2660 "beacon", ATH_BCBUF, 1, 1);
2663 "Failed to allocate beacon descriptors: %d\n", error);
2667 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2669 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2670 error = ath_tx_edma_init(sc);
2675 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2677 struct ath_atx_tid *tid;
2678 struct ath_atx_ac *ac;
2681 for (tidno = 0, tid = &an->tid[tidno];
2682 tidno < IEEE80211_NUM_TIDS;
2686 tid->seq_start = tid->seq_next = 0;
2687 tid->baw_size = WME_MAX_BA;
2688 tid->baw_head = tid->baw_tail = 0;
2690 tid->active = false;
2691 __skb_queue_head_init(&tid->buf_q);
2692 __skb_queue_head_init(&tid->retry_q);
2693 acno = TID_TO_WME_AC(tidno);
2694 tid->ac = &an->ac[acno];
2697 for (acno = 0, ac = &an->ac[acno];
2698 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2700 ac->clear_ps_filter = true;
2701 ac->txq = sc->tx.txq_map[acno];
2702 INIT_LIST_HEAD(&ac->tid_q);
2706 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2708 struct ath_atx_ac *ac;
2709 struct ath_atx_tid *tid;
2710 struct ath_txq *txq;
2713 for (tidno = 0, tid = &an->tid[tidno];
2714 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2719 ath_txq_lock(sc, txq);
2722 list_del(&tid->list);
2727 list_del(&ac->list);
2728 tid->ac->sched = false;
2731 ath_tid_drain(sc, txq, tid);
2732 tid->active = false;
2734 ath_txq_unlock(sc, txq);
2738 #ifdef CONFIG_ATH9K_TX99
2740 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2741 struct ath_tx_control *txctl)
2743 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2744 struct ath_frame_info *fi = get_frame_info(skb);
2745 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2747 int padpos, padsize;
2749 padpos = ieee80211_hdrlen(hdr->frame_control);
2750 padsize = padpos & 3;
2752 if (padsize && skb->len > padpos) {
2753 if (skb_headroom(skb) < padsize) {
2754 ath_dbg(common, XMIT,
2755 "tx99 padding failed\n");
2759 skb_push(skb, padsize);
2760 memmove(skb->data, skb->data + padsize, padpos);
2763 fi->keyix = ATH9K_TXKEYIX_INVALID;
2764 fi->framelen = skb->len + FCS_LEN;
2765 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2767 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2769 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2773 ath_set_rates(sc->tx99_vif, NULL, bf);
2775 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2776 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2778 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2783 #endif /* CONFIG_ATH9K_TX99 */