2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
161 if (txq != sc->tx.txq_map[q])
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
177 struct ieee80211_hdr *hdr;
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
197 skb = __skb_dequeue(&tid->retry_q);
199 skb = __skb_dequeue(&tid->buf_q);
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
216 struct ath_frame_info *fi;
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
241 struct ath_txq *txq = tid->ac->txq;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
249 INIT_LIST_HEAD(&bf_head);
251 memset(&ts, 0, sizeof(ts));
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
286 __clear_bit(cindex, tid->tx_buf);
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
315 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
321 struct list_head bf_head;
322 struct ath_tx_status ts;
323 struct ath_frame_info *fi;
325 memset(&ts, 0, sizeof(ts));
326 INIT_LIST_HEAD(&bf_head);
328 while ((skb = ath_tid_dequeue(tid))) {
329 fi = get_frame_info(skb);
333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
337 list_add_tail(&bf->list, &bf_head);
338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
342 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
343 struct sk_buff *skb, int count)
345 struct ath_frame_info *fi = get_frame_info(skb);
346 struct ath_buf *bf = fi->bf;
347 struct ieee80211_hdr *hdr;
348 int prev = fi->retries;
350 TX_STAT_INC(txq->axq_qnum, a_retries);
351 fi->retries += count;
356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
362 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
364 struct ath_buf *bf = NULL;
366 spin_lock_bh(&sc->tx.txbuflock);
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
369 spin_unlock_bh(&sc->tx.txbuflock);
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
376 spin_unlock_bh(&sc->tx.txbuflock);
381 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
388 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
392 tbf = ath_tx_get_buffer(sc);
396 ATH_TXBUF_RESET(tbf);
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
401 tbf->bf_state = bf->bf_state;
406 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
407 struct ath_tx_status *ts, int txok,
408 int *nframes, int *nbad)
410 struct ath_frame_info *fi;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
419 isaggr = bf_isaggr(bf);
421 seq_st = ts->ts_seqnum;
422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
426 fi = get_frame_info(bf->bf_mpdu);
427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
438 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
439 struct ath_buf *bf, struct list_head *bf_q,
440 struct ath_tx_status *ts, int txok)
442 struct ath_node *an = NULL;
444 struct ieee80211_sta *sta;
445 struct ieee80211_hw *hw = sc->hw;
446 struct ieee80211_hdr *hdr;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_atx_tid *tid = NULL;
449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
450 struct list_head bf_head;
451 struct sk_buff_head bf_pending;
452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
453 u32 ba[WME_BA_BMP_SIZE >> 5];
454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
455 bool rc_update = true, isba;
456 struct ieee80211_tx_rate rates[4];
457 struct ath_frame_info *fi;
459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
464 hdr = (struct ieee80211_hdr *)skb->data;
466 tx_info = IEEE80211_SKB_CB(skb);
468 memcpy(rates, bf->rates, sizeof(rates));
470 retries = ts->ts_longretry + 1;
471 for (i = 0; i < ts->ts_rateindex; i++)
472 retries += rates[i].count;
476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
480 INIT_LIST_HEAD(&bf_head);
482 bf_next = bf->bf_next;
484 if (!bf->bf_state.stale || bf_next != NULL)
485 list_move_tail(&bf->list, &bf_head);
487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
494 an = (struct ath_node *)sta->drv_priv;
495 tid = ath_get_skb_tid(sc, an, skb);
496 seq_first = tid->seq_start;
497 isba = ts->ts_flags & ATH9K_TX_BA;
500 * The hardware occasionally sends a tx status for the wrong TID.
501 * In this case, the BA status cannot be considered valid and all
502 * subframes need to be retransmitted
504 * Only BlockAcks have a TID and therefore normal Acks cannot be
507 if (isba && tid->tidno != ts->tid)
510 isaggr = bf_isaggr(bf);
511 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
513 if (isaggr && txok) {
514 if (ts->ts_flags & ATH9K_TX_BA) {
515 seq_st = ts->ts_seqnum;
516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
519 * AR5416 can become deaf/mute when BA
520 * issue happens. Chip needs to be reset.
521 * But AP code may have sychronization issues
522 * when perform internal reset in this routine.
523 * Only enable reset in STA mode for now.
525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
530 __skb_queue_head_init(&bf_pending);
532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
534 u16 seqno = bf->bf_state.seqno;
536 txfail = txpending = sendbar = 0;
537 bf_next = bf->bf_next;
540 tx_info = IEEE80211_SKB_CB(skb);
541 fi = get_frame_info(skb);
543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
546 * Outside of the current BlockAck window,
547 * maybe part of a previous session
550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
551 /* transmit completion, subframe is
552 * acked by block ack */
554 } else if (!isaggr && txok) {
555 /* transmit completion */
559 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
560 if (txok || !an->sleeping)
561 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
568 bar_index = max_t(int, bar_index,
569 ATH_BA_INDEX(seq_first, seqno));
573 * Make sure the last desc is reclaimed if it
574 * not a holding desc.
576 INIT_LIST_HEAD(&bf_head);
577 if (bf_next != NULL || !bf_last->bf_state.stale)
578 list_move_tail(&bf->list, &bf_head);
582 * complete the acked-ones/xretried ones; update
585 ath_tx_update_baw(sc, tid, seqno);
587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
588 memcpy(tx_info->control.rates, rates, sizeof(rates));
589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
593 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
596 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
597 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
598 ieee80211_sta_eosp(sta);
600 /* retry the un-acked ones */
601 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
604 tbf = ath_clone_txbuf(sc, bf_last);
606 * Update tx baw and complete the
607 * frame with failed status if we
611 ath_tx_update_baw(sc, tid, seqno);
613 ath_tx_complete_buf(sc, bf, txq,
615 bar_index = max_t(int, bar_index,
616 ATH_BA_INDEX(seq_first, seqno));
624 * Put this buffer to the temporary pending
625 * queue to retain ordering
627 __skb_queue_tail(&bf_pending, skb);
633 /* prepend un-acked frames to the beginning of the pending frame queue */
634 if (!skb_queue_empty(&bf_pending)) {
636 ieee80211_sta_set_buffered(sta, tid->tidno, true);
638 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
640 ath_tx_queue_tid(txq, tid);
642 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
643 tid->ac->clear_ps_filter = true;
647 if (bar_index >= 0) {
648 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
650 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
651 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
653 ath_txq_unlock(sc, txq);
654 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
655 ath_txq_lock(sc, txq);
661 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
664 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
666 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
667 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
670 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
671 struct ath_tx_status *ts, struct ath_buf *bf,
672 struct list_head *bf_head)
674 struct ieee80211_tx_info *info;
677 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
678 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
679 txq->axq_tx_inprogress = false;
682 if (bf_is_ampdu_not_probing(bf))
683 txq->axq_ampdu_depth--;
685 if (!bf_isampdu(bf)) {
687 info = IEEE80211_SKB_CB(bf->bf_mpdu);
688 memcpy(info->control.rates, bf->rates,
689 sizeof(info->control.rates));
690 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
692 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
694 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
697 ath_txq_schedule(sc, txq);
700 static bool ath_lookup_legacy(struct ath_buf *bf)
703 struct ieee80211_tx_info *tx_info;
704 struct ieee80211_tx_rate *rates;
708 tx_info = IEEE80211_SKB_CB(skb);
709 rates = tx_info->control.rates;
711 for (i = 0; i < 4; i++) {
712 if (!rates[i].count || rates[i].idx < 0)
715 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
722 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
723 struct ath_atx_tid *tid)
726 struct ieee80211_tx_info *tx_info;
727 struct ieee80211_tx_rate *rates;
728 u32 max_4ms_framelen, frmlen;
729 u16 aggr_limit, bt_aggr_limit, legacy = 0;
730 int q = tid->ac->txq->mac80211_qnum;
734 tx_info = IEEE80211_SKB_CB(skb);
738 * Find the lowest frame length among the rate series that will have a
739 * 4ms (or TXOP limited) transmit duration.
741 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
743 for (i = 0; i < 4; i++) {
749 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
754 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
759 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
762 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
763 max_4ms_framelen = min(max_4ms_framelen, frmlen);
767 * limit aggregate size by the minimum rate if rate selected is
768 * not a probe rate, if rate selected is a probe rate then
769 * avoid aggregation of this packet.
771 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
774 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
777 * Override the default aggregation limit for BTCOEX.
779 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
781 aggr_limit = bt_aggr_limit;
784 * h/w can accept aggregates up to 16 bit lengths (65535).
785 * The IE, however can hold up to 65536, which shows up here
786 * as zero. Ignore 65536 since we are constrained by hw.
788 if (tid->an->maxampdu)
789 aggr_limit = min(aggr_limit, tid->an->maxampdu);
795 * Returns the number of delimiters to be added to
796 * meet the minimum required mpdudensity.
798 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
799 struct ath_buf *bf, u16 frmlen,
802 #define FIRST_DESC_NDELIMS 60
803 u32 nsymbits, nsymbols;
806 int width, streams, half_gi, ndelim, mindelim;
807 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
809 /* Select standard number of delimiters based on frame length alone */
810 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
813 * If encryption enabled, hardware requires some more padding between
815 * TODO - this could be improved to be dependent on the rate.
816 * The hardware can keep up at lower rates, but not higher rates
818 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
819 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
820 ndelim += ATH_AGGR_ENCRYPTDELIM;
823 * Add delimiter when using RTS/CTS with aggregation
824 * and non enterprise AR9003 card
826 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
827 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
828 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
831 * Convert desired mpdu density from microeconds to bytes based
832 * on highest rate in rate series (i.e. first rate) to determine
833 * required minimum length for subframe. Take into account
834 * whether high rate is 20 or 40Mhz and half or full GI.
836 * If there is no mpdu density restriction, no further calculation
840 if (tid->an->mpdudensity == 0)
843 rix = bf->rates[0].idx;
844 flags = bf->rates[0].flags;
845 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
846 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
849 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
851 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
856 streams = HT_RC_2_STREAMS(rix);
857 nsymbits = bits_per_symbol[rix % 8][width] * streams;
858 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
860 if (frmlen < minlen) {
861 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
862 ndelim = max(mindelim, ndelim);
868 static struct ath_buf *
869 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
870 struct ath_atx_tid *tid, struct sk_buff_head **q)
872 struct ieee80211_tx_info *tx_info;
873 struct ath_frame_info *fi;
880 if (skb_queue_empty(*q))
887 fi = get_frame_info(skb);
890 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
892 bf->bf_state.stale = false;
895 __skb_unlink(skb, *q);
896 ath_txq_skb_done(sc, txq, skb);
897 ieee80211_free_txskb(sc->hw, skb);
904 tx_info = IEEE80211_SKB_CB(skb);
905 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
906 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
907 bf->bf_state.bf_type = 0;
911 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
912 seqno = bf->bf_state.seqno;
914 /* do not step over block-ack window */
915 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
918 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
919 struct ath_tx_status ts = {};
920 struct list_head bf_head;
922 INIT_LIST_HEAD(&bf_head);
923 list_add(&bf->list, &bf_head);
924 __skb_unlink(skb, *q);
925 ath_tx_update_baw(sc, tid, seqno);
926 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
937 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
938 struct ath_atx_tid *tid, struct list_head *bf_q,
939 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
942 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
943 struct ath_buf *bf = bf_first, *bf_prev = NULL;
944 int nframes = 0, ndelim;
945 u16 aggr_limit = 0, al = 0, bpad = 0,
946 al_delta, h_baw = tid->baw_size / 2;
947 struct ieee80211_tx_info *tx_info;
948 struct ath_frame_info *fi;
953 aggr_limit = ath_lookup_rate(sc, bf, tid);
957 fi = get_frame_info(skb);
959 /* do not exceed aggregation limit */
960 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
962 if (aggr_limit < al + bpad + al_delta ||
963 ath_lookup_legacy(bf) || nframes >= h_baw)
966 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
967 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
968 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
972 /* add padding for previous frame to aggregation length */
973 al += bpad + al_delta;
976 * Get the delimiters needed to meet the MPDU
977 * density for this node.
979 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
981 bpad = PADBYTES(al_delta) + (ndelim << 2);
986 /* link buffers of this frame to the aggregate */
987 if (!fi->baw_tracked)
988 ath_tx_addto_baw(sc, tid, bf);
989 bf->bf_state.ndelim = ndelim;
991 __skb_unlink(skb, tid_q);
992 list_add_tail(&bf->list, bf_q);
994 bf_prev->bf_next = bf;
998 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1003 } while (ath_tid_has_buffered(tid));
1006 bf->bf_lastbf = bf_prev;
1008 if (bf == bf_prev) {
1009 al = get_frame_info(bf->bf_mpdu)->framelen;
1010 bf->bf_state.bf_type = BUF_AMPDU;
1012 TX_STAT_INC(txq->axq_qnum, a_aggr);
1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1024 * width - 0 for 20 MHz, 1 for 40 MHz
1025 * half_gi - to use 4us v/s 3.6 us for symbol time
1027 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1028 int width, int half_gi, bool shortPreamble)
1030 u32 nbits, nsymbits, duration, nsymbols;
1033 /* find number of symbols: PLCP + data */
1034 streams = HT_RC_2_STREAMS(rix);
1035 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1036 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1037 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1040 duration = SYMBOL_TIME(nsymbols);
1042 duration = SYMBOL_TIME_HALFGI(nsymbols);
1044 /* addup duration for legacy/ht training and signal fields */
1045 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1050 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1052 int streams = HT_RC_2_STREAMS(mcs);
1056 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1057 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1058 bits -= OFDM_PLCP_BITS;
1060 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1067 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1069 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1072 /* 4ms is the default (and maximum) duration */
1073 if (!txop || txop > 4096)
1076 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1077 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1078 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1079 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1080 for (mcs = 0; mcs < 32; mcs++) {
1081 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1082 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1083 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1084 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1088 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1089 struct ath_tx_info *info, int len, bool rts)
1091 struct ath_hw *ah = sc->sc_ah;
1092 struct sk_buff *skb;
1093 struct ieee80211_tx_info *tx_info;
1094 struct ieee80211_tx_rate *rates;
1095 const struct ieee80211_rate *rate;
1096 struct ieee80211_hdr *hdr;
1097 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1098 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1103 tx_info = IEEE80211_SKB_CB(skb);
1105 hdr = (struct ieee80211_hdr *)skb->data;
1107 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1108 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1109 info->rtscts_rate = fi->rtscts_rate;
1111 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1112 bool is_40, is_sgi, is_sp;
1115 if (!rates[i].count || (rates[i].idx < 0))
1119 info->rates[i].Tries = rates[i].count;
1122 * Handle RTS threshold for unaggregated HT frames.
1124 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1125 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1126 unlikely(rts_thresh != (u32) -1)) {
1127 if (!rts_thresh || (len > rts_thresh))
1131 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1132 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1133 info->flags |= ATH9K_TXDESC_RTSENA;
1134 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1135 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1136 info->flags |= ATH9K_TXDESC_CTSENA;
1139 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1140 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1141 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1144 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1145 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1146 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1148 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1150 info->rates[i].Rate = rix | 0x80;
1151 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1152 ah->txchainmask, info->rates[i].Rate);
1153 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1154 is_40, is_sgi, is_sp);
1155 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1156 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1161 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1162 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1163 !(rate->flags & IEEE80211_RATE_ERP_G))
1164 phy = WLAN_RC_PHY_CCK;
1166 phy = WLAN_RC_PHY_OFDM;
1168 info->rates[i].Rate = rate->hw_value;
1169 if (rate->hw_value_short) {
1170 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1171 info->rates[i].Rate |= rate->hw_value_short;
1176 if (bf->bf_state.bfs_paprd)
1177 info->rates[i].ChSel = ah->txchainmask;
1179 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1180 ah->txchainmask, info->rates[i].Rate);
1182 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1183 phy, rate->bitrate * 100, len, rix, is_sp);
1186 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1187 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1188 info->flags &= ~ATH9K_TXDESC_RTSENA;
1190 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1191 if (info->flags & ATH9K_TXDESC_RTSENA)
1192 info->flags &= ~ATH9K_TXDESC_CTSENA;
1195 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1197 struct ieee80211_hdr *hdr;
1198 enum ath9k_pkt_type htype;
1201 hdr = (struct ieee80211_hdr *)skb->data;
1202 fc = hdr->frame_control;
1204 if (ieee80211_is_beacon(fc))
1205 htype = ATH9K_PKT_TYPE_BEACON;
1206 else if (ieee80211_is_probe_resp(fc))
1207 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1208 else if (ieee80211_is_atim(fc))
1209 htype = ATH9K_PKT_TYPE_ATIM;
1210 else if (ieee80211_is_pspoll(fc))
1211 htype = ATH9K_PKT_TYPE_PSPOLL;
1213 htype = ATH9K_PKT_TYPE_NORMAL;
1218 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1219 struct ath_txq *txq, int len)
1221 struct ath_hw *ah = sc->sc_ah;
1222 struct ath_buf *bf_first = NULL;
1223 struct ath_tx_info info;
1224 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1227 memset(&info, 0, sizeof(info));
1228 info.is_first = true;
1229 info.is_last = true;
1230 info.txpower = MAX_RATE_POWER;
1231 info.qcu = txq->axq_qnum;
1234 struct sk_buff *skb = bf->bf_mpdu;
1235 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1236 struct ath_frame_info *fi = get_frame_info(skb);
1237 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1239 info.type = get_hw_packet_type(skb);
1241 info.link = bf->bf_next->bf_daddr;
1248 info.flags = ATH9K_TXDESC_INTREQ;
1249 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1250 txq == sc->tx.uapsdq)
1251 info.flags |= ATH9K_TXDESC_CLRDMASK;
1253 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1254 info.flags |= ATH9K_TXDESC_NOACK;
1255 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1256 info.flags |= ATH9K_TXDESC_LDPC;
1258 if (bf->bf_state.bfs_paprd)
1259 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1260 ATH9K_TXDESC_PAPRD_S;
1263 * mac80211 doesn't handle RTS threshold for HT because
1264 * the decision has to be taken based on AMPDU length
1265 * and aggregation is done entirely inside ath9k.
1266 * Set the RTS/CTS flag for the first subframe based
1269 if (aggr && (bf == bf_first) &&
1270 unlikely(rts_thresh != (u32) -1)) {
1272 * "len" is the size of the entire AMPDU.
1274 if (!rts_thresh || (len > rts_thresh))
1277 ath_buf_set_rate(sc, bf, &info, len, rts);
1280 info.buf_addr[0] = bf->bf_buf_addr;
1281 info.buf_len[0] = skb->len;
1282 info.pkt_len = fi->framelen;
1283 info.keyix = fi->keyix;
1284 info.keytype = fi->keytype;
1288 info.aggr = AGGR_BUF_FIRST;
1289 else if (bf == bf_first->bf_lastbf)
1290 info.aggr = AGGR_BUF_LAST;
1292 info.aggr = AGGR_BUF_MIDDLE;
1294 info.ndelim = bf->bf_state.ndelim;
1295 info.aggr_len = len;
1298 if (bf == bf_first->bf_lastbf)
1301 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1307 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1308 struct ath_atx_tid *tid, struct list_head *bf_q,
1309 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1311 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1312 struct sk_buff *skb;
1316 struct ieee80211_tx_info *tx_info;
1320 __skb_unlink(skb, tid_q);
1321 list_add_tail(&bf->list, bf_q);
1323 bf_prev->bf_next = bf;
1329 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1333 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1334 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1337 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1341 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1342 struct ath_atx_tid *tid, bool *stop)
1345 struct ieee80211_tx_info *tx_info;
1346 struct sk_buff_head *tid_q;
1347 struct list_head bf_q;
1349 bool aggr, last = true;
1351 if (!ath_tid_has_buffered(tid))
1354 INIT_LIST_HEAD(&bf_q);
1356 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1360 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1361 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1362 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1363 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1368 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1370 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1373 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1375 if (list_empty(&bf_q))
1378 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1379 tid->ac->clear_ps_filter = false;
1380 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1383 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1384 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1388 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1391 struct ath_atx_tid *txtid;
1392 struct ath_node *an;
1395 an = (struct ath_node *)sta->drv_priv;
1396 txtid = ATH_AN_2_TID(an, tid);
1398 /* update ampdu factor/density, they may have changed. This may happen
1399 * in HT IBSS when a beacon with HT-info is received after the station
1400 * has already been added.
1402 if (sta->ht_cap.ht_supported) {
1403 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1404 sta->ht_cap.ampdu_factor);
1405 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1406 an->mpdudensity = density;
1409 /* force sequence number allocation for pending frames */
1410 ath_tx_tid_change_state(sc, txtid);
1412 txtid->active = true;
1413 txtid->paused = true;
1414 *ssn = txtid->seq_start = txtid->seq_next;
1415 txtid->bar_index = -1;
1417 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1418 txtid->baw_head = txtid->baw_tail = 0;
1423 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1425 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1426 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1427 struct ath_txq *txq = txtid->ac->txq;
1429 ath_txq_lock(sc, txq);
1430 txtid->active = false;
1431 txtid->paused = false;
1432 ath_tx_flush_tid(sc, txtid);
1433 ath_tx_tid_change_state(sc, txtid);
1434 ath_txq_unlock_complete(sc, txq);
1437 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1438 struct ath_node *an)
1440 struct ath_atx_tid *tid;
1441 struct ath_atx_ac *ac;
1442 struct ath_txq *txq;
1446 for (tidno = 0, tid = &an->tid[tidno];
1447 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1455 ath_txq_lock(sc, txq);
1457 buffered = ath_tid_has_buffered(tid);
1460 list_del(&tid->list);
1464 list_del(&ac->list);
1467 ath_txq_unlock(sc, txq);
1469 ieee80211_sta_set_buffered(sta, tidno, buffered);
1473 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1475 struct ath_atx_tid *tid;
1476 struct ath_atx_ac *ac;
1477 struct ath_txq *txq;
1480 for (tidno = 0, tid = &an->tid[tidno];
1481 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1486 ath_txq_lock(sc, txq);
1487 ac->clear_ps_filter = true;
1489 if (!tid->paused && ath_tid_has_buffered(tid)) {
1490 ath_tx_queue_tid(txq, tid);
1491 ath_txq_schedule(sc, txq);
1494 ath_txq_unlock_complete(sc, txq);
1498 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1501 struct ath_atx_tid *tid;
1502 struct ath_node *an;
1503 struct ath_txq *txq;
1505 an = (struct ath_node *)sta->drv_priv;
1506 tid = ATH_AN_2_TID(an, tidno);
1509 ath_txq_lock(sc, txq);
1511 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1512 tid->paused = false;
1514 if (ath_tid_has_buffered(tid)) {
1515 ath_tx_queue_tid(txq, tid);
1516 ath_txq_schedule(sc, txq);
1519 ath_txq_unlock_complete(sc, txq);
1522 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1523 struct ieee80211_sta *sta,
1524 u16 tids, int nframes,
1525 enum ieee80211_frame_release_type reason,
1528 struct ath_softc *sc = hw->priv;
1529 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1530 struct ath_txq *txq = sc->tx.uapsdq;
1531 struct ieee80211_tx_info *info;
1532 struct list_head bf_q;
1533 struct ath_buf *bf_tail = NULL, *bf;
1534 struct sk_buff_head *tid_q;
1538 INIT_LIST_HEAD(&bf_q);
1539 for (i = 0; tids && nframes; i++, tids >>= 1) {
1540 struct ath_atx_tid *tid;
1545 tid = ATH_AN_2_TID(an, i);
1549 ath_txq_lock(sc, tid->ac->txq);
1550 while (nframes > 0) {
1551 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1555 __skb_unlink(bf->bf_mpdu, tid_q);
1556 list_add_tail(&bf->list, &bf_q);
1557 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1558 ath_tx_addto_baw(sc, tid, bf);
1559 bf->bf_state.bf_type &= ~BUF_AGGR;
1561 bf_tail->bf_next = bf;
1566 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1568 if (an->sta && !ath_tid_has_buffered(tid))
1569 ieee80211_sta_set_buffered(an->sta, i, false);
1571 ath_txq_unlock_complete(sc, tid->ac->txq);
1574 if (list_empty(&bf_q))
1577 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1578 info->flags |= IEEE80211_TX_STATUS_EOSP;
1580 bf = list_first_entry(&bf_q, struct ath_buf, list);
1581 ath_txq_lock(sc, txq);
1582 ath_tx_fill_desc(sc, bf, txq, 0);
1583 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1584 ath_txq_unlock(sc, txq);
1587 /********************/
1588 /* Queue Management */
1589 /********************/
1591 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1593 struct ath_hw *ah = sc->sc_ah;
1594 struct ath9k_tx_queue_info qi;
1595 static const int subtype_txq_to_hwq[] = {
1596 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1597 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1598 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1599 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1603 memset(&qi, 0, sizeof(qi));
1604 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1605 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1606 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1607 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1608 qi.tqi_physCompBuf = 0;
1611 * Enable interrupts only for EOL and DESC conditions.
1612 * We mark tx descriptors to receive a DESC interrupt
1613 * when a tx queue gets deep; otherwise waiting for the
1614 * EOL to reap descriptors. Note that this is done to
1615 * reduce interrupt load and this only defers reaping
1616 * descriptors, never transmitting frames. Aside from
1617 * reducing interrupts this also permits more concurrency.
1618 * The only potential downside is if the tx queue backs
1619 * up in which case the top half of the kernel may backup
1620 * due to a lack of tx descriptors.
1622 * The UAPSD queue is an exception, since we take a desc-
1623 * based intr on the EOSP frames.
1625 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1626 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1628 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1629 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1631 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1632 TXQ_FLAG_TXDESCINT_ENABLE;
1634 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1635 if (axq_qnum == -1) {
1637 * NB: don't print a message, this happens
1638 * normally on parts with too few tx queues
1642 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1643 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1645 txq->axq_qnum = axq_qnum;
1646 txq->mac80211_qnum = -1;
1647 txq->axq_link = NULL;
1648 __skb_queue_head_init(&txq->complete_q);
1649 INIT_LIST_HEAD(&txq->axq_q);
1650 INIT_LIST_HEAD(&txq->axq_acq);
1651 spin_lock_init(&txq->axq_lock);
1653 txq->axq_ampdu_depth = 0;
1654 txq->axq_tx_inprogress = false;
1655 sc->tx.txqsetup |= 1<<axq_qnum;
1657 txq->txq_headidx = txq->txq_tailidx = 0;
1658 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1659 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1661 return &sc->tx.txq[axq_qnum];
1664 int ath_txq_update(struct ath_softc *sc, int qnum,
1665 struct ath9k_tx_queue_info *qinfo)
1667 struct ath_hw *ah = sc->sc_ah;
1669 struct ath9k_tx_queue_info qi;
1671 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1673 ath9k_hw_get_txq_props(ah, qnum, &qi);
1674 qi.tqi_aifs = qinfo->tqi_aifs;
1675 qi.tqi_cwmin = qinfo->tqi_cwmin;
1676 qi.tqi_cwmax = qinfo->tqi_cwmax;
1677 qi.tqi_burstTime = qinfo->tqi_burstTime;
1678 qi.tqi_readyTime = qinfo->tqi_readyTime;
1680 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1681 ath_err(ath9k_hw_common(sc->sc_ah),
1682 "Unable to update hardware queue %u!\n", qnum);
1685 ath9k_hw_resettxqueue(ah, qnum);
1691 int ath_cabq_update(struct ath_softc *sc)
1693 struct ath9k_tx_queue_info qi;
1694 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1695 int qnum = sc->beacon.cabq->axq_qnum;
1697 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1699 qi.tqi_readyTime = (cur_conf->beacon_interval *
1700 ATH_CABQ_READY_TIME) / 100;
1701 ath_txq_update(sc, qnum, &qi);
1706 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1707 struct list_head *list)
1709 struct ath_buf *bf, *lastbf;
1710 struct list_head bf_head;
1711 struct ath_tx_status ts;
1713 memset(&ts, 0, sizeof(ts));
1714 ts.ts_status = ATH9K_TX_FLUSH;
1715 INIT_LIST_HEAD(&bf_head);
1717 while (!list_empty(list)) {
1718 bf = list_first_entry(list, struct ath_buf, list);
1720 if (bf->bf_state.stale) {
1721 list_del(&bf->list);
1723 ath_tx_return_buffer(sc, bf);
1727 lastbf = bf->bf_lastbf;
1728 list_cut_position(&bf_head, list, &lastbf->list);
1729 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1734 * Drain a given TX queue (could be Beacon or Data)
1736 * This assumes output has been stopped and
1737 * we do not need to block ath_tx_tasklet.
1739 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1741 ath_txq_lock(sc, txq);
1743 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1744 int idx = txq->txq_tailidx;
1746 while (!list_empty(&txq->txq_fifo[idx])) {
1747 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1749 INCR(idx, ATH_TXFIFO_DEPTH);
1751 txq->txq_tailidx = idx;
1754 txq->axq_link = NULL;
1755 txq->axq_tx_inprogress = false;
1756 ath_drain_txq_list(sc, txq, &txq->axq_q);
1758 ath_txq_unlock_complete(sc, txq);
1761 bool ath_drain_all_txq(struct ath_softc *sc)
1763 struct ath_hw *ah = sc->sc_ah;
1764 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1765 struct ath_txq *txq;
1769 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1772 ath9k_hw_abort_tx_dma(ah);
1774 /* Check if any queue remains active */
1775 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1776 if (!ATH_TXQ_SETUP(sc, i))
1779 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1784 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1786 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1787 if (!ATH_TXQ_SETUP(sc, i))
1791 * The caller will resume queues with ieee80211_wake_queues.
1792 * Mark the queue as not stopped to prevent ath_tx_complete
1793 * from waking the queue too early.
1795 txq = &sc->tx.txq[i];
1796 txq->stopped = false;
1797 ath_draintxq(sc, txq);
1803 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1805 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1806 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1809 /* For each axq_acq entry, for each tid, try to schedule packets
1810 * for transmit until ampdu_depth has reached min Q depth.
1812 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1814 struct ath_atx_ac *ac, *last_ac;
1815 struct ath_atx_tid *tid, *last_tid;
1818 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1819 list_empty(&txq->axq_acq))
1824 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1825 while (!list_empty(&txq->axq_acq)) {
1828 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1829 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1830 list_del(&ac->list);
1833 while (!list_empty(&ac->tid_q)) {
1835 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1837 list_del(&tid->list);
1843 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1847 * add tid to round-robin queue if more frames
1848 * are pending for the tid
1850 if (ath_tid_has_buffered(tid))
1851 ath_tx_queue_tid(txq, tid);
1853 if (stop || tid == last_tid)
1857 if (!list_empty(&ac->tid_q) && !ac->sched) {
1859 list_add_tail(&ac->list, &txq->axq_acq);
1865 if (ac == last_ac) {
1870 last_ac = list_entry(txq->axq_acq.prev,
1871 struct ath_atx_ac, list);
1883 * Insert a chain of ath_buf (descriptors) on a txq and
1884 * assume the descriptors are already chained together by caller.
1886 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1887 struct list_head *head, bool internal)
1889 struct ath_hw *ah = sc->sc_ah;
1890 struct ath_common *common = ath9k_hw_common(ah);
1891 struct ath_buf *bf, *bf_last;
1892 bool puttxbuf = false;
1896 * Insert the frame on the outbound list and
1897 * pass it on to the hardware.
1900 if (list_empty(head))
1903 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1904 bf = list_first_entry(head, struct ath_buf, list);
1905 bf_last = list_entry(head->prev, struct ath_buf, list);
1907 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1908 txq->axq_qnum, txq->axq_depth);
1910 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1911 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1912 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1915 list_splice_tail_init(head, &txq->axq_q);
1917 if (txq->axq_link) {
1918 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1919 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1920 txq->axq_qnum, txq->axq_link,
1921 ito64(bf->bf_daddr), bf->bf_desc);
1925 txq->axq_link = bf_last->bf_desc;
1929 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1930 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1931 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1932 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1936 TX_STAT_INC(txq->axq_qnum, txstart);
1937 ath9k_hw_txstart(ah, txq->axq_qnum);
1943 if (bf_is_ampdu_not_probing(bf))
1944 txq->axq_ampdu_depth++;
1946 bf = bf->bf_lastbf->bf_next;
1951 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1952 struct ath_atx_tid *tid, struct sk_buff *skb)
1954 struct ath_frame_info *fi = get_frame_info(skb);
1955 struct list_head bf_head;
1960 INIT_LIST_HEAD(&bf_head);
1961 list_add_tail(&bf->list, &bf_head);
1962 bf->bf_state.bf_type = 0;
1966 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1967 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1968 TX_STAT_INC(txq->axq_qnum, queued);
1971 static void setup_frame_info(struct ieee80211_hw *hw,
1972 struct ieee80211_sta *sta,
1973 struct sk_buff *skb,
1976 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1977 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1978 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1979 const struct ieee80211_rate *rate;
1980 struct ath_frame_info *fi = get_frame_info(skb);
1981 struct ath_node *an = NULL;
1982 enum ath9k_key_type keytype;
1983 bool short_preamble = false;
1986 * We check if Short Preamble is needed for the CTS rate by
1987 * checking the BSS's global flag.
1988 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1990 if (tx_info->control.vif &&
1991 tx_info->control.vif->bss_conf.use_short_preamble)
1992 short_preamble = true;
1994 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1995 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1998 an = (struct ath_node *) sta->drv_priv;
2000 memset(fi, 0, sizeof(*fi));
2002 fi->keyix = hw_key->hw_key_idx;
2003 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2004 fi->keyix = an->ps_key;
2006 fi->keyix = ATH9K_TXKEYIX_INVALID;
2007 fi->keytype = keytype;
2008 fi->framelen = framelen;
2012 fi->rtscts_rate = rate->hw_value;
2014 fi->rtscts_rate |= rate->hw_value_short;
2017 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2019 struct ath_hw *ah = sc->sc_ah;
2020 struct ath9k_channel *curchan = ah->curchan;
2022 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2023 (chainmask == 0x7) && (rate < 0x90))
2025 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2033 * Assign a descriptor (and sequence number if necessary,
2034 * and map buffer for DMA. Frees skb on error
2036 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2037 struct ath_txq *txq,
2038 struct ath_atx_tid *tid,
2039 struct sk_buff *skb)
2041 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2042 struct ath_frame_info *fi = get_frame_info(skb);
2043 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2048 bf = ath_tx_get_buffer(sc);
2050 ath_dbg(common, XMIT, "TX buffers are full\n");
2054 ATH_TXBUF_RESET(bf);
2057 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2058 seqno = tid->seq_next;
2059 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2062 hdr->seq_ctrl |= cpu_to_le16(fragno);
2064 if (!ieee80211_has_morefrags(hdr->frame_control))
2065 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2067 bf->bf_state.seqno = seqno;
2072 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2073 skb->len, DMA_TO_DEVICE);
2074 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2076 bf->bf_buf_addr = 0;
2077 ath_err(ath9k_hw_common(sc->sc_ah),
2078 "dma_mapping_error() on TX\n");
2079 ath_tx_return_buffer(sc, bf);
2088 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2089 struct ath_tx_control *txctl)
2091 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2092 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2093 struct ieee80211_sta *sta = txctl->sta;
2094 struct ieee80211_vif *vif = info->control.vif;
2095 struct ath_vif *avp;
2096 struct ath_softc *sc = hw->priv;
2097 int frmlen = skb->len + FCS_LEN;
2098 int padpos, padsize;
2100 /* NOTE: sta can be NULL according to net/mac80211.h */
2102 txctl->an = (struct ath_node *)sta->drv_priv;
2103 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2104 avp = (void *)vif->drv_priv;
2105 txctl->an = &avp->mcast_node;
2108 if (info->control.hw_key)
2109 frmlen += info->control.hw_key->icv_len;
2112 * As a temporary workaround, assign seq# here; this will likely need
2113 * to be cleaned up to work better with Beacon transmission and virtual
2116 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2117 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2118 sc->tx.seq_no += 0x10;
2119 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2120 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2123 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2124 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2125 !ieee80211_is_data(hdr->frame_control))
2126 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2128 /* Add the padding after the header if this is not already done */
2129 padpos = ieee80211_hdrlen(hdr->frame_control);
2130 padsize = padpos & 3;
2131 if (padsize && skb->len > padpos) {
2132 if (skb_headroom(skb) < padsize)
2135 skb_push(skb, padsize);
2136 memmove(skb->data, skb->data + padsize, padpos);
2139 setup_frame_info(hw, sta, skb, frmlen);
2144 /* Upon failure caller should free skb */
2145 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2146 struct ath_tx_control *txctl)
2148 struct ieee80211_hdr *hdr;
2149 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2150 struct ieee80211_sta *sta = txctl->sta;
2151 struct ieee80211_vif *vif = info->control.vif;
2152 struct ath_softc *sc = hw->priv;
2153 struct ath_txq *txq = txctl->txq;
2154 struct ath_atx_tid *tid = NULL;
2159 ret = ath_tx_prepare(hw, skb, txctl);
2163 hdr = (struct ieee80211_hdr *) skb->data;
2165 * At this point, the vif, hw_key and sta pointers in the tx control
2166 * info are no longer valid (overwritten by the ath_frame_info data.
2169 q = skb_get_queue_mapping(skb);
2171 ath_txq_lock(sc, txq);
2172 if (txq == sc->tx.txq_map[q] &&
2173 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2175 ieee80211_stop_queue(sc->hw, q);
2176 txq->stopped = true;
2179 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2180 ath_txq_unlock(sc, txq);
2181 txq = sc->tx.uapsdq;
2182 ath_txq_lock(sc, txq);
2183 } else if (txctl->an &&
2184 ieee80211_is_data_present(hdr->frame_control)) {
2185 tid = ath_get_skb_tid(sc, txctl->an, skb);
2187 WARN_ON(tid->ac->txq != txctl->txq);
2189 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2190 tid->ac->clear_ps_filter = true;
2193 * Add this frame to software queue for scheduling later
2196 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2197 __skb_queue_tail(&tid->buf_q, skb);
2198 if (!txctl->an->sleeping)
2199 ath_tx_queue_tid(txq, tid);
2201 ath_txq_schedule(sc, txq);
2205 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2207 ath_txq_skb_done(sc, txq, skb);
2209 dev_kfree_skb_any(skb);
2211 ieee80211_free_txskb(sc->hw, skb);
2215 bf->bf_state.bfs_paprd = txctl->paprd;
2218 bf->bf_state.bfs_paprd_timestamp = jiffies;
2220 ath_set_rates(vif, sta, bf);
2221 ath_tx_send_normal(sc, txq, tid, skb);
2224 ath_txq_unlock(sc, txq);
2229 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2230 struct sk_buff *skb)
2232 struct ath_softc *sc = hw->priv;
2233 struct ath_tx_control txctl = {
2234 .txq = sc->beacon.cabq
2236 struct ath_tx_info info = {};
2237 struct ieee80211_hdr *hdr;
2238 struct ath_buf *bf_tail = NULL;
2245 sc->cur_beacon_conf.beacon_interval * 1000 *
2246 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2249 struct ath_frame_info *fi = get_frame_info(skb);
2251 if (ath_tx_prepare(hw, skb, &txctl))
2254 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2259 ath_set_rates(vif, NULL, bf);
2260 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2261 duration += info.rates[0].PktDuration;
2263 bf_tail->bf_next = bf;
2265 list_add_tail(&bf->list, &bf_q);
2269 if (duration > max_duration)
2272 skb = ieee80211_get_buffered_bc(hw, vif);
2276 ieee80211_free_txskb(hw, skb);
2278 if (list_empty(&bf_q))
2281 bf = list_first_entry(&bf_q, struct ath_buf, list);
2282 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2284 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2285 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2286 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2287 sizeof(*hdr), DMA_TO_DEVICE);
2290 ath_txq_lock(sc, txctl.txq);
2291 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2292 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2293 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2294 ath_txq_unlock(sc, txctl.txq);
2301 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2302 int tx_flags, struct ath_txq *txq)
2304 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2305 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2306 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2307 int padpos, padsize;
2308 unsigned long flags;
2310 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2312 if (sc->sc_ah->caldata)
2313 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2315 if (!(tx_flags & ATH_TX_ERROR))
2316 /* Frame was ACKed */
2317 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2319 padpos = ieee80211_hdrlen(hdr->frame_control);
2320 padsize = padpos & 3;
2321 if (padsize && skb->len>padpos+padsize) {
2323 * Remove MAC header padding before giving the frame back to
2326 memmove(skb->data + padsize, skb->data, padpos);
2327 skb_pull(skb, padsize);
2330 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2331 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2332 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2334 "Going back to sleep after having received TX status (0x%lx)\n",
2335 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2337 PS_WAIT_FOR_PSPOLL_DATA |
2338 PS_WAIT_FOR_TX_ACK));
2340 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2342 __skb_queue_tail(&txq->complete_q, skb);
2343 ath_txq_skb_done(sc, txq, skb);
2346 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2347 struct ath_txq *txq, struct list_head *bf_q,
2348 struct ath_tx_status *ts, int txok)
2350 struct sk_buff *skb = bf->bf_mpdu;
2351 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2352 unsigned long flags;
2356 tx_flags |= ATH_TX_ERROR;
2358 if (ts->ts_status & ATH9K_TXERR_FILT)
2359 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2361 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2362 bf->bf_buf_addr = 0;
2364 if (bf->bf_state.bfs_paprd) {
2365 if (time_after(jiffies,
2366 bf->bf_state.bfs_paprd_timestamp +
2367 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2368 dev_kfree_skb_any(skb);
2370 complete(&sc->paprd_complete);
2372 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2373 ath_tx_complete(sc, skb, tx_flags, txq);
2375 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2376 * accidentally reference it later.
2381 * Return the list of ath_buf of this mpdu to free queue
2383 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2384 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2385 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2388 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2389 struct ath_tx_status *ts, int nframes, int nbad,
2392 struct sk_buff *skb = bf->bf_mpdu;
2393 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2394 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2395 struct ieee80211_hw *hw = sc->hw;
2396 struct ath_hw *ah = sc->sc_ah;
2400 tx_info->status.ack_signal = ts->ts_rssi;
2402 tx_rateindex = ts->ts_rateindex;
2403 WARN_ON(tx_rateindex >= hw->max_rates);
2405 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2406 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2408 BUG_ON(nbad > nframes);
2410 tx_info->status.ampdu_len = nframes;
2411 tx_info->status.ampdu_ack_len = nframes - nbad;
2413 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2414 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2416 * If an underrun error is seen assume it as an excessive
2417 * retry only if max frame trigger level has been reached
2418 * (2 KB for single stream, and 4 KB for dual stream).
2419 * Adjust the long retry as if the frame was tried
2420 * hw->max_rate_tries times to affect how rate control updates
2421 * PER for the failed rate.
2422 * In case of congestion on the bus penalizing this type of
2423 * underruns should help hardware actually transmit new frames
2424 * successfully by eventually preferring slower rates.
2425 * This itself should also alleviate congestion on the bus.
2427 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2428 ATH9K_TX_DELIM_UNDERRUN)) &&
2429 ieee80211_is_data(hdr->frame_control) &&
2430 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2431 tx_info->status.rates[tx_rateindex].count =
2435 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2436 tx_info->status.rates[i].count = 0;
2437 tx_info->status.rates[i].idx = -1;
2440 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2443 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2445 struct ath_hw *ah = sc->sc_ah;
2446 struct ath_common *common = ath9k_hw_common(ah);
2447 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2448 struct list_head bf_head;
2449 struct ath_desc *ds;
2450 struct ath_tx_status ts;
2453 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2454 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2457 ath_txq_lock(sc, txq);
2459 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2462 if (list_empty(&txq->axq_q)) {
2463 txq->axq_link = NULL;
2464 ath_txq_schedule(sc, txq);
2467 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2470 * There is a race condition that a BH gets scheduled
2471 * after sw writes TxE and before hw re-load the last
2472 * descriptor to get the newly chained one.
2473 * Software must keep the last DONE descriptor as a
2474 * holding descriptor - software does so by marking
2475 * it with the STALE flag.
2478 if (bf->bf_state.stale) {
2480 if (list_is_last(&bf_held->list, &txq->axq_q))
2483 bf = list_entry(bf_held->list.next, struct ath_buf,
2487 lastbf = bf->bf_lastbf;
2488 ds = lastbf->bf_desc;
2490 memset(&ts, 0, sizeof(ts));
2491 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2492 if (status == -EINPROGRESS)
2495 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2498 * Remove ath_buf's of the same transmit unit from txq,
2499 * however leave the last descriptor back as the holding
2500 * descriptor for hw.
2502 lastbf->bf_state.stale = true;
2503 INIT_LIST_HEAD(&bf_head);
2504 if (!list_is_singular(&lastbf->list))
2505 list_cut_position(&bf_head,
2506 &txq->axq_q, lastbf->list.prev);
2509 list_del(&bf_held->list);
2510 ath_tx_return_buffer(sc, bf_held);
2513 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2515 ath_txq_unlock_complete(sc, txq);
2518 void ath_tx_tasklet(struct ath_softc *sc)
2520 struct ath_hw *ah = sc->sc_ah;
2521 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2524 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2525 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2526 ath_tx_processq(sc, &sc->tx.txq[i]);
2530 void ath_tx_edma_tasklet(struct ath_softc *sc)
2532 struct ath_tx_status ts;
2533 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2534 struct ath_hw *ah = sc->sc_ah;
2535 struct ath_txq *txq;
2536 struct ath_buf *bf, *lastbf;
2537 struct list_head bf_head;
2538 struct list_head *fifo_list;
2542 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2545 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2546 if (status == -EINPROGRESS)
2548 if (status == -EIO) {
2549 ath_dbg(common, XMIT, "Error processing tx status\n");
2553 /* Process beacon completions separately */
2554 if (ts.qid == sc->beacon.beaconq) {
2555 sc->beacon.tx_processed = true;
2556 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2558 ath9k_csa_is_finished(sc);
2562 txq = &sc->tx.txq[ts.qid];
2564 ath_txq_lock(sc, txq);
2566 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2568 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2569 if (list_empty(fifo_list)) {
2570 ath_txq_unlock(sc, txq);
2574 bf = list_first_entry(fifo_list, struct ath_buf, list);
2575 if (bf->bf_state.stale) {
2576 list_del(&bf->list);
2577 ath_tx_return_buffer(sc, bf);
2578 bf = list_first_entry(fifo_list, struct ath_buf, list);
2581 lastbf = bf->bf_lastbf;
2583 INIT_LIST_HEAD(&bf_head);
2584 if (list_is_last(&lastbf->list, fifo_list)) {
2585 list_splice_tail_init(fifo_list, &bf_head);
2586 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2588 if (!list_empty(&txq->axq_q)) {
2589 struct list_head bf_q;
2591 INIT_LIST_HEAD(&bf_q);
2592 txq->axq_link = NULL;
2593 list_splice_tail_init(&txq->axq_q, &bf_q);
2594 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2597 lastbf->bf_state.stale = true;
2599 list_cut_position(&bf_head, fifo_list,
2603 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2604 ath_txq_unlock_complete(sc, txq);
2612 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2614 struct ath_descdma *dd = &sc->txsdma;
2615 u8 txs_len = sc->sc_ah->caps.txs_len;
2617 dd->dd_desc_len = size * txs_len;
2618 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2619 &dd->dd_desc_paddr, GFP_KERNEL);
2626 static int ath_tx_edma_init(struct ath_softc *sc)
2630 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2632 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2633 sc->txsdma.dd_desc_paddr,
2634 ATH_TXSTATUS_RING_SIZE);
2639 int ath_tx_init(struct ath_softc *sc, int nbufs)
2641 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2644 spin_lock_init(&sc->tx.txbuflock);
2646 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2650 "Failed to allocate tx descriptors: %d\n", error);
2654 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2655 "beacon", ATH_BCBUF, 1, 1);
2658 "Failed to allocate beacon descriptors: %d\n", error);
2662 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2664 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2665 error = ath_tx_edma_init(sc);
2670 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2672 struct ath_atx_tid *tid;
2673 struct ath_atx_ac *ac;
2676 for (tidno = 0, tid = &an->tid[tidno];
2677 tidno < IEEE80211_NUM_TIDS;
2681 tid->seq_start = tid->seq_next = 0;
2682 tid->baw_size = WME_MAX_BA;
2683 tid->baw_head = tid->baw_tail = 0;
2685 tid->paused = false;
2686 tid->active = false;
2687 __skb_queue_head_init(&tid->buf_q);
2688 __skb_queue_head_init(&tid->retry_q);
2689 acno = TID_TO_WME_AC(tidno);
2690 tid->ac = &an->ac[acno];
2693 for (acno = 0, ac = &an->ac[acno];
2694 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2696 ac->clear_ps_filter = true;
2697 ac->txq = sc->tx.txq_map[acno];
2698 INIT_LIST_HEAD(&ac->tid_q);
2702 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2704 struct ath_atx_ac *ac;
2705 struct ath_atx_tid *tid;
2706 struct ath_txq *txq;
2709 for (tidno = 0, tid = &an->tid[tidno];
2710 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2715 ath_txq_lock(sc, txq);
2718 list_del(&tid->list);
2723 list_del(&ac->list);
2724 tid->ac->sched = false;
2727 ath_tid_drain(sc, txq, tid);
2728 tid->active = false;
2730 ath_txq_unlock(sc, txq);