2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 static int ath_max_4ms_framelen[4][32] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
107 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
118 list_add_tail(&tid->list, &ac->tid_q);
124 list_add_tail(&ac->list, &txq->axq_acq);
127 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 struct ath_txq *txq = tid->ac->txq;
131 WARN_ON(!tid->paused);
133 spin_lock_bh(&txq->axq_lock);
136 if (skb_queue_empty(&tid->buf_q))
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
142 spin_unlock_bh(&txq->axq_lock);
145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
155 struct ath_txq *txq = tid->ac->txq;
158 struct list_head bf_head;
159 struct ath_tx_status ts;
160 struct ath_frame_info *fi;
162 INIT_LIST_HEAD(&bf_head);
164 memset(&ts, 0, sizeof(ts));
165 spin_lock_bh(&txq->axq_lock);
167 while ((skb = __skb_dequeue(&tid->buf_q))) {
168 fi = get_frame_info(skb);
171 spin_unlock_bh(&txq->axq_lock);
172 if (bf && fi->retries) {
173 list_add_tail(&bf->list, &bf_head);
174 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
175 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
177 ath_tx_send_normal(sc, txq, NULL, skb);
179 spin_lock_bh(&txq->axq_lock);
182 spin_unlock_bh(&txq->axq_lock);
185 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
190 index = ATH_BA_INDEX(tid->seq_start, seqno);
191 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
193 __clear_bit(cindex, tid->tx_buf);
195 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
196 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
197 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
201 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
206 index = ATH_BA_INDEX(tid->seq_start, seqno);
207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
208 __set_bit(cindex, tid->tx_buf);
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
229 struct list_head bf_head;
230 struct ath_tx_status ts;
231 struct ath_frame_info *fi;
233 memset(&ts, 0, sizeof(ts));
234 INIT_LIST_HEAD(&bf_head);
236 while ((skb = __skb_dequeue(&tid->buf_q))) {
237 fi = get_frame_info(skb);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
243 spin_lock(&txq->axq_lock);
247 list_add_tail(&bf->list, &bf_head);
250 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
252 spin_unlock(&txq->axq_lock);
253 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
254 spin_lock(&txq->axq_lock);
257 tid->seq_next = tid->seq_start;
258 tid->baw_tail = tid->baw_head;
261 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
264 struct ath_frame_info *fi = get_frame_info(skb);
265 struct ath_buf *bf = fi->bf;
266 struct ieee80211_hdr *hdr;
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
274 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
275 sizeof(*hdr), DMA_TO_DEVICE);
278 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
280 struct ath_buf *bf = NULL;
282 spin_lock_bh(&sc->tx.txbuflock);
284 if (unlikely(list_empty(&sc->tx.txbuf))) {
285 spin_unlock_bh(&sc->tx.txbuflock);
289 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
292 spin_unlock_bh(&sc->tx.txbuflock);
297 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
299 spin_lock_bh(&sc->tx.txbuflock);
300 list_add_tail(&bf->list, &sc->tx.txbuf);
301 spin_unlock_bh(&sc->tx.txbuflock);
304 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
308 tbf = ath_tx_get_buffer(sc);
312 ATH_TXBUF_RESET(tbf);
314 tbf->bf_mpdu = bf->bf_mpdu;
315 tbf->bf_buf_addr = bf->bf_buf_addr;
316 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
317 tbf->bf_state = bf->bf_state;
322 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
323 struct ath_tx_status *ts, int txok,
324 int *nframes, int *nbad)
326 struct ath_frame_info *fi;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
335 isaggr = bf_isaggr(bf);
337 seq_st = ts->ts_seqnum;
338 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
342 fi = get_frame_info(bf->bf_mpdu);
343 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
346 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
354 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
355 struct ath_buf *bf, struct list_head *bf_q,
356 struct ath_tx_status *ts, int txok, bool retry)
358 struct ath_node *an = NULL;
360 struct ieee80211_sta *sta;
361 struct ieee80211_hw *hw = sc->hw;
362 struct ieee80211_hdr *hdr;
363 struct ieee80211_tx_info *tx_info;
364 struct ath_atx_tid *tid = NULL;
365 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
366 struct list_head bf_head;
367 struct sk_buff_head bf_pending;
368 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
370 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
371 bool rc_update = true;
372 struct ieee80211_tx_rate rates[4];
373 struct ath_frame_info *fi;
379 hdr = (struct ieee80211_hdr *)skb->data;
381 tx_info = IEEE80211_SKB_CB(skb);
383 memcpy(rates, tx_info->control.rates, sizeof(rates));
387 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
391 INIT_LIST_HEAD(&bf_head);
393 bf_next = bf->bf_next;
395 if (!bf->bf_stale || bf_next != NULL)
396 list_move_tail(&bf->list, &bf_head);
398 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
406 an = (struct ath_node *)sta->drv_priv;
407 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
408 tid = ATH_AN_2_TID(an, tidno);
411 * The hardware occasionally sends a tx status for the wrong TID.
412 * In this case, the BA status cannot be considered valid and all
413 * subframes need to be retransmitted
415 if (tidno != ts->tid)
418 isaggr = bf_isaggr(bf);
419 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
421 if (isaggr && txok) {
422 if (ts->ts_flags & ATH9K_TX_BA) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
427 * AR5416 can become deaf/mute when BA
428 * issue happens. Chip needs to be reset.
429 * But AP code may have sychronization issues
430 * when perform internal reset in this routine.
431 * Only enable reset in STA mode for now.
433 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
438 __skb_queue_head_init(&bf_pending);
440 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
442 u16 seqno = bf->bf_state.seqno;
444 txfail = txpending = sendbar = 0;
445 bf_next = bf->bf_next;
448 tx_info = IEEE80211_SKB_CB(skb);
449 fi = get_frame_info(skb);
451 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
452 /* transmit completion, subframe is
453 * acked by block ack */
455 } else if (!isaggr && txok) {
456 /* transmit completion */
459 if ((tid->state & AGGR_CLEANUP) || !retry) {
461 * cleanup in progress, just fail
462 * the un-acked sub-frames
465 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
466 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
468 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
480 * Make sure the last desc is reclaimed if it
481 * not a holding desc.
483 INIT_LIST_HEAD(&bf_head);
484 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
485 bf_next != NULL || !bf_last->bf_stale)
486 list_move_tail(&bf->list, &bf_head);
488 if (!txpending || (tid->state & AGGR_CLEANUP)) {
490 * complete the acked-ones/xretried ones; update
493 spin_lock_bh(&txq->axq_lock);
494 ath_tx_update_baw(sc, tid, seqno);
495 spin_unlock_bh(&txq->axq_lock);
497 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
498 memcpy(tx_info->control.rates, rates, sizeof(rates));
499 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
503 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
506 /* retry the un-acked ones */
507 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
508 if (bf->bf_next == NULL && bf_last->bf_stale) {
511 tbf = ath_clone_txbuf(sc, bf_last);
513 * Update tx baw and complete the
514 * frame with failed status if we
518 spin_lock_bh(&txq->axq_lock);
519 ath_tx_update_baw(sc, tid, seqno);
520 spin_unlock_bh(&txq->axq_lock);
522 ath_tx_complete_buf(sc, bf, txq,
533 * Put this buffer to the temporary pending
534 * queue to retain ordering
536 __skb_queue_tail(&bf_pending, skb);
542 /* prepend un-acked frames to the beginning of the pending frame queue */
543 if (!skb_queue_empty(&bf_pending)) {
545 ieee80211_sta_set_buffered(sta, tid->tidno, true);
547 spin_lock_bh(&txq->axq_lock);
549 tid->ac->clear_ps_filter = true;
550 skb_queue_splice(&bf_pending, &tid->buf_q);
552 ath_tx_queue_tid(txq, tid);
553 spin_unlock_bh(&txq->axq_lock);
556 if (tid->state & AGGR_CLEANUP) {
557 ath_tx_flush_tid(sc, tid);
559 if (tid->baw_head == tid->baw_tail) {
560 tid->state &= ~AGGR_ADDBA_COMPLETE;
561 tid->state &= ~AGGR_CLEANUP;
568 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
569 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
573 static bool ath_lookup_legacy(struct ath_buf *bf)
576 struct ieee80211_tx_info *tx_info;
577 struct ieee80211_tx_rate *rates;
581 tx_info = IEEE80211_SKB_CB(skb);
582 rates = tx_info->control.rates;
584 for (i = 0; i < 4; i++) {
585 if (!rates[i].count || rates[i].idx < 0)
588 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
595 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
596 struct ath_atx_tid *tid)
599 struct ieee80211_tx_info *tx_info;
600 struct ieee80211_tx_rate *rates;
601 u32 max_4ms_framelen, frmlen;
602 u16 aggr_limit, legacy = 0;
606 tx_info = IEEE80211_SKB_CB(skb);
607 rates = tx_info->control.rates;
610 * Find the lowest frame length among the rate series that will have a
611 * 4ms transmit duration.
612 * TODO - TXOP limit needs to be considered.
614 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
616 for (i = 0; i < 4; i++) {
617 if (rates[i].count) {
619 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
624 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
629 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
632 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
633 max_4ms_framelen = min(max_4ms_framelen, frmlen);
638 * limit aggregate size by the minimum rate if rate selected is
639 * not a probe rate, if rate selected is a probe rate then
640 * avoid aggregation of this packet.
642 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
645 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
646 aggr_limit = min((max_4ms_framelen * 3) / 8,
647 (u32)ATH_AMPDU_LIMIT_MAX);
649 aggr_limit = min(max_4ms_framelen,
650 (u32)ATH_AMPDU_LIMIT_MAX);
653 * h/w can accept aggregates up to 16 bit lengths (65535).
654 * The IE, however can hold up to 65536, which shows up here
655 * as zero. Ignore 65536 since we are constrained by hw.
657 if (tid->an->maxampdu)
658 aggr_limit = min(aggr_limit, tid->an->maxampdu);
664 * Returns the number of delimiters to be added to
665 * meet the minimum required mpdudensity.
667 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
668 struct ath_buf *bf, u16 frmlen,
671 #define FIRST_DESC_NDELIMS 60
672 struct sk_buff *skb = bf->bf_mpdu;
673 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
674 u32 nsymbits, nsymbols;
677 int width, streams, half_gi, ndelim, mindelim;
678 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
680 /* Select standard number of delimiters based on frame length alone */
681 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
684 * If encryption enabled, hardware requires some more padding between
686 * TODO - this could be improved to be dependent on the rate.
687 * The hardware can keep up at lower rates, but not higher rates
689 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
690 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
691 ndelim += ATH_AGGR_ENCRYPTDELIM;
694 * Add delimiter when using RTS/CTS with aggregation
695 * and non enterprise AR9003 card
697 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
698 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
699 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
702 * Convert desired mpdu density from microeconds to bytes based
703 * on highest rate in rate series (i.e. first rate) to determine
704 * required minimum length for subframe. Take into account
705 * whether high rate is 20 or 40Mhz and half or full GI.
707 * If there is no mpdu density restriction, no further calculation
711 if (tid->an->mpdudensity == 0)
714 rix = tx_info->control.rates[0].idx;
715 flags = tx_info->control.rates[0].flags;
716 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
717 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
720 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
722 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
727 streams = HT_RC_2_STREAMS(rix);
728 nsymbits = bits_per_symbol[rix % 8][width] * streams;
729 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
731 if (frmlen < minlen) {
732 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
733 ndelim = max(mindelim, ndelim);
739 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
741 struct ath_atx_tid *tid,
742 struct list_head *bf_q,
745 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
746 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
747 int rl = 0, nframes = 0, ndelim, prev_al = 0;
748 u16 aggr_limit = 0, al = 0, bpad = 0,
749 al_delta, h_baw = tid->baw_size / 2;
750 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
751 struct ieee80211_tx_info *tx_info;
752 struct ath_frame_info *fi;
757 skb = skb_peek(&tid->buf_q);
758 fi = get_frame_info(skb);
761 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
766 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
767 seqno = bf->bf_state.seqno;
771 /* do not step over block-ack window */
772 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
773 status = ATH_AGGR_BAW_CLOSED;
778 aggr_limit = ath_lookup_rate(sc, bf, tid);
782 /* do not exceed aggregation limit */
783 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
786 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
787 ath_lookup_legacy(bf))) {
788 status = ATH_AGGR_LIMITED;
792 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
793 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
796 /* do not exceed subframe limit */
797 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
798 status = ATH_AGGR_LIMITED;
802 /* add padding for previous frame to aggregation length */
803 al += bpad + al_delta;
806 * Get the delimiters needed to meet the MPDU
807 * density for this node.
809 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
811 bpad = PADBYTES(al_delta) + (ndelim << 2);
816 /* link buffers of this frame to the aggregate */
818 ath_tx_addto_baw(sc, tid, seqno);
819 bf->bf_state.ndelim = ndelim;
821 __skb_unlink(skb, &tid->buf_q);
822 list_add_tail(&bf->list, bf_q);
824 bf_prev->bf_next = bf;
828 } while (!skb_queue_empty(&tid->buf_q));
838 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
839 * width - 0 for 20 MHz, 1 for 40 MHz
840 * half_gi - to use 4us v/s 3.6 us for symbol time
842 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
843 int width, int half_gi, bool shortPreamble)
845 u32 nbits, nsymbits, duration, nsymbols;
848 /* find number of symbols: PLCP + data */
849 streams = HT_RC_2_STREAMS(rix);
850 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
851 nsymbits = bits_per_symbol[rix % 8][width] * streams;
852 nsymbols = (nbits + nsymbits - 1) / nsymbits;
855 duration = SYMBOL_TIME(nsymbols);
857 duration = SYMBOL_TIME_HALFGI(nsymbols);
859 /* addup duration for legacy/ht training and signal fields */
860 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
865 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
866 struct ath_tx_info *info, int len)
868 struct ath_hw *ah = sc->sc_ah;
870 struct ieee80211_tx_info *tx_info;
871 struct ieee80211_tx_rate *rates;
872 const struct ieee80211_rate *rate;
873 struct ieee80211_hdr *hdr;
878 tx_info = IEEE80211_SKB_CB(skb);
879 rates = tx_info->control.rates;
880 hdr = (struct ieee80211_hdr *)skb->data;
882 /* set dur_update_en for l-sig computation except for PS-Poll frames */
883 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
886 * We check if Short Preamble is needed for the CTS rate by
887 * checking the BSS's global flag.
888 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
890 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
891 info->rtscts_rate = rate->hw_value;
892 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
893 info->rtscts_rate |= rate->hw_value_short;
895 for (i = 0; i < 4; i++) {
896 bool is_40, is_sgi, is_sp;
899 if (!rates[i].count || (rates[i].idx < 0))
903 info->rates[i].Tries = rates[i].count;
905 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
906 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
907 info->flags |= ATH9K_TXDESC_RTSENA;
908 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
909 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
910 info->flags |= ATH9K_TXDESC_CTSENA;
913 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
914 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
915 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
916 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
918 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
919 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
920 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
922 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
924 info->rates[i].Rate = rix | 0x80;
925 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
926 ah->txchainmask, info->rates[i].Rate);
927 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
928 is_40, is_sgi, is_sp);
929 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
930 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
935 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
936 !(rate->flags & IEEE80211_RATE_ERP_G))
937 phy = WLAN_RC_PHY_CCK;
939 phy = WLAN_RC_PHY_OFDM;
941 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
942 info->rates[i].Rate = rate->hw_value;
943 if (rate->hw_value_short) {
944 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
945 info->rates[i].Rate |= rate->hw_value_short;
950 if (bf->bf_state.bfs_paprd)
951 info->rates[i].ChSel = ah->txchainmask;
953 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
954 ah->txchainmask, info->rates[i].Rate);
956 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
957 phy, rate->bitrate * 100, len, rix, is_sp);
960 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
961 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
962 info->flags &= ~ATH9K_TXDESC_RTSENA;
964 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
965 if (info->flags & ATH9K_TXDESC_RTSENA)
966 info->flags &= ~ATH9K_TXDESC_CTSENA;
969 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
971 struct ieee80211_hdr *hdr;
972 enum ath9k_pkt_type htype;
975 hdr = (struct ieee80211_hdr *)skb->data;
976 fc = hdr->frame_control;
978 if (ieee80211_is_beacon(fc))
979 htype = ATH9K_PKT_TYPE_BEACON;
980 else if (ieee80211_is_probe_resp(fc))
981 htype = ATH9K_PKT_TYPE_PROBE_RESP;
982 else if (ieee80211_is_atim(fc))
983 htype = ATH9K_PKT_TYPE_ATIM;
984 else if (ieee80211_is_pspoll(fc))
985 htype = ATH9K_PKT_TYPE_PSPOLL;
987 htype = ATH9K_PKT_TYPE_NORMAL;
992 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
993 struct ath_txq *txq, int len)
995 struct ath_hw *ah = sc->sc_ah;
996 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
997 struct ath_buf *bf_first = bf;
998 struct ath_tx_info info;
999 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1001 memset(&info, 0, sizeof(info));
1002 info.is_first = true;
1003 info.is_last = true;
1004 info.txpower = MAX_RATE_POWER;
1005 info.qcu = txq->axq_qnum;
1007 info.flags = ATH9K_TXDESC_INTREQ;
1008 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1009 info.flags |= ATH9K_TXDESC_NOACK;
1010 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1011 info.flags |= ATH9K_TXDESC_LDPC;
1013 ath_buf_set_rate(sc, bf, &info, len);
1015 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1016 info.flags |= ATH9K_TXDESC_CLRDMASK;
1018 if (bf->bf_state.bfs_paprd)
1019 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1023 struct sk_buff *skb = bf->bf_mpdu;
1024 struct ath_frame_info *fi = get_frame_info(skb);
1026 info.type = get_hw_packet_type(skb);
1028 info.link = bf->bf_next->bf_daddr;
1032 info.buf_addr[0] = bf->bf_buf_addr;
1033 info.buf_len[0] = skb->len;
1034 info.pkt_len = fi->framelen;
1035 info.keyix = fi->keyix;
1036 info.keytype = fi->keytype;
1040 info.aggr = AGGR_BUF_FIRST;
1041 else if (!bf->bf_next)
1042 info.aggr = AGGR_BUF_LAST;
1044 info.aggr = AGGR_BUF_MIDDLE;
1046 info.ndelim = bf->bf_state.ndelim;
1047 info.aggr_len = len;
1050 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1055 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1056 struct ath_atx_tid *tid)
1059 enum ATH_AGGR_STATUS status;
1060 struct ieee80211_tx_info *tx_info;
1061 struct list_head bf_q;
1065 if (skb_queue_empty(&tid->buf_q))
1068 INIT_LIST_HEAD(&bf_q);
1070 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1073 * no frames picked up to be aggregated;
1074 * block-ack window is not open.
1076 if (list_empty(&bf_q))
1079 bf = list_first_entry(&bf_q, struct ath_buf, list);
1080 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1081 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1083 if (tid->ac->clear_ps_filter) {
1084 tid->ac->clear_ps_filter = false;
1085 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1087 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1090 /* if only one frame, send as non-aggregate */
1091 if (bf == bf->bf_lastbf) {
1092 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1093 bf->bf_state.bf_type = BUF_AMPDU;
1095 TX_STAT_INC(txq->axq_qnum, a_aggr);
1098 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1099 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1100 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1101 status != ATH_AGGR_BAW_CLOSED);
1104 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1107 struct ath_atx_tid *txtid;
1108 struct ath_node *an;
1110 an = (struct ath_node *)sta->drv_priv;
1111 txtid = ATH_AN_2_TID(an, tid);
1113 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1116 txtid->state |= AGGR_ADDBA_PROGRESS;
1117 txtid->paused = true;
1118 *ssn = txtid->seq_start = txtid->seq_next;
1120 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1121 txtid->baw_head = txtid->baw_tail = 0;
1126 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1128 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1129 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1130 struct ath_txq *txq = txtid->ac->txq;
1132 if (txtid->state & AGGR_CLEANUP)
1135 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1136 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1140 spin_lock_bh(&txq->axq_lock);
1141 txtid->paused = true;
1144 * If frames are still being transmitted for this TID, they will be
1145 * cleaned up during tx completion. To prevent race conditions, this
1146 * TID can only be reused after all in-progress subframes have been
1149 if (txtid->baw_head != txtid->baw_tail)
1150 txtid->state |= AGGR_CLEANUP;
1152 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1153 spin_unlock_bh(&txq->axq_lock);
1155 ath_tx_flush_tid(sc, txtid);
1158 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1159 struct ath_node *an)
1161 struct ath_atx_tid *tid;
1162 struct ath_atx_ac *ac;
1163 struct ath_txq *txq;
1167 for (tidno = 0, tid = &an->tid[tidno];
1168 tidno < WME_NUM_TID; tidno++, tid++) {
1176 spin_lock_bh(&txq->axq_lock);
1178 buffered = !skb_queue_empty(&tid->buf_q);
1181 list_del(&tid->list);
1185 list_del(&ac->list);
1188 spin_unlock_bh(&txq->axq_lock);
1190 ieee80211_sta_set_buffered(sta, tidno, buffered);
1194 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1196 struct ath_atx_tid *tid;
1197 struct ath_atx_ac *ac;
1198 struct ath_txq *txq;
1201 for (tidno = 0, tid = &an->tid[tidno];
1202 tidno < WME_NUM_TID; tidno++, tid++) {
1207 spin_lock_bh(&txq->axq_lock);
1208 ac->clear_ps_filter = true;
1210 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1211 ath_tx_queue_tid(txq, tid);
1212 ath_txq_schedule(sc, txq);
1215 spin_unlock_bh(&txq->axq_lock);
1219 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1221 struct ath_atx_tid *txtid;
1222 struct ath_node *an;
1224 an = (struct ath_node *)sta->drv_priv;
1226 if (sc->sc_flags & SC_OP_TXAGGR) {
1227 txtid = ATH_AN_2_TID(an, tid);
1229 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1230 txtid->state |= AGGR_ADDBA_COMPLETE;
1231 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1232 ath_tx_resume_tid(sc, txtid);
1236 /********************/
1237 /* Queue Management */
1238 /********************/
1240 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1241 struct ath_txq *txq)
1243 struct ath_atx_ac *ac, *ac_tmp;
1244 struct ath_atx_tid *tid, *tid_tmp;
1246 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1247 list_del(&ac->list);
1249 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1250 list_del(&tid->list);
1252 ath_tid_drain(sc, txq, tid);
1257 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1259 struct ath_hw *ah = sc->sc_ah;
1260 struct ath9k_tx_queue_info qi;
1261 static const int subtype_txq_to_hwq[] = {
1262 [WME_AC_BE] = ATH_TXQ_AC_BE,
1263 [WME_AC_BK] = ATH_TXQ_AC_BK,
1264 [WME_AC_VI] = ATH_TXQ_AC_VI,
1265 [WME_AC_VO] = ATH_TXQ_AC_VO,
1269 memset(&qi, 0, sizeof(qi));
1270 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1271 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1272 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1273 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1274 qi.tqi_physCompBuf = 0;
1277 * Enable interrupts only for EOL and DESC conditions.
1278 * We mark tx descriptors to receive a DESC interrupt
1279 * when a tx queue gets deep; otherwise waiting for the
1280 * EOL to reap descriptors. Note that this is done to
1281 * reduce interrupt load and this only defers reaping
1282 * descriptors, never transmitting frames. Aside from
1283 * reducing interrupts this also permits more concurrency.
1284 * The only potential downside is if the tx queue backs
1285 * up in which case the top half of the kernel may backup
1286 * due to a lack of tx descriptors.
1288 * The UAPSD queue is an exception, since we take a desc-
1289 * based intr on the EOSP frames.
1291 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1292 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1293 TXQ_FLAG_TXERRINT_ENABLE;
1295 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1296 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1298 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1299 TXQ_FLAG_TXDESCINT_ENABLE;
1301 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1302 if (axq_qnum == -1) {
1304 * NB: don't print a message, this happens
1305 * normally on parts with too few tx queues
1309 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1310 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1312 txq->axq_qnum = axq_qnum;
1313 txq->mac80211_qnum = -1;
1314 txq->axq_link = NULL;
1315 INIT_LIST_HEAD(&txq->axq_q);
1316 INIT_LIST_HEAD(&txq->axq_acq);
1317 spin_lock_init(&txq->axq_lock);
1319 txq->axq_ampdu_depth = 0;
1320 txq->axq_tx_inprogress = false;
1321 sc->tx.txqsetup |= 1<<axq_qnum;
1323 txq->txq_headidx = txq->txq_tailidx = 0;
1324 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1325 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1327 return &sc->tx.txq[axq_qnum];
1330 int ath_txq_update(struct ath_softc *sc, int qnum,
1331 struct ath9k_tx_queue_info *qinfo)
1333 struct ath_hw *ah = sc->sc_ah;
1335 struct ath9k_tx_queue_info qi;
1337 if (qnum == sc->beacon.beaconq) {
1339 * XXX: for beacon queue, we just save the parameter.
1340 * It will be picked up by ath_beaconq_config when
1343 sc->beacon.beacon_qi = *qinfo;
1347 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1349 ath9k_hw_get_txq_props(ah, qnum, &qi);
1350 qi.tqi_aifs = qinfo->tqi_aifs;
1351 qi.tqi_cwmin = qinfo->tqi_cwmin;
1352 qi.tqi_cwmax = qinfo->tqi_cwmax;
1353 qi.tqi_burstTime = qinfo->tqi_burstTime;
1354 qi.tqi_readyTime = qinfo->tqi_readyTime;
1356 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1357 ath_err(ath9k_hw_common(sc->sc_ah),
1358 "Unable to update hardware queue %u!\n", qnum);
1361 ath9k_hw_resettxqueue(ah, qnum);
1367 int ath_cabq_update(struct ath_softc *sc)
1369 struct ath9k_tx_queue_info qi;
1370 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1371 int qnum = sc->beacon.cabq->axq_qnum;
1373 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1375 * Ensure the readytime % is within the bounds.
1377 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1378 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1379 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1380 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1382 qi.tqi_readyTime = (cur_conf->beacon_interval *
1383 sc->config.cabqReadytime) / 100;
1384 ath_txq_update(sc, qnum, &qi);
1389 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1391 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1392 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1395 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1396 struct list_head *list, bool retry_tx)
1397 __releases(txq->axq_lock)
1398 __acquires(txq->axq_lock)
1400 struct ath_buf *bf, *lastbf;
1401 struct list_head bf_head;
1402 struct ath_tx_status ts;
1404 memset(&ts, 0, sizeof(ts));
1405 INIT_LIST_HEAD(&bf_head);
1407 while (!list_empty(list)) {
1408 bf = list_first_entry(list, struct ath_buf, list);
1411 list_del(&bf->list);
1413 ath_tx_return_buffer(sc, bf);
1417 lastbf = bf->bf_lastbf;
1418 list_cut_position(&bf_head, list, &lastbf->list);
1421 if (bf_is_ampdu_not_probing(bf))
1422 txq->axq_ampdu_depth--;
1424 spin_unlock_bh(&txq->axq_lock);
1426 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1429 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1430 spin_lock_bh(&txq->axq_lock);
1435 * Drain a given TX queue (could be Beacon or Data)
1437 * This assumes output has been stopped and
1438 * we do not need to block ath_tx_tasklet.
1440 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1442 spin_lock_bh(&txq->axq_lock);
1443 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1444 int idx = txq->txq_tailidx;
1446 while (!list_empty(&txq->txq_fifo[idx])) {
1447 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1450 INCR(idx, ATH_TXFIFO_DEPTH);
1452 txq->txq_tailidx = idx;
1455 txq->axq_link = NULL;
1456 txq->axq_tx_inprogress = false;
1457 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1459 /* flush any pending frames if aggregation is enabled */
1460 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1461 ath_txq_drain_pending_buffers(sc, txq);
1463 spin_unlock_bh(&txq->axq_lock);
1466 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1468 struct ath_hw *ah = sc->sc_ah;
1469 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1470 struct ath_txq *txq;
1474 if (sc->sc_flags & SC_OP_INVALID)
1477 ath9k_hw_abort_tx_dma(ah);
1479 /* Check if any queue remains active */
1480 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1481 if (!ATH_TXQ_SETUP(sc, i))
1484 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1489 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1491 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1492 if (!ATH_TXQ_SETUP(sc, i))
1496 * The caller will resume queues with ieee80211_wake_queues.
1497 * Mark the queue as not stopped to prevent ath_tx_complete
1498 * from waking the queue too early.
1500 txq = &sc->tx.txq[i];
1501 txq->stopped = false;
1502 ath_draintxq(sc, txq, retry_tx);
1508 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1510 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1511 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1514 /* For each axq_acq entry, for each tid, try to schedule packets
1515 * for transmit until ampdu_depth has reached min Q depth.
1517 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1519 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1520 struct ath_atx_tid *tid, *last_tid;
1522 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1523 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1526 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1527 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1529 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1530 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1531 list_del(&ac->list);
1534 while (!list_empty(&ac->tid_q)) {
1535 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1537 list_del(&tid->list);
1543 ath_tx_sched_aggr(sc, txq, tid);
1546 * add tid to round-robin queue if more frames
1547 * are pending for the tid
1549 if (!skb_queue_empty(&tid->buf_q))
1550 ath_tx_queue_tid(txq, tid);
1552 if (tid == last_tid ||
1553 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1557 if (!list_empty(&ac->tid_q)) {
1560 list_add_tail(&ac->list, &txq->axq_acq);
1564 if (ac == last_ac ||
1565 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1575 * Insert a chain of ath_buf (descriptors) on a txq and
1576 * assume the descriptors are already chained together by caller.
1578 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1579 struct list_head *head, bool internal)
1581 struct ath_hw *ah = sc->sc_ah;
1582 struct ath_common *common = ath9k_hw_common(ah);
1583 struct ath_buf *bf, *bf_last;
1584 bool puttxbuf = false;
1588 * Insert the frame on the outbound list and
1589 * pass it on to the hardware.
1592 if (list_empty(head))
1595 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1596 bf = list_first_entry(head, struct ath_buf, list);
1597 bf_last = list_entry(head->prev, struct ath_buf, list);
1599 ath_dbg(common, ATH_DBG_QUEUE,
1600 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1602 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1603 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1604 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1607 list_splice_tail_init(head, &txq->axq_q);
1609 if (txq->axq_link) {
1610 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1611 ath_dbg(common, ATH_DBG_XMIT,
1612 "link[%u] (%p)=%llx (%p)\n",
1613 txq->axq_qnum, txq->axq_link,
1614 ito64(bf->bf_daddr), bf->bf_desc);
1618 txq->axq_link = bf_last->bf_desc;
1622 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1623 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1624 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1625 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1629 TX_STAT_INC(txq->axq_qnum, txstart);
1630 ath9k_hw_txstart(ah, txq->axq_qnum);
1635 if (bf_is_ampdu_not_probing(bf))
1636 txq->axq_ampdu_depth++;
1640 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1641 struct sk_buff *skb, struct ath_tx_control *txctl)
1643 struct ath_frame_info *fi = get_frame_info(skb);
1644 struct list_head bf_head;
1648 * Do not queue to h/w when any of the following conditions is true:
1649 * - there are pending frames in software queue
1650 * - the TID is currently paused for ADDBA/BAR request
1651 * - seqno is not within block-ack window
1652 * - h/w queue depth exceeds low water mark
1654 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1655 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1656 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1658 * Add this frame to software queue for scheduling later
1661 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1662 __skb_queue_tail(&tid->buf_q, skb);
1663 if (!txctl->an || !txctl->an->sleeping)
1664 ath_tx_queue_tid(txctl->txq, tid);
1668 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1672 bf->bf_state.bf_type = BUF_AMPDU;
1673 INIT_LIST_HEAD(&bf_head);
1674 list_add(&bf->list, &bf_head);
1676 /* Add sub-frame to BAW */
1677 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1679 /* Queue to h/w without aggregation */
1680 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1682 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1683 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1686 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1687 struct ath_atx_tid *tid, struct sk_buff *skb)
1689 struct ath_frame_info *fi = get_frame_info(skb);
1690 struct list_head bf_head;
1695 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1700 INIT_LIST_HEAD(&bf_head);
1701 list_add_tail(&bf->list, &bf_head);
1702 bf->bf_state.bf_type = 0;
1704 /* update starting sequence number for subsequent ADDBA request */
1706 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1709 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1710 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1711 TX_STAT_INC(txq->axq_qnum, queued);
1714 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1717 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1718 struct ieee80211_sta *sta = tx_info->control.sta;
1719 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1720 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1721 struct ath_frame_info *fi = get_frame_info(skb);
1722 struct ath_node *an = NULL;
1723 enum ath9k_key_type keytype;
1725 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1728 an = (struct ath_node *) sta->drv_priv;
1730 memset(fi, 0, sizeof(*fi));
1732 fi->keyix = hw_key->hw_key_idx;
1733 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1734 fi->keyix = an->ps_key;
1736 fi->keyix = ATH9K_TXKEYIX_INVALID;
1737 fi->keytype = keytype;
1738 fi->framelen = framelen;
1741 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1743 struct ath_hw *ah = sc->sc_ah;
1744 struct ath9k_channel *curchan = ah->curchan;
1745 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1746 (curchan->channelFlags & CHANNEL_5GHZ) &&
1747 (chainmask == 0x7) && (rate < 0x90))
1754 * Assign a descriptor (and sequence number if necessary,
1755 * and map buffer for DMA. Frees skb on error
1757 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1758 struct ath_txq *txq,
1759 struct ath_atx_tid *tid,
1760 struct sk_buff *skb)
1762 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1763 struct ath_frame_info *fi = get_frame_info(skb);
1764 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1768 bf = ath_tx_get_buffer(sc);
1770 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1774 ATH_TXBUF_RESET(bf);
1777 seqno = tid->seq_next;
1778 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1779 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1780 bf->bf_state.seqno = seqno;
1785 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1786 skb->len, DMA_TO_DEVICE);
1787 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1789 bf->bf_buf_addr = 0;
1790 ath_err(ath9k_hw_common(sc->sc_ah),
1791 "dma_mapping_error() on TX\n");
1792 ath_tx_return_buffer(sc, bf);
1801 dev_kfree_skb_any(skb);
1805 /* FIXME: tx power */
1806 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1807 struct ath_tx_control *txctl)
1809 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1810 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1811 struct ath_atx_tid *tid = NULL;
1815 spin_lock_bh(&txctl->txq->axq_lock);
1816 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1817 ieee80211_is_data_qos(hdr->frame_control)) {
1818 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1819 IEEE80211_QOS_CTL_TID_MASK;
1820 tid = ATH_AN_2_TID(txctl->an, tidno);
1822 WARN_ON(tid->ac->txq != txctl->txq);
1825 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1827 * Try aggregation if it's a unicast data frame
1828 * and the destination is HT capable.
1830 ath_tx_send_ampdu(sc, tid, skb, txctl);
1832 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1836 bf->bf_state.bfs_paprd = txctl->paprd;
1839 bf->bf_state.bfs_paprd_timestamp = jiffies;
1841 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1845 spin_unlock_bh(&txctl->txq->axq_lock);
1848 /* Upon failure caller should free skb */
1849 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1850 struct ath_tx_control *txctl)
1852 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1853 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1854 struct ieee80211_sta *sta = info->control.sta;
1855 struct ieee80211_vif *vif = info->control.vif;
1856 struct ath_softc *sc = hw->priv;
1857 struct ath_txq *txq = txctl->txq;
1858 int padpos, padsize;
1859 int frmlen = skb->len + FCS_LEN;
1862 /* NOTE: sta can be NULL according to net/mac80211.h */
1864 txctl->an = (struct ath_node *)sta->drv_priv;
1866 if (info->control.hw_key)
1867 frmlen += info->control.hw_key->icv_len;
1870 * As a temporary workaround, assign seq# here; this will likely need
1871 * to be cleaned up to work better with Beacon transmission and virtual
1874 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1875 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1876 sc->tx.seq_no += 0x10;
1877 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1878 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1881 /* Add the padding after the header if this is not already done */
1882 padpos = ath9k_cmn_padpos(hdr->frame_control);
1883 padsize = padpos & 3;
1884 if (padsize && skb->len > padpos) {
1885 if (skb_headroom(skb) < padsize)
1888 skb_push(skb, padsize);
1889 memmove(skb->data, skb->data + padsize, padpos);
1890 hdr = (struct ieee80211_hdr *) skb->data;
1893 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1894 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1895 !ieee80211_is_data(hdr->frame_control))
1896 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1898 setup_frame_info(hw, skb, frmlen);
1901 * At this point, the vif, hw_key and sta pointers in the tx control
1902 * info are no longer valid (overwritten by the ath_frame_info data.
1905 q = skb_get_queue_mapping(skb);
1906 spin_lock_bh(&txq->axq_lock);
1907 if (txq == sc->tx.txq_map[q] &&
1908 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1909 ieee80211_stop_queue(sc->hw, q);
1912 spin_unlock_bh(&txq->axq_lock);
1914 ath_tx_start_dma(sc, skb, txctl);
1922 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1923 int tx_flags, struct ath_txq *txq)
1925 struct ieee80211_hw *hw = sc->hw;
1926 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1927 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1928 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1929 int q, padpos, padsize;
1931 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1933 if (tx_flags & ATH_TX_BAR)
1934 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1936 if (!(tx_flags & ATH_TX_ERROR))
1937 /* Frame was ACKed */
1938 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1940 padpos = ath9k_cmn_padpos(hdr->frame_control);
1941 padsize = padpos & 3;
1942 if (padsize && skb->len>padpos+padsize) {
1944 * Remove MAC header padding before giving the frame back to
1947 memmove(skb->data + padsize, skb->data, padpos);
1948 skb_pull(skb, padsize);
1951 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1952 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1953 ath_dbg(common, ATH_DBG_PS,
1954 "Going back to sleep after having received TX status (0x%lx)\n",
1955 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1957 PS_WAIT_FOR_PSPOLL_DATA |
1958 PS_WAIT_FOR_TX_ACK));
1961 q = skb_get_queue_mapping(skb);
1962 if (txq == sc->tx.txq_map[q]) {
1963 spin_lock_bh(&txq->axq_lock);
1964 if (WARN_ON(--txq->pending_frames < 0))
1965 txq->pending_frames = 0;
1967 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1968 ieee80211_wake_queue(sc->hw, q);
1971 spin_unlock_bh(&txq->axq_lock);
1974 ieee80211_tx_status(hw, skb);
1977 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1978 struct ath_txq *txq, struct list_head *bf_q,
1979 struct ath_tx_status *ts, int txok, int sendbar)
1981 struct sk_buff *skb = bf->bf_mpdu;
1982 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1983 unsigned long flags;
1987 tx_flags = ATH_TX_BAR;
1990 tx_flags |= ATH_TX_ERROR;
1992 if (ts->ts_status & ATH9K_TXERR_FILT)
1993 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1995 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1996 bf->bf_buf_addr = 0;
1998 if (bf->bf_state.bfs_paprd) {
1999 if (time_after(jiffies,
2000 bf->bf_state.bfs_paprd_timestamp +
2001 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2002 dev_kfree_skb_any(skb);
2004 complete(&sc->paprd_complete);
2006 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2007 ath_tx_complete(sc, skb, tx_flags, txq);
2009 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2010 * accidentally reference it later.
2015 * Return the list of ath_buf of this mpdu to free queue
2017 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2018 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2019 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2022 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2023 struct ath_tx_status *ts, int nframes, int nbad,
2026 struct sk_buff *skb = bf->bf_mpdu;
2027 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2028 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2029 struct ieee80211_hw *hw = sc->hw;
2030 struct ath_hw *ah = sc->sc_ah;
2034 tx_info->status.ack_signal = ts->ts_rssi;
2036 tx_rateindex = ts->ts_rateindex;
2037 WARN_ON(tx_rateindex >= hw->max_rates);
2039 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2040 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2042 BUG_ON(nbad > nframes);
2044 tx_info->status.ampdu_len = nframes;
2045 tx_info->status.ampdu_ack_len = nframes - nbad;
2047 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2048 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2050 * If an underrun error is seen assume it as an excessive
2051 * retry only if max frame trigger level has been reached
2052 * (2 KB for single stream, and 4 KB for dual stream).
2053 * Adjust the long retry as if the frame was tried
2054 * hw->max_rate_tries times to affect how rate control updates
2055 * PER for the failed rate.
2056 * In case of congestion on the bus penalizing this type of
2057 * underruns should help hardware actually transmit new frames
2058 * successfully by eventually preferring slower rates.
2059 * This itself should also alleviate congestion on the bus.
2061 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2062 ATH9K_TX_DELIM_UNDERRUN)) &&
2063 ieee80211_is_data(hdr->frame_control) &&
2064 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2065 tx_info->status.rates[tx_rateindex].count =
2069 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2070 tx_info->status.rates[i].count = 0;
2071 tx_info->status.rates[i].idx = -1;
2074 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2077 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2078 struct ath_tx_status *ts, struct ath_buf *bf,
2079 struct list_head *bf_head)
2080 __releases(txq->axq_lock)
2081 __acquires(txq->axq_lock)
2086 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2087 txq->axq_tx_inprogress = false;
2088 if (bf_is_ampdu_not_probing(bf))
2089 txq->axq_ampdu_depth--;
2091 spin_unlock_bh(&txq->axq_lock);
2093 if (!bf_isampdu(bf)) {
2094 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2095 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2097 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2099 spin_lock_bh(&txq->axq_lock);
2101 if (sc->sc_flags & SC_OP_TXAGGR)
2102 ath_txq_schedule(sc, txq);
2105 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2107 struct ath_hw *ah = sc->sc_ah;
2108 struct ath_common *common = ath9k_hw_common(ah);
2109 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2110 struct list_head bf_head;
2111 struct ath_desc *ds;
2112 struct ath_tx_status ts;
2115 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2116 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2119 spin_lock_bh(&txq->axq_lock);
2121 if (work_pending(&sc->hw_reset_work))
2124 if (list_empty(&txq->axq_q)) {
2125 txq->axq_link = NULL;
2126 if (sc->sc_flags & SC_OP_TXAGGR)
2127 ath_txq_schedule(sc, txq);
2130 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2133 * There is a race condition that a BH gets scheduled
2134 * after sw writes TxE and before hw re-load the last
2135 * descriptor to get the newly chained one.
2136 * Software must keep the last DONE descriptor as a
2137 * holding descriptor - software does so by marking
2138 * it with the STALE flag.
2143 if (list_is_last(&bf_held->list, &txq->axq_q))
2146 bf = list_entry(bf_held->list.next, struct ath_buf,
2150 lastbf = bf->bf_lastbf;
2151 ds = lastbf->bf_desc;
2153 memset(&ts, 0, sizeof(ts));
2154 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2155 if (status == -EINPROGRESS)
2158 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2161 * Remove ath_buf's of the same transmit unit from txq,
2162 * however leave the last descriptor back as the holding
2163 * descriptor for hw.
2165 lastbf->bf_stale = true;
2166 INIT_LIST_HEAD(&bf_head);
2167 if (!list_is_singular(&lastbf->list))
2168 list_cut_position(&bf_head,
2169 &txq->axq_q, lastbf->list.prev);
2172 list_del(&bf_held->list);
2173 ath_tx_return_buffer(sc, bf_held);
2176 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2178 spin_unlock_bh(&txq->axq_lock);
2181 static void ath_tx_complete_poll_work(struct work_struct *work)
2183 struct ath_softc *sc = container_of(work, struct ath_softc,
2184 tx_complete_work.work);
2185 struct ath_txq *txq;
2187 bool needreset = false;
2188 #ifdef CONFIG_ATH9K_DEBUGFS
2189 sc->tx_complete_poll_work_seen++;
2192 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2193 if (ATH_TXQ_SETUP(sc, i)) {
2194 txq = &sc->tx.txq[i];
2195 spin_lock_bh(&txq->axq_lock);
2196 if (txq->axq_depth) {
2197 if (txq->axq_tx_inprogress) {
2199 spin_unlock_bh(&txq->axq_lock);
2202 txq->axq_tx_inprogress = true;
2205 spin_unlock_bh(&txq->axq_lock);
2209 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2210 "tx hung, resetting the chip\n");
2211 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2212 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2215 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2216 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2221 void ath_tx_tasklet(struct ath_softc *sc)
2224 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2226 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2228 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2229 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2230 ath_tx_processq(sc, &sc->tx.txq[i]);
2234 void ath_tx_edma_tasklet(struct ath_softc *sc)
2236 struct ath_tx_status ts;
2237 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2238 struct ath_hw *ah = sc->sc_ah;
2239 struct ath_txq *txq;
2240 struct ath_buf *bf, *lastbf;
2241 struct list_head bf_head;
2245 if (work_pending(&sc->hw_reset_work))
2248 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2249 if (status == -EINPROGRESS)
2251 if (status == -EIO) {
2252 ath_dbg(common, ATH_DBG_XMIT,
2253 "Error processing tx status\n");
2257 /* Skip beacon completions */
2258 if (ts.qid == sc->beacon.beaconq)
2261 txq = &sc->tx.txq[ts.qid];
2263 spin_lock_bh(&txq->axq_lock);
2265 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2266 spin_unlock_bh(&txq->axq_lock);
2270 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2271 struct ath_buf, list);
2272 lastbf = bf->bf_lastbf;
2274 INIT_LIST_HEAD(&bf_head);
2275 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2278 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2279 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2281 if (!list_empty(&txq->axq_q)) {
2282 struct list_head bf_q;
2284 INIT_LIST_HEAD(&bf_q);
2285 txq->axq_link = NULL;
2286 list_splice_tail_init(&txq->axq_q, &bf_q);
2287 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2291 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2292 spin_unlock_bh(&txq->axq_lock);
2300 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2302 struct ath_descdma *dd = &sc->txsdma;
2303 u8 txs_len = sc->sc_ah->caps.txs_len;
2305 dd->dd_desc_len = size * txs_len;
2306 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2307 &dd->dd_desc_paddr, GFP_KERNEL);
2314 static int ath_tx_edma_init(struct ath_softc *sc)
2318 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2320 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2321 sc->txsdma.dd_desc_paddr,
2322 ATH_TXSTATUS_RING_SIZE);
2327 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2329 struct ath_descdma *dd = &sc->txsdma;
2331 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2335 int ath_tx_init(struct ath_softc *sc, int nbufs)
2337 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2340 spin_lock_init(&sc->tx.txbuflock);
2342 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2346 "Failed to allocate tx descriptors: %d\n", error);
2350 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2351 "beacon", ATH_BCBUF, 1, 1);
2354 "Failed to allocate beacon descriptors: %d\n", error);
2358 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2360 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2361 error = ath_tx_edma_init(sc);
2373 void ath_tx_cleanup(struct ath_softc *sc)
2375 if (sc->beacon.bdma.dd_desc_len != 0)
2376 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2378 if (sc->tx.txdma.dd_desc_len != 0)
2379 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2381 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2382 ath_tx_edma_cleanup(sc);
2385 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2387 struct ath_atx_tid *tid;
2388 struct ath_atx_ac *ac;
2391 for (tidno = 0, tid = &an->tid[tidno];
2392 tidno < WME_NUM_TID;
2396 tid->seq_start = tid->seq_next = 0;
2397 tid->baw_size = WME_MAX_BA;
2398 tid->baw_head = tid->baw_tail = 0;
2400 tid->paused = false;
2401 tid->state &= ~AGGR_CLEANUP;
2402 __skb_queue_head_init(&tid->buf_q);
2403 acno = TID_TO_WME_AC(tidno);
2404 tid->ac = &an->ac[acno];
2405 tid->state &= ~AGGR_ADDBA_COMPLETE;
2406 tid->state &= ~AGGR_ADDBA_PROGRESS;
2409 for (acno = 0, ac = &an->ac[acno];
2410 acno < WME_NUM_AC; acno++, ac++) {
2412 ac->txq = sc->tx.txq_map[acno];
2413 INIT_LIST_HEAD(&ac->tid_q);
2417 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2419 struct ath_atx_ac *ac;
2420 struct ath_atx_tid *tid;
2421 struct ath_txq *txq;
2424 for (tidno = 0, tid = &an->tid[tidno];
2425 tidno < WME_NUM_TID; tidno++, tid++) {
2430 spin_lock_bh(&txq->axq_lock);
2433 list_del(&tid->list);
2438 list_del(&ac->list);
2439 tid->ac->sched = false;
2442 ath_tid_drain(sc, txq, tid);
2443 tid->state &= ~AGGR_ADDBA_COMPLETE;
2444 tid->state &= ~AGGR_CLEANUP;
2446 spin_unlock_bh(&txq->axq_lock);