2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
63 struct list_head *bf_q,
64 int txok, int sendbar);
65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
66 struct list_head *head);
67 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
68 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
70 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
71 int nbad, int txok, bool update_rc);
73 /*********************/
74 /* Aggregation logic */
75 /*********************/
77 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
79 struct ath_atx_ac *ac = tid->ac;
88 list_add_tail(&tid->list, &ac->tid_q);
94 list_add_tail(&ac->list, &txq->axq_acq);
97 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
99 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
101 spin_lock_bh(&txq->axq_lock);
103 spin_unlock_bh(&txq->axq_lock);
106 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
110 BUG_ON(tid->paused <= 0);
111 spin_lock_bh(&txq->axq_lock);
118 if (list_empty(&tid->buf_q))
121 ath_tx_queue_tid(txq, tid);
122 ath_txq_schedule(sc, txq);
124 spin_unlock_bh(&txq->axq_lock);
127 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
131 struct list_head bf_head;
132 INIT_LIST_HEAD(&bf_head);
134 BUG_ON(tid->paused <= 0);
135 spin_lock_bh(&txq->axq_lock);
139 if (tid->paused > 0) {
140 spin_unlock_bh(&txq->axq_lock);
144 while (!list_empty(&tid->buf_q)) {
145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
146 BUG_ON(bf_isretried(bf));
147 list_move_tail(&bf->list, &bf_head);
148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
151 spin_unlock_bh(&txq->axq_lock);
154 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
159 index = ATH_BA_INDEX(tid->seq_start, seqno);
160 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
162 tid->tx_buf[cindex] = NULL;
164 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
165 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
166 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
170 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
175 if (bf_isretried(bf))
178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
181 BUG_ON(tid->tx_buf[cindex] != NULL);
182 tid->tx_buf[cindex] = bf;
184 if (index >= ((tid->baw_tail - tid->baw_head) &
185 (ATH_TID_MAX_BUFS - 1))) {
186 tid->baw_tail = cindex;
187 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
192 * TODO: For frame(s) that are in the retry state, we will reuse the
193 * sequence number(s) without setting the retry bit. The
194 * alternative is to give up on these and BAR the receiver's window
197 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
198 struct ath_atx_tid *tid)
202 struct list_head bf_head;
203 INIT_LIST_HEAD(&bf_head);
206 if (list_empty(&tid->buf_q))
209 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
210 list_move_tail(&bf->list, &bf_head);
212 if (bf_isretried(bf))
213 ath_tx_update_baw(sc, tid, bf->bf_seqno);
215 spin_unlock(&txq->axq_lock);
216 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
217 spin_lock(&txq->axq_lock);
220 tid->seq_next = tid->seq_start;
221 tid->baw_tail = tid->baw_head;
224 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
228 struct ieee80211_hdr *hdr;
230 bf->bf_state.bf_type |= BUF_RETRY;
232 TX_STAT_INC(txq->axq_qnum, a_retries);
235 hdr = (struct ieee80211_hdr *)skb->data;
236 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
239 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
243 spin_lock_bh(&sc->tx.txbuflock);
244 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
245 spin_unlock_bh(&sc->tx.txbuflock);
248 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
249 list_del(&tbf->list);
250 spin_unlock_bh(&sc->tx.txbuflock);
252 ATH_TXBUF_RESET(tbf);
254 tbf->bf_mpdu = bf->bf_mpdu;
255 tbf->bf_buf_addr = bf->bf_buf_addr;
256 *(tbf->bf_desc) = *(bf->bf_desc);
257 tbf->bf_state = bf->bf_state;
258 tbf->bf_dmacontext = bf->bf_dmacontext;
263 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
264 struct ath_buf *bf, struct list_head *bf_q,
267 struct ath_node *an = NULL;
269 struct ieee80211_sta *sta;
270 struct ieee80211_hdr *hdr;
271 struct ath_atx_tid *tid = NULL;
272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
273 struct ath_desc *ds = bf_last->bf_desc;
274 struct list_head bf_head, bf_pending;
275 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
276 u32 ba[WME_BA_BMP_SIZE >> 5];
277 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
278 bool rc_update = true;
281 hdr = (struct ieee80211_hdr *)skb->data;
285 /* XXX: use ieee80211_find_sta! */
286 sta = ieee80211_find_sta_by_hw(sc->hw, hdr->addr1);
292 an = (struct ath_node *)sta->drv_priv;
293 tid = ATH_AN_2_TID(an, bf->bf_tidno);
295 isaggr = bf_isaggr(bf);
296 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
298 if (isaggr && txok) {
299 if (ATH_DS_TX_BA(ds)) {
300 seq_st = ATH_DS_BA_SEQ(ds);
301 memcpy(ba, ATH_DS_BA_BITMAP(ds),
302 WME_BA_BMP_SIZE >> 3);
305 * AR5416 can become deaf/mute when BA
306 * issue happens. Chip needs to be reset.
307 * But AP code may have sychronization issues
308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now.
311 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
316 INIT_LIST_HEAD(&bf_pending);
317 INIT_LIST_HEAD(&bf_head);
319 nbad = ath_tx_num_badfrms(sc, bf, txok);
321 txfail = txpending = 0;
322 bf_next = bf->bf_next;
324 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
325 /* transmit completion, subframe is
326 * acked by block ack */
328 } else if (!isaggr && txok) {
329 /* transmit completion */
332 if (!(tid->state & AGGR_CLEANUP) &&
333 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
334 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
335 ath_tx_set_retry(sc, txq, bf);
338 bf->bf_state.bf_type |= BUF_XRETRY;
345 * cleanup in progress, just fail
346 * the un-acked sub-frames
352 if (bf_next == NULL) {
354 * Make sure the last desc is reclaimed if it
355 * not a holding desc.
357 if (!bf_last->bf_stale)
358 list_move_tail(&bf->list, &bf_head);
360 INIT_LIST_HEAD(&bf_head);
362 BUG_ON(list_empty(bf_q));
363 list_move_tail(&bf->list, &bf_head);
368 * complete the acked-ones/xretried ones; update
371 spin_lock_bh(&txq->axq_lock);
372 ath_tx_update_baw(sc, tid, bf->bf_seqno);
373 spin_unlock_bh(&txq->axq_lock);
375 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
376 ath_tx_rc_status(bf, ds, nbad, txok, true);
379 ath_tx_rc_status(bf, ds, nbad, txok, false);
382 ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar);
384 /* retry the un-acked ones */
385 if (bf->bf_next == NULL && bf_last->bf_stale) {
388 tbf = ath_clone_txbuf(sc, bf_last);
390 * Update tx baw and complete the frame with
391 * failed status if we run out of tx buf
394 spin_lock_bh(&txq->axq_lock);
395 ath_tx_update_baw(sc, tid,
397 spin_unlock_bh(&txq->axq_lock);
399 bf->bf_state.bf_type |= BUF_XRETRY;
400 ath_tx_rc_status(bf, ds, nbad,
402 ath_tx_complete_buf(sc, bf, txq,
407 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
408 list_add_tail(&tbf->list, &bf_head);
411 * Clear descriptor status words for
414 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
418 * Put this buffer to the temporary pending
419 * queue to retain ordering
421 list_splice_tail_init(&bf_head, &bf_pending);
427 if (tid->state & AGGR_CLEANUP) {
428 if (tid->baw_head == tid->baw_tail) {
429 tid->state &= ~AGGR_ADDBA_COMPLETE;
430 tid->state &= ~AGGR_CLEANUP;
432 /* send buffered frames as singles */
433 ath_tx_flush_tid(sc, tid);
439 /* prepend un-acked frames to the beginning of the pending frame queue */
440 if (!list_empty(&bf_pending)) {
441 spin_lock_bh(&txq->axq_lock);
442 list_splice(&bf_pending, &tid->buf_q);
443 ath_tx_queue_tid(txq, tid);
444 spin_unlock_bh(&txq->axq_lock);
450 ath_reset(sc, false);
453 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
454 struct ath_atx_tid *tid)
456 const struct ath_rate_table *rate_table = sc->cur_rate_table;
458 struct ieee80211_tx_info *tx_info;
459 struct ieee80211_tx_rate *rates;
460 struct ath_tx_info_priv *tx_info_priv;
461 u32 max_4ms_framelen, frmlen;
462 u16 aggr_limit, legacy = 0;
466 tx_info = IEEE80211_SKB_CB(skb);
467 rates = tx_info->control.rates;
468 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
471 * Find the lowest frame length among the rate series that will have a
472 * 4ms transmit duration.
473 * TODO - TXOP limit needs to be considered.
475 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
477 for (i = 0; i < 4; i++) {
478 if (rates[i].count) {
479 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
484 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
485 max_4ms_framelen = min(max_4ms_framelen, frmlen);
490 * limit aggregate size by the minimum rate if rate selected is
491 * not a probe rate, if rate selected is a probe rate then
492 * avoid aggregation of this packet.
494 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
497 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
498 aggr_limit = min((max_4ms_framelen * 3) / 8,
499 (u32)ATH_AMPDU_LIMIT_MAX);
501 aggr_limit = min(max_4ms_framelen,
502 (u32)ATH_AMPDU_LIMIT_MAX);
505 * h/w can accept aggregates upto 16 bit lengths (65535).
506 * The IE, however can hold upto 65536, which shows up here
507 * as zero. Ignore 65536 since we are constrained by hw.
509 if (tid->an->maxampdu)
510 aggr_limit = min(aggr_limit, tid->an->maxampdu);
516 * Returns the number of delimiters to be added to
517 * meet the minimum required mpdudensity.
519 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
520 struct ath_buf *bf, u16 frmlen)
522 const struct ath_rate_table *rt = sc->cur_rate_table;
523 struct sk_buff *skb = bf->bf_mpdu;
524 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
525 u32 nsymbits, nsymbols;
528 int width, half_gi, ndelim, mindelim;
530 /* Select standard number of delimiters based on frame length alone */
531 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
534 * If encryption enabled, hardware requires some more padding between
536 * TODO - this could be improved to be dependent on the rate.
537 * The hardware can keep up at lower rates, but not higher rates
539 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
540 ndelim += ATH_AGGR_ENCRYPTDELIM;
543 * Convert desired mpdu density from microeconds to bytes based
544 * on highest rate in rate series (i.e. first rate) to determine
545 * required minimum length for subframe. Take into account
546 * whether high rate is 20 or 40Mhz and half or full GI.
548 * If there is no mpdu density restriction, no further calculation
552 if (tid->an->mpdudensity == 0)
555 rix = tx_info->control.rates[0].idx;
556 flags = tx_info->control.rates[0].flags;
557 rc = rt->info[rix].ratecode;
558 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
559 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
562 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
564 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
569 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
570 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
572 if (frmlen < minlen) {
573 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
574 ndelim = max(mindelim, ndelim);
580 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
582 struct ath_atx_tid *tid,
583 struct list_head *bf_q)
585 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
586 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
587 int rl = 0, nframes = 0, ndelim, prev_al = 0;
588 u16 aggr_limit = 0, al = 0, bpad = 0,
589 al_delta, h_baw = tid->baw_size / 2;
590 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
592 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
595 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
597 /* do not step over block-ack window */
598 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
599 status = ATH_AGGR_BAW_CLOSED;
604 aggr_limit = ath_lookup_rate(sc, bf, tid);
608 /* do not exceed aggregation limit */
609 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
612 (aggr_limit < (al + bpad + al_delta + prev_al))) {
613 status = ATH_AGGR_LIMITED;
617 /* do not exceed subframe limit */
618 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
619 status = ATH_AGGR_LIMITED;
624 /* add padding for previous frame to aggregation length */
625 al += bpad + al_delta;
628 * Get the delimiters needed to meet the MPDU
629 * density for this node.
631 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
632 bpad = PADBYTES(al_delta) + (ndelim << 2);
635 bf->bf_desc->ds_link = 0;
637 /* link buffers of this frame to the aggregate */
638 ath_tx_addto_baw(sc, tid, bf);
639 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
640 list_move_tail(&bf->list, bf_q);
642 bf_prev->bf_next = bf;
643 bf_prev->bf_desc->ds_link = bf->bf_daddr;
647 } while (!list_empty(&tid->buf_q));
649 bf_first->bf_al = al;
650 bf_first->bf_nframes = nframes;
656 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
657 struct ath_atx_tid *tid)
660 enum ATH_AGGR_STATUS status;
661 struct list_head bf_q;
664 if (list_empty(&tid->buf_q))
667 INIT_LIST_HEAD(&bf_q);
669 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
672 * no frames picked up to be aggregated;
673 * block-ack window is not open.
675 if (list_empty(&bf_q))
678 bf = list_first_entry(&bf_q, struct ath_buf, list);
679 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
681 /* if only one frame, send as non-aggregate */
682 if (bf->bf_nframes == 1) {
683 bf->bf_state.bf_type &= ~BUF_AGGR;
684 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
685 ath_buf_set_rate(sc, bf);
686 ath_tx_txqaddbuf(sc, txq, &bf_q);
690 /* setup first desc of aggregate */
691 bf->bf_state.bf_type |= BUF_AGGR;
692 ath_buf_set_rate(sc, bf);
693 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
695 /* anchor last desc of aggregate */
696 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
698 txq->axq_aggr_depth++;
699 ath_tx_txqaddbuf(sc, txq, &bf_q);
700 TX_STAT_INC(txq->axq_qnum, a_aggr);
702 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
703 status != ATH_AGGR_BAW_CLOSED);
706 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
709 struct ath_atx_tid *txtid;
712 an = (struct ath_node *)sta->drv_priv;
713 txtid = ATH_AN_2_TID(an, tid);
714 txtid->state |= AGGR_ADDBA_PROGRESS;
715 ath_tx_pause_tid(sc, txtid);
716 *ssn = txtid->seq_start;
719 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
721 struct ath_node *an = (struct ath_node *)sta->drv_priv;
722 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
723 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
725 struct list_head bf_head;
726 INIT_LIST_HEAD(&bf_head);
728 if (txtid->state & AGGR_CLEANUP)
731 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
732 txtid->state &= ~AGGR_ADDBA_PROGRESS;
736 ath_tx_pause_tid(sc, txtid);
738 /* drop all software retried frames and mark this TID */
739 spin_lock_bh(&txq->axq_lock);
740 while (!list_empty(&txtid->buf_q)) {
741 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
742 if (!bf_isretried(bf)) {
744 * NB: it's based on the assumption that
745 * software retried frame will always stay
746 * at the head of software queue.
750 list_move_tail(&bf->list, &bf_head);
751 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
752 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
754 spin_unlock_bh(&txq->axq_lock);
756 if (txtid->baw_head != txtid->baw_tail) {
757 txtid->state |= AGGR_CLEANUP;
759 txtid->state &= ~AGGR_ADDBA_COMPLETE;
760 ath_tx_flush_tid(sc, txtid);
764 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
766 struct ath_atx_tid *txtid;
769 an = (struct ath_node *)sta->drv_priv;
771 if (sc->sc_flags & SC_OP_TXAGGR) {
772 txtid = ATH_AN_2_TID(an, tid);
774 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
775 txtid->state |= AGGR_ADDBA_COMPLETE;
776 txtid->state &= ~AGGR_ADDBA_PROGRESS;
777 ath_tx_resume_tid(sc, txtid);
781 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
783 struct ath_atx_tid *txtid;
785 if (!(sc->sc_flags & SC_OP_TXAGGR))
788 txtid = ATH_AN_2_TID(an, tidno);
790 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
795 /********************/
796 /* Queue Management */
797 /********************/
799 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
802 struct ath_atx_ac *ac, *ac_tmp;
803 struct ath_atx_tid *tid, *tid_tmp;
805 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
808 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
809 list_del(&tid->list);
811 ath_tid_drain(sc, txq, tid);
816 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
818 struct ath_hw *ah = sc->sc_ah;
819 struct ath_common *common = ath9k_hw_common(ah);
820 struct ath9k_tx_queue_info qi;
823 memset(&qi, 0, sizeof(qi));
824 qi.tqi_subtype = subtype;
825 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
826 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
827 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
828 qi.tqi_physCompBuf = 0;
831 * Enable interrupts only for EOL and DESC conditions.
832 * We mark tx descriptors to receive a DESC interrupt
833 * when a tx queue gets deep; otherwise waiting for the
834 * EOL to reap descriptors. Note that this is done to
835 * reduce interrupt load and this only defers reaping
836 * descriptors, never transmitting frames. Aside from
837 * reducing interrupts this also permits more concurrency.
838 * The only potential downside is if the tx queue backs
839 * up in which case the top half of the kernel may backup
840 * due to a lack of tx descriptors.
842 * The UAPSD queue is an exception, since we take a desc-
843 * based intr on the EOSP frames.
845 if (qtype == ATH9K_TX_QUEUE_UAPSD)
846 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
848 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
849 TXQ_FLAG_TXDESCINT_ENABLE;
850 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
853 * NB: don't print a message, this happens
854 * normally on parts with too few tx queues
858 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
859 ath_print(common, ATH_DBG_FATAL,
860 "qnum %u out of range, max %u!\n",
861 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
862 ath9k_hw_releasetxqueue(ah, qnum);
865 if (!ATH_TXQ_SETUP(sc, qnum)) {
866 struct ath_txq *txq = &sc->tx.txq[qnum];
868 txq->axq_qnum = qnum;
869 txq->axq_link = NULL;
870 INIT_LIST_HEAD(&txq->axq_q);
871 INIT_LIST_HEAD(&txq->axq_acq);
872 spin_lock_init(&txq->axq_lock);
874 txq->axq_aggr_depth = 0;
875 txq->axq_linkbuf = NULL;
876 txq->axq_tx_inprogress = false;
877 sc->tx.txqsetup |= 1<<qnum;
879 return &sc->tx.txq[qnum];
882 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
887 case ATH9K_TX_QUEUE_DATA:
888 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
889 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
890 "HAL AC %u out of range, max %zu!\n",
891 haltype, ARRAY_SIZE(sc->tx.hwq_map));
894 qnum = sc->tx.hwq_map[haltype];
896 case ATH9K_TX_QUEUE_BEACON:
897 qnum = sc->beacon.beaconq;
899 case ATH9K_TX_QUEUE_CAB:
900 qnum = sc->beacon.cabq->axq_qnum;
908 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
910 struct ath_txq *txq = NULL;
913 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
914 txq = &sc->tx.txq[qnum];
916 spin_lock_bh(&txq->axq_lock);
918 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
919 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
920 "TX queue: %d is full, depth: %d\n",
921 qnum, txq->axq_depth);
922 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
924 spin_unlock_bh(&txq->axq_lock);
928 spin_unlock_bh(&txq->axq_lock);
933 int ath_txq_update(struct ath_softc *sc, int qnum,
934 struct ath9k_tx_queue_info *qinfo)
936 struct ath_hw *ah = sc->sc_ah;
938 struct ath9k_tx_queue_info qi;
940 if (qnum == sc->beacon.beaconq) {
942 * XXX: for beacon queue, we just save the parameter.
943 * It will be picked up by ath_beaconq_config when
946 sc->beacon.beacon_qi = *qinfo;
950 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
952 ath9k_hw_get_txq_props(ah, qnum, &qi);
953 qi.tqi_aifs = qinfo->tqi_aifs;
954 qi.tqi_cwmin = qinfo->tqi_cwmin;
955 qi.tqi_cwmax = qinfo->tqi_cwmax;
956 qi.tqi_burstTime = qinfo->tqi_burstTime;
957 qi.tqi_readyTime = qinfo->tqi_readyTime;
959 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
960 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
961 "Unable to update hardware queue %u!\n", qnum);
964 ath9k_hw_resettxqueue(ah, qnum);
970 int ath_cabq_update(struct ath_softc *sc)
972 struct ath9k_tx_queue_info qi;
973 int qnum = sc->beacon.cabq->axq_qnum;
975 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
977 * Ensure the readytime % is within the bounds.
979 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
980 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
981 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
982 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
984 qi.tqi_readyTime = (sc->beacon_interval *
985 sc->config.cabqReadytime) / 100;
986 ath_txq_update(sc, qnum, &qi);
992 * Drain a given TX queue (could be Beacon or Data)
994 * This assumes output has been stopped and
995 * we do not need to block ath_tx_tasklet.
997 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
999 struct ath_buf *bf, *lastbf;
1000 struct list_head bf_head;
1002 INIT_LIST_HEAD(&bf_head);
1005 spin_lock_bh(&txq->axq_lock);
1007 if (list_empty(&txq->axq_q)) {
1008 txq->axq_link = NULL;
1009 txq->axq_linkbuf = NULL;
1010 spin_unlock_bh(&txq->axq_lock);
1014 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1017 list_del(&bf->list);
1018 spin_unlock_bh(&txq->axq_lock);
1020 spin_lock_bh(&sc->tx.txbuflock);
1021 list_add_tail(&bf->list, &sc->tx.txbuf);
1022 spin_unlock_bh(&sc->tx.txbuflock);
1026 lastbf = bf->bf_lastbf;
1028 lastbf->bf_desc->ds_txstat.ts_flags =
1029 ATH9K_TX_SW_ABORTED;
1031 /* remove ath_buf's of the same mpdu from txq */
1032 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1035 spin_unlock_bh(&txq->axq_lock);
1038 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1040 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
1043 spin_lock_bh(&txq->axq_lock);
1044 txq->axq_tx_inprogress = false;
1045 spin_unlock_bh(&txq->axq_lock);
1047 /* flush any pending frames if aggregation is enabled */
1048 if (sc->sc_flags & SC_OP_TXAGGR) {
1050 spin_lock_bh(&txq->axq_lock);
1051 ath_txq_drain_pending_buffers(sc, txq);
1052 spin_unlock_bh(&txq->axq_lock);
1057 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1059 struct ath_hw *ah = sc->sc_ah;
1060 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1061 struct ath_txq *txq;
1064 if (sc->sc_flags & SC_OP_INVALID)
1067 /* Stop beacon queue */
1068 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1070 /* Stop data queues */
1071 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1072 if (ATH_TXQ_SETUP(sc, i)) {
1073 txq = &sc->tx.txq[i];
1074 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1075 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1082 ath_print(common, ATH_DBG_XMIT,
1083 "Unable to stop TxDMA. Reset HAL!\n");
1085 spin_lock_bh(&sc->sc_resetlock);
1086 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1088 ath_print(common, ATH_DBG_FATAL,
1089 "Unable to reset hardware; reset status %d\n",
1091 spin_unlock_bh(&sc->sc_resetlock);
1094 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1095 if (ATH_TXQ_SETUP(sc, i))
1096 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1100 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1102 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1103 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1106 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1108 struct ath_atx_ac *ac;
1109 struct ath_atx_tid *tid;
1111 if (list_empty(&txq->axq_acq))
1114 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1115 list_del(&ac->list);
1119 if (list_empty(&ac->tid_q))
1122 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1123 list_del(&tid->list);
1129 ath_tx_sched_aggr(sc, txq, tid);
1132 * add tid to round-robin queue if more frames
1133 * are pending for the tid
1135 if (!list_empty(&tid->buf_q))
1136 ath_tx_queue_tid(txq, tid);
1139 } while (!list_empty(&ac->tid_q));
1141 if (!list_empty(&ac->tid_q)) {
1144 list_add_tail(&ac->list, &txq->axq_acq);
1149 int ath_tx_setup(struct ath_softc *sc, int haltype)
1151 struct ath_txq *txq;
1153 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1154 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1155 "HAL AC %u out of range, max %zu!\n",
1156 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1159 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1161 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1172 * Insert a chain of ath_buf (descriptors) on a txq and
1173 * assume the descriptors are already chained together by caller.
1175 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1176 struct list_head *head)
1178 struct ath_hw *ah = sc->sc_ah;
1179 struct ath_common *common = ath9k_hw_common(ah);
1183 * Insert the frame on the outbound list and
1184 * pass it on to the hardware.
1187 if (list_empty(head))
1190 bf = list_first_entry(head, struct ath_buf, list);
1192 list_splice_tail_init(head, &txq->axq_q);
1194 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1196 ath_print(common, ATH_DBG_QUEUE,
1197 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1199 if (txq->axq_link == NULL) {
1200 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1201 ath_print(common, ATH_DBG_XMIT,
1202 "TXDP[%u] = %llx (%p)\n",
1203 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1205 *txq->axq_link = bf->bf_daddr;
1206 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1207 txq->axq_qnum, txq->axq_link,
1208 ito64(bf->bf_daddr), bf->bf_desc);
1210 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1211 ath9k_hw_txstart(ah, txq->axq_qnum);
1214 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1216 struct ath_buf *bf = NULL;
1218 spin_lock_bh(&sc->tx.txbuflock);
1220 if (unlikely(list_empty(&sc->tx.txbuf))) {
1221 spin_unlock_bh(&sc->tx.txbuflock);
1225 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1226 list_del(&bf->list);
1228 spin_unlock_bh(&sc->tx.txbuflock);
1233 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1234 struct list_head *bf_head,
1235 struct ath_tx_control *txctl)
1239 bf = list_first_entry(bf_head, struct ath_buf, list);
1240 bf->bf_state.bf_type |= BUF_AMPDU;
1241 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1244 * Do not queue to h/w when any of the following conditions is true:
1245 * - there are pending frames in software queue
1246 * - the TID is currently paused for ADDBA/BAR request
1247 * - seqno is not within block-ack window
1248 * - h/w queue depth exceeds low water mark
1250 if (!list_empty(&tid->buf_q) || tid->paused ||
1251 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1252 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1254 * Add this frame to software queue for scheduling later
1257 list_move_tail(&bf->list, &tid->buf_q);
1258 ath_tx_queue_tid(txctl->txq, tid);
1262 /* Add sub-frame to BAW */
1263 ath_tx_addto_baw(sc, tid, bf);
1265 /* Queue to h/w without aggregation */
1268 ath_buf_set_rate(sc, bf);
1269 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1272 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1273 struct ath_atx_tid *tid,
1274 struct list_head *bf_head)
1278 bf = list_first_entry(bf_head, struct ath_buf, list);
1279 bf->bf_state.bf_type &= ~BUF_AMPDU;
1281 /* update starting sequence number for subsequent ADDBA request */
1282 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1286 ath_buf_set_rate(sc, bf);
1287 ath_tx_txqaddbuf(sc, txq, bf_head);
1288 TX_STAT_INC(txq->axq_qnum, queued);
1291 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1292 struct list_head *bf_head)
1296 bf = list_first_entry(bf_head, struct ath_buf, list);
1300 ath_buf_set_rate(sc, bf);
1301 ath_tx_txqaddbuf(sc, txq, bf_head);
1302 TX_STAT_INC(txq->axq_qnum, queued);
1305 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1307 struct ieee80211_hdr *hdr;
1308 enum ath9k_pkt_type htype;
1311 hdr = (struct ieee80211_hdr *)skb->data;
1312 fc = hdr->frame_control;
1314 if (ieee80211_is_beacon(fc))
1315 htype = ATH9K_PKT_TYPE_BEACON;
1316 else if (ieee80211_is_probe_resp(fc))
1317 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1318 else if (ieee80211_is_atim(fc))
1319 htype = ATH9K_PKT_TYPE_ATIM;
1320 else if (ieee80211_is_pspoll(fc))
1321 htype = ATH9K_PKT_TYPE_PSPOLL;
1323 htype = ATH9K_PKT_TYPE_NORMAL;
1328 static bool is_pae(struct sk_buff *skb)
1330 struct ieee80211_hdr *hdr;
1333 hdr = (struct ieee80211_hdr *)skb->data;
1334 fc = hdr->frame_control;
1336 if (ieee80211_is_data(fc)) {
1337 if (ieee80211_is_nullfunc(fc) ||
1338 /* Port Access Entity (IEEE 802.1X) */
1339 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1347 static int get_hw_crypto_keytype(struct sk_buff *skb)
1349 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1351 if (tx_info->control.hw_key) {
1352 if (tx_info->control.hw_key->alg == ALG_WEP)
1353 return ATH9K_KEY_TYPE_WEP;
1354 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1355 return ATH9K_KEY_TYPE_TKIP;
1356 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1357 return ATH9K_KEY_TYPE_AES;
1360 return ATH9K_KEY_TYPE_CLEAR;
1363 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1366 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1367 struct ieee80211_hdr *hdr;
1368 struct ath_node *an;
1369 struct ath_atx_tid *tid;
1373 if (!tx_info->control.sta)
1376 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1377 hdr = (struct ieee80211_hdr *)skb->data;
1378 fc = hdr->frame_control;
1380 if (ieee80211_is_data_qos(fc)) {
1381 qc = ieee80211_get_qos_ctl(hdr);
1382 bf->bf_tidno = qc[0] & 0xf;
1386 * For HT capable stations, we save tidno for later use.
1387 * We also override seqno set by upper layer with the one
1388 * in tx aggregation state.
1390 * If fragmentation is on, the sequence number is
1391 * not overridden, since it has been
1392 * incremented by the fragmentation routine.
1394 * FIXME: check if the fragmentation threshold exceeds
1397 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1398 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1399 IEEE80211_SEQ_SEQ_SHIFT);
1400 bf->bf_seqno = tid->seq_next;
1401 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1404 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1405 struct ath_txq *txq)
1407 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1410 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1411 flags |= ATH9K_TXDESC_INTREQ;
1413 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1414 flags |= ATH9K_TXDESC_NOACK;
1421 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1422 * width - 0 for 20 MHz, 1 for 40 MHz
1423 * half_gi - to use 4us v/s 3.6 us for symbol time
1425 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1426 int width, int half_gi, bool shortPreamble)
1428 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1429 u32 nbits, nsymbits, duration, nsymbols;
1431 int streams, pktlen;
1433 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1434 rc = rate_table->info[rix].ratecode;
1436 /* for legacy rates, use old function to compute packet duration */
1437 if (!IS_HT_RATE(rc))
1438 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1439 rix, shortPreamble);
1441 /* find number of symbols: PLCP + data */
1442 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1443 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1444 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1447 duration = SYMBOL_TIME(nsymbols);
1449 duration = SYMBOL_TIME_HALFGI(nsymbols);
1451 /* addup duration for legacy/ht training and signal fields */
1452 streams = HT_RC_2_STREAMS(rc);
1453 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1458 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1460 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1461 const struct ath_rate_table *rt = sc->cur_rate_table;
1462 struct ath9k_11n_rate_series series[4];
1463 struct sk_buff *skb;
1464 struct ieee80211_tx_info *tx_info;
1465 struct ieee80211_tx_rate *rates;
1466 struct ieee80211_hdr *hdr;
1468 u8 rix = 0, ctsrate = 0;
1471 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1474 tx_info = IEEE80211_SKB_CB(skb);
1475 rates = tx_info->control.rates;
1476 hdr = (struct ieee80211_hdr *)skb->data;
1477 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1480 * We check if Short Preamble is needed for the CTS rate by
1481 * checking the BSS's global flag.
1482 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1484 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1485 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1486 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1488 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1491 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1492 * Check the first rate in the series to decide whether RTS/CTS
1493 * or CTS-to-self has to be used.
1495 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1496 flags = ATH9K_TXDESC_CTSENA;
1497 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1498 flags = ATH9K_TXDESC_RTSENA;
1500 /* FIXME: Handle aggregation protection */
1501 if (sc->config.ath_aggr_prot &&
1502 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1503 flags = ATH9K_TXDESC_RTSENA;
1506 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1507 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1508 flags &= ~(ATH9K_TXDESC_RTSENA);
1510 for (i = 0; i < 4; i++) {
1511 if (!rates[i].count || (rates[i].idx < 0))
1515 series[i].Tries = rates[i].count;
1516 series[i].ChSel = common->tx_chainmask;
1518 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1519 series[i].Rate = rt->info[rix].ratecode |
1520 rt->info[rix].short_preamble;
1522 series[i].Rate = rt->info[rix].ratecode;
1524 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1525 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1526 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1527 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1528 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1529 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1531 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1532 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1533 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1534 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1537 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1538 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1539 bf->bf_lastbf->bf_desc,
1540 !is_pspoll, ctsrate,
1541 0, series, 4, flags);
1543 if (sc->config.ath_aggr_prot && flags)
1544 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1547 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1548 struct sk_buff *skb,
1549 struct ath_tx_control *txctl)
1551 struct ath_wiphy *aphy = hw->priv;
1552 struct ath_softc *sc = aphy->sc;
1553 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1554 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1555 struct ath_tx_info_priv *tx_info_priv;
1559 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1560 if (unlikely(!tx_info_priv))
1562 tx_info->rate_driver_data[0] = tx_info_priv;
1563 tx_info_priv->aphy = aphy;
1564 tx_info_priv->frame_type = txctl->frame_type;
1565 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1566 fc = hdr->frame_control;
1568 ATH_TXBUF_RESET(bf);
1570 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1572 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1573 bf->bf_state.bf_type |= BUF_HT;
1575 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1577 bf->bf_keytype = get_hw_crypto_keytype(skb);
1578 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1579 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1580 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1582 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1585 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1586 assign_aggr_tid_seqno(skb, bf);
1590 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1591 skb->len, DMA_TO_DEVICE);
1592 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1594 kfree(tx_info_priv);
1595 tx_info->rate_driver_data[0] = NULL;
1596 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1597 "dma_mapping_error() on TX\n");
1601 bf->bf_buf_addr = bf->bf_dmacontext;
1605 /* FIXME: tx power */
1606 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1607 struct ath_tx_control *txctl)
1609 struct sk_buff *skb = bf->bf_mpdu;
1610 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1611 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1612 struct ath_node *an = NULL;
1613 struct list_head bf_head;
1614 struct ath_desc *ds;
1615 struct ath_atx_tid *tid;
1616 struct ath_hw *ah = sc->sc_ah;
1620 frm_type = get_hw_packet_type(skb);
1621 fc = hdr->frame_control;
1623 INIT_LIST_HEAD(&bf_head);
1624 list_add_tail(&bf->list, &bf_head);
1628 ds->ds_data = bf->bf_buf_addr;
1630 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1631 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1633 ath9k_hw_filltxdesc(ah, ds,
1634 skb->len, /* segment length */
1635 true, /* first segment */
1636 true, /* last segment */
1637 ds); /* first descriptor */
1639 spin_lock_bh(&txctl->txq->axq_lock);
1641 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1642 tx_info->control.sta) {
1643 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1644 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1646 if (!ieee80211_is_data_qos(fc)) {
1647 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1651 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1653 * Try aggregation if it's a unicast data frame
1654 * and the destination is HT capable.
1656 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1659 * Send this frame as regular when ADDBA
1660 * exchange is neither complete nor pending.
1662 ath_tx_send_ht_normal(sc, txctl->txq,
1666 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1670 spin_unlock_bh(&txctl->txq->axq_lock);
1673 /* Upon failure caller should free skb */
1674 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1675 struct ath_tx_control *txctl)
1677 struct ath_wiphy *aphy = hw->priv;
1678 struct ath_softc *sc = aphy->sc;
1679 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1683 bf = ath_tx_get_buffer(sc);
1685 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1689 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1691 struct ath_txq *txq = txctl->txq;
1693 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1695 /* upon ath_tx_processq() this TX queue will be resumed, we
1696 * guarantee this will happen by knowing beforehand that
1697 * we will at least have to run TX completionon one buffer
1699 spin_lock_bh(&txq->axq_lock);
1700 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1701 ieee80211_stop_queue(sc->hw,
1702 skb_get_queue_mapping(skb));
1705 spin_unlock_bh(&txq->axq_lock);
1707 spin_lock_bh(&sc->tx.txbuflock);
1708 list_add_tail(&bf->list, &sc->tx.txbuf);
1709 spin_unlock_bh(&sc->tx.txbuflock);
1714 ath_tx_start_dma(sc, bf, txctl);
1719 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1721 struct ath_wiphy *aphy = hw->priv;
1722 struct ath_softc *sc = aphy->sc;
1723 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1724 int hdrlen, padsize;
1725 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1726 struct ath_tx_control txctl;
1728 memset(&txctl, 0, sizeof(struct ath_tx_control));
1731 * As a temporary workaround, assign seq# here; this will likely need
1732 * to be cleaned up to work better with Beacon transmission and virtual
1735 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1736 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1737 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1738 sc->tx.seq_no += 0x10;
1739 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1740 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1743 /* Add the padding after the header if this is not already done */
1744 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1746 padsize = hdrlen % 4;
1747 if (skb_headroom(skb) < padsize) {
1748 ath_print(common, ATH_DBG_XMIT,
1749 "TX CABQ padding failed\n");
1750 dev_kfree_skb_any(skb);
1753 skb_push(skb, padsize);
1754 memmove(skb->data, skb->data + padsize, hdrlen);
1757 txctl.txq = sc->beacon.cabq;
1759 ath_print(common, ATH_DBG_XMIT,
1760 "transmitting CABQ packet, skb: %p\n", skb);
1762 if (ath_tx_start(hw, skb, &txctl) != 0) {
1763 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1769 dev_kfree_skb_any(skb);
1776 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1779 struct ieee80211_hw *hw = sc->hw;
1780 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1781 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1782 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1783 int hdrlen, padsize;
1784 int frame_type = ATH9K_NOT_INTERNAL;
1786 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1789 hw = tx_info_priv->aphy->hw;
1790 frame_type = tx_info_priv->frame_type;
1793 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1794 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1795 kfree(tx_info_priv);
1796 tx_info->rate_driver_data[0] = NULL;
1799 if (tx_flags & ATH_TX_BAR)
1800 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1802 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1803 /* Frame was ACKed */
1804 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1807 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1808 padsize = hdrlen & 3;
1809 if (padsize && hdrlen >= 24) {
1811 * Remove MAC header padding before giving the frame back to
1814 memmove(skb->data + padsize, skb->data, hdrlen);
1815 skb_pull(skb, padsize);
1818 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1819 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1820 ath_print(common, ATH_DBG_PS,
1821 "Going back to sleep after having "
1822 "received TX status (0x%x)\n",
1823 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1824 SC_OP_WAIT_FOR_CAB |
1825 SC_OP_WAIT_FOR_PSPOLL_DATA |
1826 SC_OP_WAIT_FOR_TX_ACK));
1829 if (frame_type == ATH9K_NOT_INTERNAL)
1830 ieee80211_tx_status(hw, skb);
1832 ath9k_tx_status(hw, skb);
1835 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1836 struct ath_txq *txq,
1837 struct list_head *bf_q,
1838 int txok, int sendbar)
1840 struct sk_buff *skb = bf->bf_mpdu;
1841 unsigned long flags;
1845 tx_flags = ATH_TX_BAR;
1848 tx_flags |= ATH_TX_ERROR;
1850 if (bf_isxretried(bf))
1851 tx_flags |= ATH_TX_XRETRY;
1854 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1855 ath_tx_complete(sc, skb, tx_flags);
1856 ath_debug_stat_tx(sc, txq, bf);
1859 * Return the list of ath_buf of this mpdu to free queue
1861 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1862 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1863 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1866 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1869 struct ath_buf *bf_last = bf->bf_lastbf;
1870 struct ath_desc *ds = bf_last->bf_desc;
1872 u32 ba[WME_BA_BMP_SIZE >> 5];
1877 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1880 isaggr = bf_isaggr(bf);
1882 seq_st = ATH_DS_BA_SEQ(ds);
1883 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1887 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1888 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1897 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1898 int nbad, int txok, bool update_rc)
1900 struct sk_buff *skb = bf->bf_mpdu;
1901 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1902 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1903 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1904 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1908 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1910 tx_rateindex = ds->ds_txstat.ts_rateindex;
1911 WARN_ON(tx_rateindex >= hw->max_rates);
1913 tx_info_priv->update_rc = update_rc;
1914 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1915 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1917 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1918 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1919 if (ieee80211_is_data(hdr->frame_control)) {
1920 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1921 sizeof(tx_info_priv->tx));
1922 tx_info_priv->n_frames = bf->bf_nframes;
1923 tx_info_priv->n_bad_frames = nbad;
1927 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1928 tx_info->status.rates[i].count = 0;
1930 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1933 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1937 spin_lock_bh(&txq->axq_lock);
1939 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1940 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1942 ieee80211_wake_queue(sc->hw, qnum);
1946 spin_unlock_bh(&txq->axq_lock);
1949 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1951 struct ath_hw *ah = sc->sc_ah;
1952 struct ath_common *common = ath9k_hw_common(ah);
1953 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1954 struct list_head bf_head;
1955 struct ath_desc *ds;
1959 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1960 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1964 spin_lock_bh(&txq->axq_lock);
1965 if (list_empty(&txq->axq_q)) {
1966 txq->axq_link = NULL;
1967 txq->axq_linkbuf = NULL;
1968 spin_unlock_bh(&txq->axq_lock);
1971 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1974 * There is a race condition that a BH gets scheduled
1975 * after sw writes TxE and before hw re-load the last
1976 * descriptor to get the newly chained one.
1977 * Software must keep the last DONE descriptor as a
1978 * holding descriptor - software does so by marking
1979 * it with the STALE flag.
1984 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1985 spin_unlock_bh(&txq->axq_lock);
1988 bf = list_entry(bf_held->list.next,
1989 struct ath_buf, list);
1993 lastbf = bf->bf_lastbf;
1994 ds = lastbf->bf_desc;
1996 status = ath9k_hw_txprocdesc(ah, ds);
1997 if (status == -EINPROGRESS) {
1998 spin_unlock_bh(&txq->axq_lock);
2001 if (bf->bf_desc == txq->axq_lastdsWithCTS)
2002 txq->axq_lastdsWithCTS = NULL;
2003 if (ds == txq->axq_gatingds)
2004 txq->axq_gatingds = NULL;
2007 * Remove ath_buf's of the same transmit unit from txq,
2008 * however leave the last descriptor back as the holding
2009 * descriptor for hw.
2011 lastbf->bf_stale = true;
2012 INIT_LIST_HEAD(&bf_head);
2013 if (!list_is_singular(&lastbf->list))
2014 list_cut_position(&bf_head,
2015 &txq->axq_q, lastbf->list.prev);
2019 txq->axq_aggr_depth--;
2021 txok = (ds->ds_txstat.ts_status == 0);
2022 txq->axq_tx_inprogress = false;
2023 spin_unlock_bh(&txq->axq_lock);
2026 spin_lock_bh(&sc->tx.txbuflock);
2027 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2028 spin_unlock_bh(&sc->tx.txbuflock);
2031 if (!bf_isampdu(bf)) {
2033 * This frame is sent out as a single frame.
2034 * Use hardware retry status for this frame.
2036 bf->bf_retries = ds->ds_txstat.ts_longretry;
2037 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2038 bf->bf_state.bf_type |= BUF_XRETRY;
2039 ath_tx_rc_status(bf, ds, 0, txok, true);
2043 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2045 ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0);
2047 ath_wake_mac80211_queue(sc, txq);
2049 spin_lock_bh(&txq->axq_lock);
2050 if (sc->sc_flags & SC_OP_TXAGGR)
2051 ath_txq_schedule(sc, txq);
2052 spin_unlock_bh(&txq->axq_lock);
2056 static void ath_tx_complete_poll_work(struct work_struct *work)
2058 struct ath_softc *sc = container_of(work, struct ath_softc,
2059 tx_complete_work.work);
2060 struct ath_txq *txq;
2062 bool needreset = false;
2064 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2065 if (ATH_TXQ_SETUP(sc, i)) {
2066 txq = &sc->tx.txq[i];
2067 spin_lock_bh(&txq->axq_lock);
2068 if (txq->axq_depth) {
2069 if (txq->axq_tx_inprogress) {
2071 spin_unlock_bh(&txq->axq_lock);
2074 txq->axq_tx_inprogress = true;
2077 spin_unlock_bh(&txq->axq_lock);
2081 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2082 "tx hung, resetting the chip\n");
2083 ath9k_ps_wakeup(sc);
2084 ath_reset(sc, false);
2085 ath9k_ps_restore(sc);
2088 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2089 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2094 void ath_tx_tasklet(struct ath_softc *sc)
2097 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2099 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2101 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2102 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2103 ath_tx_processq(sc, &sc->tx.txq[i]);
2111 int ath_tx_init(struct ath_softc *sc, int nbufs)
2113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2116 spin_lock_init(&sc->tx.txbuflock);
2118 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2121 ath_print(common, ATH_DBG_FATAL,
2122 "Failed to allocate tx descriptors: %d\n", error);
2126 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2127 "beacon", ATH_BCBUF, 1);
2129 ath_print(common, ATH_DBG_FATAL,
2130 "Failed to allocate beacon descriptors: %d\n", error);
2134 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2143 void ath_tx_cleanup(struct ath_softc *sc)
2145 if (sc->beacon.bdma.dd_desc_len != 0)
2146 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2148 if (sc->tx.txdma.dd_desc_len != 0)
2149 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2152 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2154 struct ath_atx_tid *tid;
2155 struct ath_atx_ac *ac;
2158 for (tidno = 0, tid = &an->tid[tidno];
2159 tidno < WME_NUM_TID;
2163 tid->seq_start = tid->seq_next = 0;
2164 tid->baw_size = WME_MAX_BA;
2165 tid->baw_head = tid->baw_tail = 0;
2167 tid->paused = false;
2168 tid->state &= ~AGGR_CLEANUP;
2169 INIT_LIST_HEAD(&tid->buf_q);
2170 acno = TID_TO_WME_AC(tidno);
2171 tid->ac = &an->ac[acno];
2172 tid->state &= ~AGGR_ADDBA_COMPLETE;
2173 tid->state &= ~AGGR_ADDBA_PROGRESS;
2176 for (acno = 0, ac = &an->ac[acno];
2177 acno < WME_NUM_AC; acno++, ac++) {
2179 INIT_LIST_HEAD(&ac->tid_q);
2183 ac->qnum = ath_tx_get_qnum(sc,
2184 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2187 ac->qnum = ath_tx_get_qnum(sc,
2188 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2191 ac->qnum = ath_tx_get_qnum(sc,
2192 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2195 ac->qnum = ath_tx_get_qnum(sc,
2196 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2202 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2205 struct ath_atx_ac *ac, *ac_tmp;
2206 struct ath_atx_tid *tid, *tid_tmp;
2207 struct ath_txq *txq;
2209 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2210 if (ATH_TXQ_SETUP(sc, i)) {
2211 txq = &sc->tx.txq[i];
2213 spin_lock(&txq->axq_lock);
2215 list_for_each_entry_safe(ac,
2216 ac_tmp, &txq->axq_acq, list) {
2217 tid = list_first_entry(&ac->tid_q,
2218 struct ath_atx_tid, list);
2219 if (tid && tid->an != an)
2221 list_del(&ac->list);
2224 list_for_each_entry_safe(tid,
2225 tid_tmp, &ac->tid_q, list) {
2226 list_del(&tid->list);
2228 ath_tid_drain(sc, txq, tid);
2229 tid->state &= ~AGGR_ADDBA_COMPLETE;
2230 tid->state &= ~AGGR_CLEANUP;
2234 spin_unlock(&txq->axq_lock);